amaranth-boards/nmigen_boards/resources, branch main Board definitions for Amaranth HDL https://git.mciantyre.dev/amaranth-boards/atom?h=main 2023-02-03T05:37:00+00:00 Remove the deprecated `nmigen_boards` namespace. 2023-02-03T05:37:00+00:00 Catherine whitequark@whitequark.org 2023-02-03T05:35:40+00:00 urn:sha1:70cafaff98f58bf99138ccd848a630974da7d88e Rename nMigen to Amaranth HDL. 2021-12-10T08:30:37+00:00 whitequark whitequark@whitequark.org 2021-12-10T07:38:00+00:00 urn:sha1:b968cfade961a329c26035ef8bfdf3058e95a9f1 Factor out DDR3. 2021-06-13T19:34:27+00:00 S.J.R. van Schaik stephan@synkhronix.com 2021-06-01T06:09:21+00:00 urn:sha1:9d24c51197fdc176dcaeaa0a2156b1cdc75bf1ac [breaking-change] Factor out PS2Resource. 2021-06-03T14:53:08+00:00 S.J.R. van Schaik stephan@synkhronix.com 2021-06-03T14:53:08+00:00 urn:sha1:dbde179dc53e6cc3bdde0b6b00b31446367f5451 [breaking-change] Factor out VGAResource. 2021-05-31T08:51:32+00:00 S.J.R. van Schaik stephan@synkhronix.com 2021-05-31T08:51:32+00:00 urn:sha1:08b1b955b1fba1f776ff233a23eb98526a8d0c39 [breaking-change] Add `_n` suffix to argument names of pins with fixed inverters. 2020-11-26T14:50:00+00:00 GuzTech GuzTech@users.noreply.github.com 2020-11-26T14:50:00+00:00 urn:sha1:b40c3d6cb20081ff8941fc4addef92170ffb01a9 Note: this change does NOT affect pin functionality or naming, and does not require modifying your design. It does however affect some board files, where keywords corresponding to active low pins will have to be adjusted: SPIResource(0, cs="C1", ...) → SPIResource(0, cs_n="C1", ...) The new naming scheme will make it easier to write and audit board files by clearly marking inverted pins in resource factories, similarly to how `PinsN` indicates the same in bare resources. Fixes #129. resources.interface: allow SPIResource to be unidirectional. 2020-11-25T02:29:20+00:00 whitequark whitequark@whitequark.org 2020-11-24T22:26:53+00:00 urn:sha1:4bef280a80151161fc885ac46d2e22bf79d2cb2f See #104. Factor out I2C resource. 2020-11-05T06:52:12+00:00 awygle awygle@gmail.com 2020-11-05T06:52:12+00:00 urn:sha1:ec65568d91dca4ca2ff7da22b90ad6574bbad68a resources.memory: make cs pin optional for SDRAMResource 2020-09-06T22:58:25+00:00 marble cyber-murmel@users.noreply.github.com 2020-09-06T22:58:25+00:00 urn:sha1:71ddd72ad38de011b1aa54d472db91bb32408b8e resources: allow use of ULPI PHYs with active-low RST pins 2020-08-06T01:04:35+00:00 Katherine Temkin k@ktemkin.com 2020-07-30T00:07:25+00:00 urn:sha1:13b90ac5230081de0f94599ff56e4aa1c4ded7e7 Also, fixes a typo that affected PHYs with rst specified