From 6bbd2dd89f78f38f11ec497e34d4cddf8aae88dc Mon Sep 17 00:00:00 2001
From: slan <chezslan@gmail.com>
Date: Wed, 24 Feb 2021 08:46:34 +0200
Subject: arty_a7: add missing constraints

---
 nmigen_boards/arty_a7.py | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py
index 3f72f0a..73456b7 100644
--- a/nmigen_boards/arty_a7.py
+++ b/nmigen_boards/arty_a7.py
@@ -204,7 +204,11 @@ class ArtyA7Platform(Xilinx7SeriesPlatform):
                 "write_cfgmem -force -format bin -interface spix4 -size 16 "
                 "-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
             "add_constraints":
-                "set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
+                """
+                set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+                set_property CFGBVS VCCO [current_design]
+                set_property CONFIG_VOLTAGE 3.3 [current_design]
+                """
         }
         return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
 
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