From 8be37da521e8789726a53bd4e0c261c12e2ab22b Mon Sep 17 00:00:00 2001 From: Mariusz Glebocki Date: Tue, 25 Aug 2020 16:29:28 +0200 Subject: arty_a7: fix `rst` pin polarity. --- nmigen_boards/arty_a7.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'nmigen_boards/arty_a7.py') diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py index 7e7e628..9fb0842 100644 --- a/nmigen_boards/arty_a7.py +++ b/nmigen_boards/arty_a7.py @@ -18,7 +18,7 @@ class ArtyA7Platform(Xilinx7SeriesPlatform): resources = [ Resource("clk100", 0, Pins("E3", dir="i"), Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")), - Resource("rst", 0, Pins("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")), + Resource("rst", 0, PinsN("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")), *LEDResources(pins="H5 J5 T9 T10", attrs=Attrs(IOSTANDARD="LVCMOS33")), -- cgit v1.2.3