From 19cf06052230831e6d899aa3cf71539fe746a43e Mon Sep 17 00:00:00 2001
From: ECP5-PCIe <65254322+ECP5-PCIe@users.noreply.github.com>
Date: Thu, 16 Jul 2020 10:22:51 +0200
Subject: [breaking-change] Update SPI pin names.

The new names follow the OSHWA convention described at:
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
---
 nmigen_boards/genesys2.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'nmigen_boards/genesys2.py')

diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py
index 66525fd..b23976f 100644
--- a/nmigen_boards/genesys2.py
+++ b/nmigen_boards/genesys2.py
@@ -99,8 +99,8 @@ class Genesys2Platform(Xilinx7SeriesPlatform):
         Resource("audio_clk", 0,  # ADAU1761 MCLK
                  Pins("AK19", dir="o"), Attrs(IOSTANDARD="LVCMOS18")),
         SPIResource(0,  # OLED, SSD1306, 128 x 32
-                    cs="dummy-cs0", clk="AF17", mosi="Y15",
-                    miso="dummy-miso0", reset="AB17",
+                    cs="dummy-cs0", clk="AF17", copi="Y15",
+                    cipo="dummy-cipo0", reset="AB17",
                     attrs=Attrs(IOSTANDARD="LVCMOS18")),
         Resource("oled", 0,  # OLED, UG-2832HSWEG04
                  Subsignal("dc", Pins("AC17", dir="o")),
-- 
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