From 19cf06052230831e6d899aa3cf71539fe746a43e Mon Sep 17 00:00:00 2001
From: ECP5-PCIe <65254322+ECP5-PCIe@users.noreply.github.com>
Date: Thu, 16 Jul 2020 10:22:51 +0200
Subject: [breaking-change] Update SPI pin names.

The new names follow the OSHWA convention described at:
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
---
 nmigen_boards/mercury.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'nmigen_boards/mercury.py')

diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py
index 5daf802..c0bd107 100644
--- a/nmigen_boards/mercury.py
+++ b/nmigen_boards/mercury.py
@@ -40,19 +40,19 @@ class MercuryPlatform(XilinxSpartan3APlatform):
         # The serial interface and flash memory have a shared SPI bus.
         # FPGA is secondary.
         SPIResource("spi_serial", 0, role="device",
-            cs="P39", clk="P53", mosi="P46", miso="P51",
+            cs="P39", clk="P53", copi="P46", cipo="P51",
             attrs=Attrs(IOSTANDARD="LVTTL"),
         ),
 
         # FPGA is primary.
         *SPIFlashResources(0,
-            cs="P27", clk="P53", mosi="P46", miso="P51",
+            cs="P27", clk="P53", copi="P46", cipo="P51",
             attrs=Attrs(IOSTANDARD="LVTTL")
         ),
 
         # ADC over SPI- FPGA is primary.
         SPIResource("spi_adc", 0, role="host",
-            cs="P12", clk="P9", mosi="P10", miso="P21",
+            cs="P12", clk="P9", copi="P10", cipo="P21",
             attrs=Attrs(IOSTANDARD="LVTTL"),
         ),
 
-- 
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