From c7c637043817eae6f48c33b707b40c9c1b20f199 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 3 Oct 2019 05:54:12 +0000
Subject: Reorganize resource taxonomy.

The current hierarchy isn't particularly well suited to resources
like SDRAM or NOR flash, so make it much less fine-grained but easier
to use and less nitpicky.
---
 nmigen_boards/resources/interface.py | 72 ++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 nmigen_boards/resources/interface.py

(limited to 'nmigen_boards/resources/interface.py')

diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py
new file mode 100644
index 0000000..7ab0518
--- /dev/null
+++ b/nmigen_boards/resources/interface.py
@@ -0,0 +1,72 @@
+from nmigen.build import *
+
+
+__all__ = ["UARTResource", "IrDAResource", "SPIResource"]
+
+
+def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
+                 attrs=None):
+    io = []
+    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
+    if rts is not None:
+        io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1)))
+    if cts is not None:
+        io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1)))
+    if dtr is not None:
+        io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1)))
+    if dsr is not None:
+        io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1)))
+    if dcd is not None:
+        io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1)))
+    if ri is not None:
+        io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1)))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource.family(*args, default_name="uart", ios=io)
+
+
+def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
+    # Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
+    # be specified, and it is mapped to a logic level en subsignal.
+    assert (en is not None) ^ (sd is not None)
+
+    io = []
+    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
+    if en is not None:
+        io.append(Subsignal("en", Pins(en, dir="o", assert_width=1)))
+    if sd is not None:
+        io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1)))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource("irda", number, *io)
+
+
+def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None, attrs=None, role="host"):
+    assert role in ("host", "device")
+
+    io = []
+    if role == "host":
+        io.append(Subsignal("cs", PinsN(cs, dir="o")))
+        io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
+        io.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
+        io.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
+    else:  # device
+        io.append(Subsignal("cs", PinsN(cs, dir="i", assert_width=1)))
+        io.append(Subsignal("clk", Pins(clk, dir="i", assert_width=1)))
+        io.append(Subsignal("mosi", Pins(mosi, dir="i", assert_width=1)))
+        io.append(Subsignal("miso", Pins(miso, dir="oe", assert_width=1)))
+    if int is not None:
+        if role == "host":
+            io.append(Subsignal("int", Pins(int, dir="i")))
+        else:
+            io.append(Subsignal("int", Pins(int, dir="oe", assert_width=1)))
+    if reset is not None:
+        if role == "host":
+            io.append(Subsignal("reset", Pins(reset, dir="o")))
+        else:
+            io.append(Subsignal("reset", Pins(reset, dir="i", assert_width=1)))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource.family(*args, default_name="spi", ios=io)
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