From 71ddd72ad38de011b1aa54d472db91bb32408b8e Mon Sep 17 00:00:00 2001 From: marble Date: Mon, 7 Sep 2020 00:58:25 +0200 Subject: resources.memory: make cs pin optional for SDRAMResource --- nmigen_boards/resources/memory.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'nmigen_boards/resources/memory.py') diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py index 160f3df..064369f 100644 --- a/nmigen_boards/resources/memory.py +++ b/nmigen_boards/resources/memory.py @@ -103,13 +103,14 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, return Resource.family(*args, default_name="sram", ios=io) -def SDRAMResource(*args, clk, cke=None, cs, we, ras, cas, ba, a, dq, dqm=None, +def SDRAMResource(*args, clk, cke=None, cs=None, we, ras, cas, ba, a, dq, dqm=None, conn=None, attrs=None): io = [] io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1))) if cke is not None: io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, assert_width=1))) - io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1))) + if cs is not None: + io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1))) io.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1))) io.append(Subsignal("ras", PinsN(ras, dir="o", conn=conn, assert_width=1))) io.append(Subsignal("cas", PinsN(cas, dir="o", conn=conn, assert_width=1))) -- cgit v1.2.3