From 95c1760cc87770b9dba8997c08508541a8cbec95 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 2 Jul 2020 01:56:53 +0000 Subject: [breaking-change] resources.memory: add missing inversion on SRAMResource(dm=). The semantics should be that a high bit of data mask (UB#LB#) enables the write to the corresponding byte. --- nmigen_boards/resources/memory.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'nmigen_boards/resources/memory.py') diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py index b2be757..7f45cad 100644 --- a/nmigen_boards/resources/memory.py +++ b/nmigen_boards/resources/memory.py @@ -97,7 +97,7 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, io.append(Subsignal("a", Pins(a, dir="o", conn=conn))) io.append(Subsignal("d", Pins(d, dir="io", conn=conn))) if dm is not None: - io.append(Subsignal("dm", Pins(dm, dir="o", conn=conn))) # dm="LB# UB#" + io.append(Subsignal("dm", PinsN(dm, dir="o", conn=conn))) # dm="LB# UB#" if attrs is not None: io.append(attrs) return Resource.family(*args, default_name="sram", ios=io) -- cgit v1.2.3