From 65fc46c957174e877924c3f7d8e05a3006ff1a76 Mon Sep 17 00:00:00 2001 From: Katherine Temkin Date: Wed, 7 Oct 2020 19:52:19 -0600 Subject: genesys2: correctly specify I/O attributes for VADJ banks --- nmigen_boards/genesys2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'nmigen_boards') diff --git a/nmigen_boards/genesys2.py b/nmigen_boards/genesys2.py index b23976f..a82ceaa 100644 --- a/nmigen_boards/genesys2.py +++ b/nmigen_boards/genesys2.py @@ -24,7 +24,7 @@ class Genesys2Platform(Xilinx7SeriesPlatform): self._JP6 = JP6 def bank15_16_17_iostandard(self): - return "LVCMOS" + self._JP6 + return "LVCMOS" + self._JP6.replace('V', '') default_rst = "rst" default_clk = "clk" -- cgit v1.2.3