From 689a76207a61433b802ccdc96f5ffc3d07d81cec Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Mon, 10 Aug 2020 20:17:17 +0200 Subject: [breaking-change] Arty A7: rename cpu_reset resource to rst. (#102) It's now define properly as input and used as default reset. --- nmigen_boards/arty_a7.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'nmigen_boards') diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py index b1defe1..7e7e628 100644 --- a/nmigen_boards/arty_a7.py +++ b/nmigen_boards/arty_a7.py @@ -14,9 +14,11 @@ class ArtyA7Platform(Xilinx7SeriesPlatform): package = "csg324" speed = "1L" default_clk = "clk100" + default_rst = "rst" resources = [ Resource("clk100", 0, Pins("E3", dir="i"), Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")), + Resource("rst", 0, Pins("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")), *LEDResources(pins="H5 J5 T9 T10", attrs=Attrs(IOSTANDARD="LVCMOS33")), @@ -33,8 +35,6 @@ class ArtyA7Platform(Xilinx7SeriesPlatform): attrs=Attrs(IOSTANDARD="LVCMOS33") ), - Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")), - SPIResource(0, cs="C1", clk="F1", copi="H1", cipo="G1", attrs=Attrs(IOSTANDARD="LVCMOS33") -- cgit v1.2.3