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<title>icestorm/examples/hx8kboard, branch main</title>
<subtitle>Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
</subtitle>
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<updated>2022-09-15T10:32:45+00:00</updated>
<entry>
<title>Replaced instances of `arachne-pnr` with the `nextpnr-ice40`  equivalent</title>
<updated>2022-09-15T10:32:45+00:00</updated>
<author>
<name>Aki Van Ness</name>
<email>aki@lethalbit.net</email>
</author>
<published>2022-09-15T10:32:45+00:00</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>Some cleanups in verilog examples</title>
<updated>2017-01-09T20:21:15+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2017-01-09T20:21:15+00:00</published>
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</content>
</entry>
<entry>
<title>Fixed files with CRLF line endings</title>
<updated>2017-01-01T21:12:32+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2017-01-01T21:12:32+00:00</published>
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<id>urn:sha1:13e654fe2e9484aaddf69d9e2015722604418210</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Timing models for LP and HX devices</title>
<updated>2016-02-01T22:32:03+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2016-02-01T22:32:03+00:00</published>
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</content>
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<entry>
<title>added icetime -o/-r options</title>
<updated>2016-01-17T23:11:13+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2016-01-17T23:11:13+00:00</published>
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</content>
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<entry>
<title>Added icetime to examples</title>
<updated>2016-01-17T10:40:22+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2016-01-17T10:40:22+00:00</published>
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</content>
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<entry>
<title>Renamed IceBox .txt files to .asc files</title>
<updated>2016-01-01T14:08:41+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2016-01-01T14:08:41+00:00</published>
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<id>urn:sha1:804e47d8ff5651b579f6c43fcb96b569e0cbcdc5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge pull request #18 from esden/flex_example_make</title>
<updated>2015-12-30T18:00:54+00:00</updated>
<author>
<name>Clifford Wolf</name>
<email>clifford@clifford.at</email>
</author>
<published>2015-12-30T18:00:54+00:00</published>
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<id>urn:sha1:51067aff52eb958fb47b179328e3b1e1ef5d32eb</id>
<content type='text'>
[examples] Made the example Makefiles easier to reuse.</content>
</entry>
<entry>
<title>[examples] Added sudo prog target to prevent compiling the code as root. And made make clean more conservative.</title>
<updated>2015-12-30T11:40:20+00:00</updated>
<author>
<name>Piotr Esden-Tempski</name>
<email>piotr@esden.net</email>
</author>
<published>2015-12-30T11:40:20+00:00</published>
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</content>
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<entry>
<title>remove trailing tab in hx8kboard example verilog</title>
<updated>2015-12-29T19:53:43+00:00</updated>
<author>
<name>Max Bruckner</name>
<email>max@maxbruckner.de</email>
</author>
<published>2015-12-29T19:53:43+00:00</published>
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