icestorm/examples/iceblink, branch main Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered) https://git.mciantyre.dev/icestorm/atom?h=main 2022-09-15T10:32:45+00:00 Replaced instances of `arachne-pnr` with the `nextpnr-ice40` equivalent 2022-09-15T10:32:45+00:00 Aki Van Ness aki@lethalbit.net 2022-09-15T10:32:45+00:00 urn:sha1:ca43729f124466b816f922842353feeb3f6f8e84 Update README to be clearer 2018-07-03T20:19:58+00:00 Tim Ansell me@mith.ro 2018-07-03T20:19:58+00:00 urn:sha1:69d32b129bf61d5e9f24bc096d82562a7f4620c5 The example doesn't work out of the box with the iCEblink40-lp1k board. Squelch trailing whitespace 2017-08-01T12:43:15+00:00 Larry Doolittle ldoolitt@recycle.lbl.gov 2017-08-01T00:01:55+00:00 urn:sha1:b3d35ccadc745851514abc7d7aa26f41532ac914 Add missing .rpt file to iceblink example "make clean" 2017-04-23T14:00:41+00:00 Clifford Wolf clifford@clifford.at 2017-04-23T14:00:41+00:00 urn:sha1:587363b64a8b5d210a05dd6e5f91c9992db496b7 Some cleanups in verilog examples 2017-01-09T20:21:15+00:00 Clifford Wolf clifford@clifford.at 2017-01-09T20:21:15+00:00 urn:sha1:f920831e43c686dcaeca39c2481d5f22c014940f Fixed files with CRLF line endings 2017-01-01T21:12:32+00:00 Clifford Wolf clifford@clifford.at 2017-01-01T21:12:32+00:00 urn:sha1:13e654fe2e9484aaddf69d9e2015722604418210 Timing models for LP and HX devices 2016-02-01T22:32:03+00:00 Clifford Wolf clifford@clifford.at 2016-02-01T22:32:03+00:00 urn:sha1:81c33a343ffce5eab897d0a5a7d228bfcb08aaf4 Port example to iceblink40 board. 2016-01-31T11:03:11+00:00 Kalle Raiskila kraiskil@iki.fi 2016-01-31T11:01:18+00:00 urn:sha1:438c0b55aea79da73f9be6ace4ddf2b77b749774