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-rw-r--r--docs/source/format.rst11
-rw-r--r--docs/source/io_tile.rst22
-rw-r--r--docs/source/ultraplus.rst248
3 files changed, 137 insertions, 144 deletions
diff --git a/docs/source/format.rst b/docs/source/format.rst
index 4f88ae9..9240fef 100644
--- a/docs/source/format.rst
+++ b/docs/source/format.rst
@@ -26,11 +26,17 @@ The following commands are known:
| Opcode | Description |
+===================================+===================================+
| 0 | payload=1: Write CRAM Data |
+| +-----------------------------------+
| | payload=2: Read BRAM Data |
+| +-----------------------------------+
| | payload=3: Write BRAM Data |
+| +-----------------------------------+
| | payload=4: Read BRAM Data |
+| +-----------------------------------+
| | payload=5: Reset CRC |
+| +-----------------------------------+
| | payload=6: Wakeup |
+| +-----------------------------------+
| | payload=8: Reboot |
+-----------------------------------+-----------------------------------+
| 1 | Set bank number |
@@ -41,8 +47,11 @@ The following commands are known:
+-----------------------------------+-----------------------------------+
| 5 | Set internal oscillator frequency |
| | range |
+| +-----------------------------------+
| | payload=0: low |
+| +-----------------------------------+
| | payload=1: medium |
+| +-----------------------------------+
| | payload=2: high |
+-----------------------------------+-----------------------------------+
| 6 | Set bank width (16-bits, MSB |
@@ -55,7 +64,9 @@ The following commands are known:
| | first) |
+-----------------------------------+-----------------------------------+
| 9 | payload=0: Disable warm boot |
+| +-----------------------------------+
| | payload=16: Enable cold boot |
+| +-----------------------------------+
| | payload=32: Enable warm boot |
+-----------------------------------+-----------------------------------+
diff --git a/docs/source/io_tile.rst b/docs/source/io_tile.rst
index 12d09b6..1ed707b 100644
--- a/docs/source/io_tile.rst
+++ b/docs/source/io_tile.rst
@@ -327,11 +327,17 @@ configured as follows (bits listed from LSB to MSB):
| | | Parameter |
+=======================+=======================+=======================+
| 0 3 | PLLCONFIG_5 | Select PLL Type: |
+| | +-----------------------+
| | | 000 = DISABLED |
+| | +-----------------------+
| | | 010 = SB_PLL40_PAD |
+| | +-----------------------+
| | | 100 = SB_PLL40_2_PAD |
+| | +-----------------------+
| | | 110 = SB_PLL40_2F_PAD |
+| | +-----------------------+
| | | 011 = SB_PLL40_CORE |
+| | +-----------------------+
| | | 111 = |
| | | SB_PLL40_2F_CORE |
+-----------------------+-----------------------+-----------------------+
@@ -340,10 +346,14 @@ configured as follows (bits listed from LSB to MSB):
| 0 5 | PLLCONFIG_3 | |
+-----------------------+-----------------------+-----------------------+
| 0 5 | PLLCONFIG_5 | FEEDBACK_PATH |
+| | +-----------------------+
| | | 000 = "DELAY" |
+| | +-----------------------+
| | | 001 = "SIMPLE" |
+| | +-----------------------+
| | | 010 = |
| | | "PHASE_AND_DELAY" |
+| | +-----------------------+
| | | 110 = "EXTERNAL" |
+-----------------------+-----------------------+-----------------------+
| 0 2 | PLLCONFIG_9 | |
@@ -352,27 +362,39 @@ configured as follows (bits listed from LSB to MSB):
+-----------------------+-----------------------+-----------------------+
| 0 4 | PLLCONFIG_4 | DELAY_ADJ |
| | | USTMENT_MODE_FEEDBACK |
+| | +-----------------------+
| | | 0 = "FIXED" |
+| | +-----------------------+
| | | 1 = "DYNAMIC" |
+-----------------------+-----------------------+-----------------------+
| 0 4 | PLLCONFIG_9 | DELAY_ADJ |
| | | USTMENT_MODE_RELATIVE |
+| | +-----------------------+
| | | 0 = "FIXED" |
+| | +-----------------------+
| | | 1 = "DYNAMIC" |
+-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_6 | PLLOUT_SELECT |
| | | PLLOUT_SELECT_PORTA |
+| | +-----------------------+
| | | 00 = "GENCLK" |
+| | +-----------------------+
| | | 01 = "GENCLK_HALF" |
+| | +-----------------------+
| | | 10 = "SHIFTREG_90deg" |
+| | +-----------------------+
| | | 11 = "SHIFTREG_0deg" |
+-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_7 | |
+-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_2 | PLLOUT_SELECT_PORTB |
+| | +-----------------------+
| | | 00 = "GENCLK" |
+| | +-----------------------+
| | | 01 = "GENCLK_HALF" |
+| | +-----------------------+
| | | 10 = "SHIFTREG_90deg" |
+| | +-----------------------+
| | | 11 = "SHIFTREG_0deg" |
+-----------------------+-----------------------+-----------------------+
| 0 3 | PLLCONFIG_3 | |
diff --git a/docs/source/ultraplus.rst b/docs/source/ultraplus.rst
index 7a0640d..a09aaeb 100644
--- a/docs/source/ultraplus.rst
+++ b/docs/source/ultraplus.rst
@@ -32,98 +32,64 @@ of signals and configuration bits is documented below.
| **Signal Assignments**
-+----------+----------+----------+----------+----------+----------+
-| SB_MAC16 | DSP0 | DSP1 | DSP2 | DSP3 | IPCON4 |
-| port | | | | | |
-+==========+==========+==========+==========+==========+==========+
-| CLK | -- | -- | lutff_gl | -- | -- |
-| | | | obal/clk | | |
-+----------+----------+----------+----------+----------+----------+
-| CE | -- | -- | lutff_gl | -- | -- |
-| | | | obal/cen | | |
-+----------+----------+----------+----------+----------+----------+
-| C[7:0] | -- | -- | -- | l | -- |
-| | | | | utff\_[7 | |
-| | | | | :0]/in_3 | |
-+----------+----------+----------+----------+----------+----------+
-| C[15:8] | -- | -- | -- | l | -- |
-| | | | | utff\_[7 | |
-| | | | | :0]/in_1 | |
-+----------+----------+----------+----------+----------+----------+
-| A[7:0] | -- | -- | l | -- | -- |
-| | | | utff\_[7 | | |
-| | | | :0]/in_3 | | |
-+----------+----------+----------+----------+----------+----------+
-| A[15:8] | -- | -- | l | -- | -- |
-| | | | utff\_[7 | | |
-| | | | :0]/in_1 | | |
-+----------+----------+----------+----------+----------+----------+
-| B[7:0] | -- | l | -- | -- | -- |
-| | | utff\_[7 | | | |
-| | | :0]/in_3 | | | |
-+----------+----------+----------+----------+----------+----------+
-| B[15:8] | -- | l | -- | -- | -- |
-| | | utff\_[7 | | | |
-| | | :0]/in_1 | | | |
-+----------+----------+----------+----------+----------+----------+
-| D[7:0] | l | -- | -- | -- | -- |
-| | utff\_[7 | | | | |
-| | :0]/in_3 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| D[15:8] | l | -- | -- | -- | -- |
-| | utff\_[7 | | | | |
-| | :0]/in_1 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| IRSTTOP | -- | lutff_gl | -- | -- | -- |
-| | | obal/s_r | | | |
-+----------+----------+----------+----------+----------+----------+
-| IRSTBOT | lutff_gl | -- | -- | -- | -- |
-| | obal/s_r | | | | |
-+----------+----------+----------+----------+----------+----------+
-| ORSTTOP | -- | -- | -- | lutff_gl | -- |
-| | | | | obal/s_r | |
-+----------+----------+----------+----------+----------+----------+
-| ORSTBOT | -- | -- | lutff_gl | -- | -- |
-| | | | obal/s_r | | |
-+----------+----------+----------+----------+----------+----------+
-| AHOLD | -- | -- | lutf | -- | -- |
-| | | | f_0/in_0 | | |
-+----------+----------+----------+----------+----------+----------+
-| BHOLD | -- | lutf | -- | -- | -- |
-| | | f_0/in_0 | | | |
-+----------+----------+----------+----------+----------+----------+
-| CHOLD | -- | -- | -- | lutf | -- |
-| | | | | f_0/in_0 | |
-+----------+----------+----------+----------+----------+----------+
-| DHOLD | lutf | -- | -- | -- | -- |
-| | f_0/in_0 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| OHOLDTOP | -- | -- | -- | lutf | -- |
-| | | | | f_1/in_0 | |
-+----------+----------+----------+----------+----------+----------+
-| OHOLDBOT | lutf | -- | -- | -- | -- |
-| | f_1/in_0 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| A | -- | -- | -- | lutf | -- |
-| DDSUBTOP | | | | f_3/in_0 | |
-+----------+----------+----------+----------+----------+----------+
-| A | lutf | -- | -- | -- | -- |
-| DDSUBBOT | f_3/in_0 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| OLOADTOP | -- | -- | -- | lutf | -- |
-| | | | | f_2/in_0 | |
-+----------+----------+----------+----------+----------+----------+
-| OLOADBOT | lutf | -- | -- | -- | -- |
-| | f_2/in_0 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| CI | lutf | -- | -- | -- | -- |
-| | f_4/in_0 | | | | |
-+----------+----------+----------+----------+----------+----------+
-| O[31:0] | mult/ | mult/O | mult/O\ | mult/O\ | -- |
-| | O\_[7:0] | \_[15:8] | _[23:16] | _[31:24] | |
-+----------+----------+----------+----------+----------+----------+
-| CO | -- | -- | -- | -- | slf_op_0 |
-+----------+----------+----------+----------+----------+----------+
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| SB_MAC16 | DSP0 | DSP1 | DSP2 | DSP3 | IPCON4 |
+| port | | | | | |
++==========+=====================+=====================+=====================+=====================+=====================+
+| CLK | -- | -- | lutff_global/clk | -- | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| CE | -- | -- | lutff_global/cen | -- | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| C[7:0] | -- | -- | -- | lutff\_[7:0]/in_3 | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| C[15:8] | -- | -- | -- | lutff\_[7:0]/in_1 | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| A[7:0] | -- | -- | lutff\_[7:0]/in_3 | -- | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| A[15:8] | -- | -- | lutff\_[7:0]/in_1 | -- | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| B[7:0] | -- | lutff\_[7:0]/in_3 | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| B[15:8] | -- | lutff\_[7:0]/in_1 | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| D[7:0] | lutff\_[7:0]/in_3 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| D[15:8] | lutff\_[7:0]/in_1 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| IRSTTOP | -- | lutff_global/s_r | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| IRSTBOT | lutff_global/s_r | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| ORSTTOP | -- | -- | -- | lutff_global/s_r | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| ORSTBOT | -- | -- | lutff_global/s_r | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| AHOLD | -- | -- | lutff_0/in_0 | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| BHOLD | -- | lutff_0/in_0 | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| CHOLD | -- | -- | -- | lutff_0/in_0 | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| DHOLD | lutff_0/in_0 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| OHOLDTOP | -- | -- | -- | lutff_1/in_0 | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| OHOLDBOT | lutff_1/in_0 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| A | -- | -- | -- | lutff_3/in_0 | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| A | lutff_3/in_0 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| OLOADTOP | -- | -- | -- | lutff_2/in_0 | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| OLOADBOT | lutff_2/in_0 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| CI | lutff_4/in_0 | | | | |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| O[31:0] | mult/O\_[7:0] | mult/O\_[15:8] | mult/O\_[23:16] | mult/O\_[31:24] | -- |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
+| CO | -- | -- | -- | -- | slf_op_0 |
++----------+---------------------+---------------------+---------------------+---------------------+---------------------+
| **Configuration Bits**
@@ -141,58 +107,52 @@ bits are then located in IPConnect tile (0, 19) CBIT[6:3].
The full list of configuration bits, including the changes for the DSP
at (0, 15) are described in the table below.
-+-----------------------+-----------------------+-----------------------+
-| Parameter | Normal Position | DSP (0, 15) |
-| | | Changes |
-+=======================+=======================+=======================+
-| C_REG | DSP0.CBIT_0 | |
-+-----------------------+-----------------------+-----------------------+
-| A_REG | DSP0.CBIT_1 | |
-+-----------------------+-----------------------+-----------------------+
-| B_REG | DSP0.CBIT_2 | |
-+-----------------------+-----------------------+-----------------------+
-| D_REG | DSP0.CBIT_3 | |
-+-----------------------+-----------------------+-----------------------+
-| TOP_8x8_MULT_REG | DSP0.CBIT_4 | |
-+-----------------------+-----------------------+-----------------------+
-| BOT_8x8_MULT_REG | DSP0.CBIT_5 | |
-+-----------------------+-----------------------+-----------------------+
-| PIP | DSP0.CBIT_6 | |
-| ELINE_16x16_MULT_REG1 | | |
-+-----------------------+-----------------------+-----------------------+
-| PIP | DSP0.CBIT_7 | |
-| ELINE_16x16_MULT_REG2 | | |
-+-----------------------+-----------------------+-----------------------+
-| TOPOUTPUT_SELECT[0] | DSP1.CBIT_0 | |
-+-----------------------+-----------------------+-----------------------+
-| TOPOUTPUT_SELECT[1] | DSP1.CBIT_1 | (0, 19).CBIT_3 |
-+-----------------------+-----------------------+-----------------------+
-| TOPA | DSP1.CBIT\_[3:2] | (0, 19).CBIT\_[5:4] |
-| DDSUB_LOWERINPUT[1:0] | | |
-+-----------------------+-----------------------+-----------------------+
-| TOPADDSUB_UPPERINUT | DSP1.CBIT_4 | (0, 19).CBIT_6 |
-+-----------------------+-----------------------+-----------------------+
-| TOPAD | DSP1.CBIT\_[6:5] | |
-| DSUB_CARRYSELECT[1:0] | | |
-+-----------------------+-----------------------+-----------------------+
-| BOTOUTPUT_SELECT[0] | DSP1.CBIT_7 | |
-+-----------------------+-----------------------+-----------------------+
-| BOTOUTPUT_SELECT[1] | DSP2.CBIT_0 | |
-+-----------------------+-----------------------+-----------------------+
-| BOTA | DSP2.CBIT\_[2:1] | |
-| DDSUB_LOWERINPUT[1:0] | | |
-+-----------------------+-----------------------+-----------------------+
-| BOTADDSUB_UPPERINPUT | DSP2.CBIT_3 | |
-+-----------------------+-----------------------+-----------------------+
-| BOTAD | DSP2.CBIT\_[5:4] | |
-| DSUB_CARRYSELECT[1:0] | | |
-+-----------------------+-----------------------+-----------------------+
-| MODE_8x8 | DSP2.CBIT_6 | |
-+-----------------------+-----------------------+-----------------------+
-| A_SIGNED | DSP2.CBIT_7 | |
-+-----------------------+-----------------------+-----------------------+
-| B_SIGNED | DSP3.CBIT_0 | |
-+-----------------------+-----------------------+-----------------------+
++----------------------------+-----------------------+-----------------------+
+| Parameter | Normal Position | DSP (0, 15) |
+| | | Changes |
++============================+=======================+=======================+
+| C_REG | DSP0.CBIT_0 | |
++----------------------------+-----------------------+-----------------------+
+| A_REG | DSP0.CBIT_1 | |
++----------------------------+-----------------------+-----------------------+
+| B_REG | DSP0.CBIT_2 | |
++----------------------------+-----------------------+-----------------------+
+| D_REG | DSP0.CBIT_3 | |
++----------------------------+-----------------------+-----------------------+
+| TOP_8x8_MULT_REG | DSP0.CBIT_4 | |
++----------------------------+-----------------------+-----------------------+
+| BOT_8x8_MULT_REG | DSP0.CBIT_5 | |
++----------------------------+-----------------------+-----------------------+
+| PIPELINE_16x16_MULT_REG1 | DSP0.CBIT_6 | |
++----------------------------+-----------------------+-----------------------+
+| PIPELINE_16x16_MULT_REG2 | DSP0.CBIT_7 | |
++----------------------------+-----------------------+-----------------------+
+| TOPOUTPUT_SELECT[0] | DSP1.CBIT_0 | |
++----------------------------+-----------------------+-----------------------+
+| TOPOUTPUT_SELECT[1] | DSP1.CBIT_1 | (0, 19).CBIT_3 |
++----------------------------+-----------------------+-----------------------+
+| TOPADDSUB_LOWERINPUT[1:0] | DSP1.CBIT\_[3:2] | (0, 19).CBIT\_[5:4] |
++----------------------------+-----------------------+-----------------------+
+| TOPADDSUB_UPPERINUT | DSP1.CBIT_4 | (0, 19).CBIT_6 |
++----------------------------+-----------------------+-----------------------+
+| TOPADDSUB_CARRYSELECT[1:0] | DSP1.CBIT\_[6:5] | |
++----------------------------+-----------------------+-----------------------+
+| BOTOUTPUT_SELECT[0] | DSP1.CBIT_7 | |
++----------------------------+-----------------------+-----------------------+
+| BOTOUTPUT_SELECT[1] | DSP2.CBIT_0 | |
++----------------------------+-----------------------+-----------------------+
+| BOTADDSUB_LOWERINPUT[1:0] | DSP2.CBIT\_[2:1] | |
++----------------------------+-----------------------+-----------------------+
+| BOTADDSUB_UPPERINPUT | DSP2.CBIT_3 | |
++----------------------------+-----------------------+-----------------------+
+| BOTADDSUB_CARRYSELECT[1:0] | DSP2.CBIT\_[5:4] | |
++----------------------------+-----------------------+-----------------------+
+| MODE_8x8 | DSP2.CBIT_6 | |
++----------------------------+-----------------------+-----------------------+
+| A_SIGNED | DSP2.CBIT_7 | |
++----------------------------+-----------------------+-----------------------+
+| B_SIGNED | DSP3.CBIT_0 | |
++----------------------------+-----------------------+-----------------------+
Lattice document a limited number of supported configurations in the ICE
Technology Library document, and Lattice's EDIF parser will reject
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 16:52:34 +0000