diff options
Diffstat (limited to 'icebox/icebox_hlc2asc.py')
| -rwxr-xr-x | icebox/icebox_hlc2asc.py | 52 |
1 files changed, 32 insertions, 20 deletions
diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index 3f3df90..08b5556 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -509,7 +509,6 @@ def logic_expression_to_lut(s, args): for j in range(len(args)))) else '0' for i in range(1 << len(args))) - class ParseError(Exception): pass @@ -533,7 +532,9 @@ class Main: and len(fields[1]) >= 2 and fields[1][0] == '"' \ and fields[1][-1] == '"' \ and self.ic is None and self.device is None: - self.device = fields[1][1:-1] + self.device = fields[1][1:-1].lower() + if self.device.startswith('lp') or self.device.startswith('hx'): + self.device = self.device[2:] if self.device == '1k': self.ic = icebox.iceconfig() self.ic.setup_empty_1k() @@ -702,14 +703,6 @@ class Tile: continue add_entry(entry, bits) - # Let the routing bits be specified in both a->b and b->a direction. - for bits, *entry in self.db: - if not ic.tile_has_entry(x, y, (bits, *entry)): - continue - if entry[0] != "routing": - continue - add_entry((entry[0], entry[2], entry[1]), bits) - self.buffers = [] self.routings = [] self.bits_set = set() @@ -749,11 +742,19 @@ class Tile: bits_set.add((int(match.group(2)), int(match.group(3)))) if set.intersection(bits_set, bits_clear): - raise ValueError("trying to set/clear the same bit(s) at once") + raise ValueError( + "trying to set/clear the same bit(s) at once set:{} clear:{}".format( + bits_set, bits_clear)) if set.intersection(bits_set, self.bits_cleared) or \ set.intersection(bits_clear, self.bits_set): - raise ParseError("conflicting bits") + raise ParseError("""\ +conflicting bits {} + setting:{:<30} - current clear:{} +clearing:{:<30} - current set :{}""".format( + bits, + str(bits_set), self.bits_cleared, + str(bits_clear), self.bits_set)) self.bits_set.update(bits_set) self.bits_cleared.update(bits_clear) @@ -776,7 +777,7 @@ class Tile: if (src, dst) not in self.buffers: self.buffers.append((src, dst)) self.apply_directive('buffer', src, dst) - elif len(fields) == 3 and fields[1] == '<->': + elif len(fields) == 3 and fields[1] == '~>': src = untranslate_netname(self.x, self.y, self.ic.max_x - 1, self.ic.max_y - 1, fields[0]) @@ -787,7 +788,7 @@ class Tile: if (src, dst) not in self.routings: self.routings.append((src, dst)) self.apply_directive('routing', src, dst) - elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) else: @@ -831,8 +832,19 @@ class LogicCell: if fields[0] == 'lut' and len(fields) == 2 and self.lut_bits is None: self.lut_bits = fields[1] elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=': - self.lut_bits = logic_expression_to_lut( - ' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3')) + m = re.match("([0-9]+)'b([01]+)", fields[2]) + if m: + lut_bits = m.group(2) + if len(lut_bits) != int(m.group(1)): + raise ParseError + m = len(lut_bits) + if m < 16: + lut_bits = (16-m) * "0" + lut_bits + # Verilog 16'bXXXX is MSB first but the bitstream wants LSB. + self.lut_bits = lut_bits[::-1] + else: + self.lut_bits = logic_expression_to_lut( + ' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3')) elif fields == ['enable_carry']: self.seq_bits[0] = '1' elif fields == ['enable_dff']: @@ -841,11 +853,11 @@ class LogicCell: self.seq_bits[2] = '1' elif fields == ['async_setreset']: self.seq_bits[3] = '1' - elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) return - elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'): prefix = 'lutff_%d/' % self.index # Strip prefix if it is given @@ -1002,10 +1014,10 @@ class IOBlock: == ("padin_glb_netwk", fields[2][10:])] assert len(bit) == 1 self.tile.ic.extra_bits.add(bit[0]) - elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) - elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'): prefix = 'io_%d/' % self.index # Strip prefix if it is given |