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Diffstat (limited to 'icefuzz/tests/sb_io_i3c.rpt')
| -rw-r--r-- | icefuzz/tests/sb_io_i3c.rpt | 108 |
1 files changed, 108 insertions, 0 deletions
diff --git a/icefuzz/tests/sb_io_i3c.rpt b/icefuzz/tests/sb_io_i3c.rpt new file mode 100644 index 0000000..0b76167 --- /dev/null +++ b/icefuzz/tests/sb_io_i3c.rpt @@ -0,0 +1,108 @@ +# ****************************************************************************** + +# iCEcube Static Timer + +# Version: 2017.08.27940 + +# Build Date: Sep 12 2017 08:03:55 + +# File Generated: Jan 13 2018 18:40:35 + +# Purpose: Timing Report with critical paths info + +# Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved. + +# ****************************************************************************** + +Device: iCE40UP5KUP5K +Derating factors (Best:Typical:Worst) :- ( 1 : 1 : 1 ) +Derating factor used to generate this timing report: Worst +Based on the following operating conditions +Junction Temperature(degree Celsius): 0 +Core Voltage(V): -1 +Process Corner: Worst +NOTE: +Please check both worst-case and best-case scenarios for "Setup Times" +and "Hold Times" checks +Maximum Operating Frequency is: N/A + + + ##################################################################### + 3::Datasheet Report + +All values are in Picoseconds + ===================================================================== + + 3.1::Setup Times + ---------------- + +Data Port Clock Port Setup Times Clock Reference:Phase +--------- ---------- ----------- --------------------- + + + 3.2::Clock to Out + ----------------- + +Data Port Clock Port Clock to Out Clock Reference:Phase +--------- ---------- ------------ --------------------- + + + 3.3::Pad to Pad + --------------- + +Port Name (Input) Port Name (Output) Pad to Pad +----------------- ------------------ ---------- + + + 3.4::Hold Times + --------------- + +Data Port Clock Port Hold Times Clock Reference:Phase +--------- ---------- ---------- --------------------- + + + 3.5::Minimum Clock to Out + ------------------------- + +Data Port Clock Port Minimum Clock to Out Clock Reference:Phase +--------- ---------- -------------------- --------------------- + + + 3.6::Minimum Pad To Pad + ----------------------- + +Port Name (Input) Port Name (Output) Minimum Pad To Pad +----------------- ------------------ ------------------ + +===================================================================== + End of Datasheet Report +##################################################################### + +##################################################################### + 6::Path Details for DataSheet +===================================================================== + + + +===================================================================== + End of Path Details for Datasheet +##################################################################### + +##################################################################### + Detailed Setup Report for all timing paths +===================================================================== +===================================================================== + End of Detailed Setup Report for all timing paths +##################################################################### + +##################################################################### + Detailed Hold Report for all timing paths +===================================================================== +===================================================================== + End of Detailed Hold Report for all timing paths +##################################################################### + +##################################################################### + End of Timing Report +##################################################################### + |