aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2018-01-26Working DSP timing analysisDavid Shah
2018-01-26Work on timing analysis of DSPsDavid Shah
2018-01-23Parse extra cells in icetimeDavid Shah
2018-01-22More DSP timing fuzzing, start adding new tiles to icetimeDavid Shah
2018-01-22Seperate different DSP configs in timing dataDavid Shah
2018-01-20Fix 5k timing dataDavid Shah
2018-01-16Merge pull request #116 from daveshah1/up5k_misc_fixesClifford Wolf
Miscellaneous UltraPlus fixes and improvements
2018-01-16Add example for 5k UWG30 packageDavid Shah
2018-01-16I³C IO reverse engineered and documentedDavid Shah
2018-01-16Add 5k UWG30 ieren data to dbDavid Shah
2018-01-16Remove seperate 5k RAM DB and share with 8k insteadDavid Shah
This should ensure that the 5k RAM routing entries are now complete, fixing #115
2018-01-16Add pinout for 5k UWG30 packageDavid Shah
2018-01-16Add SPI enable bits to docsDavid Shah
2018-01-16HFOSC trimming infoDavid Shah
2018-01-16New UltraPlus corner tracing algorithmDavid Shah
2018-01-16Misc routing tweaksDavid Shah
2018-01-16Figure out missing SPI config bits, and add to chipdbDavid Shah
2018-01-02Add "iceprog -e"Clifford Wolf
2017-12-31Merge pull request #113 from cr1901/nosleepClifford Wolf
Add option to `icepack` to disable SPI Deep Power-Down command in bitstream.
2017-12-31Enable writing nosleep config bit into output bitstream.William D. Jones
2017-12-31Add nosleep field to FpgaConfig- read_bits recognizes the option.William D. Jones
2017-12-09Merge pull request #112 from mithro/patch-2Clifford Wolf
Creating COPYING file.
2017-12-08Creating COPYING file.Tim Ansell
So GitHub automatically detects the license of the repo.
2017-11-28Merge pull request #110 from daveshah1/up5k_ipClifford Wolf
UltraPlus Hard IP and icetime Support
2017-11-28Whitespace fixesDavid Shah
2017-11-28Add uncommitted changes and tidy up some filesDavid Shah
2017-11-26Chipdb fix for hard IPDavid Shah
2017-11-25Add note about glitch filterDavid Shah
2017-11-24Add UltraPlus IP to chipdbDavid Shah
2017-11-24Initial 5k support in icetime (no support for new cells yet)David Shah
2017-11-24Preparations for 5k icetimeDavid Shah
2017-11-24Documented I2C/SPI/LEDDA_IPDavid Shah
2017-11-24All 5k IP tracedDavid Shah
2017-11-24Work on UltraPlus IP tracingDavid Shah
2017-11-23Begin I2C/SPI IP reverse engineeringDavid Shah
2017-11-21Merge pull request #109 from daveshah1/up5kClifford Wolf
Support for new UltraPlus features
2017-11-20Tidy up 5k examplesDavid Shah
2017-11-20Fix whitespace and a couple of typosDavid Shah
2017-11-19Add UltraPlus info to docsDavid Shah
2017-11-19Merge branch 'master' into up5kDavid Shah
2017-11-19Add BeagleWire linkClifford Wolf
2017-11-18Merge branch 'master' into up5kDavid Shah
2017-11-18Merge commit '05440e4'Clifford Wolf
2017-11-18Add all cf_bits and pullup strength notesDavid Shah
2017-11-18Update udev rule in docs/index.htmlClifford Wolf
2017-11-18Corrections and changes to UltraPlus docDavid Shah
2017-11-18Merge branch 'master' into up5kDavid Shah
2017-11-17Add missing 5k BRAM bitsDavid Shah
2017-11-17Make 5k db as a default targetDavid Shah
2017-11-17Remove non-existing routing resources (5k)David Shah
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-27 01:39:55 +0000