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2022-03-29Merge pull request #294 from YosysHQ/gatecat/lut-false-pathgatecat
icetime: Ignore false paths through LUTs based on function
2022-03-29icetime: Ignore false paths through LUTs based on functiongatecat
Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-25Merge pull request #293 from YosysHQ/gatecat/cb121-fixgatecat
icebox: cb121 does have a PLL
2022-03-25icebox: cb121 does have a PLLgatecat
Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-05icetime: indent with tabsMaik Merten
2022-03-05icetime PCF parsing: handle -pullup and -pullup_resistor in set_io constraintsMaik Merten
2022-01-22Merge pull request #289 from osresearch/bitstream-prgatecat
docs/format.html: document bram/cram read-back commands
2022-01-22docs/format.html: document bram/cram read-back commandsTrammell Hudson
The Lattice tools use these additional commands to read-back the BRAM and CRAM after programming to validate that it was written correctly. `iceprog` doesn't use this right now, so this is just for documentation purposes. Signed-off-by: Trammell Hudson <hudson@trmm.net>
2022-01-02Merge pull request #287 from projf/update-urlCatherine
Update URL for web site.
2021-12-17iceprog: Use open-drain output to drive SS and Reset lineSylvain Munaut
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-12-17iceprog: Improve reset to disable both CRM and QPISylvain Munaut
It's hard to cover 100% of cases, but this seems to improve probability that a reset works, at least for me on the icebreaker. Some other flash have a different QPI disable command though :/ Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-12-17iceprog: Add option that set QE=1 bit in SR2Sylvain Munaut
This is useful when testing litex SoC that rely on that bit being set The setting is non-volatile so it only needs to be done once in case you happen to have used a flash chip that's not by default QE=1 (This has been designed for winbond flash. Others might use different bit ...) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-11-28Update URL for web site.Will Green
2021-09-06Merge pull request #282 from jkiv/iceprog-ignorig-fixMiodrag Milanović
[iceprog] Fixed typo in error message: "Ignorig"
2021-09-06Update variable name to PYTHON3Miodrag Milanovic
2021-09-06Merge pull request #239 from xobs/python-bin-nameMiodrag Milanović
Use $(PYTHON) in Makefiles instead of `python3`
2021-09-06Fixes for macOSMiodrag Milanovic
2021-08-30Merge pull request #276 from esden/progressClaire Xen
iceprog: Add write and read progress indication.
2021-05-03[iceprog] Fixed typo in error message: "Ignorig"Jon Kivinen
2021-03-09Use --recursive for nextpnr clonegatecat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05Merge pull request #279 from YosysHQ/update-gitignorewhitequark
Add more build products to .gitignore
2021-03-05Add more build products to .gitignore.whitequark
2021-02-05Add an option (-p) to force use of SB_PLL40_PADDavid Williams
When a clock is applied to a dedicated clock pin, SB_PLL40_CORE is no longer the correct primitive to use. Also the name of the clock input must be PACKAGEPIN (rather than REFERENCECLK)
2021-01-16iceprog: Add write and read progress indication.Piotr Esden-Tempski
2020-12-04Merge pull request #275 from nils1603/feature/ip_support_u4kDavid Shah
added I2C and SPI for u4k to database
2020-12-04added I2C and SPI for u4k to databaseNils Albartus
2020-08-19Fix links and email addr in index.htmlClaire Wolf
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-19Use YosysHQ in index.htmlClaire Wolf
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-19Use Claire in index.htmlClaire Wolf
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-08Merge pull request #264 from YosysHQ/mmicko/improvementsMiodrag Milanović
Support rest of parts by icetime
2020-07-08Enable rest of lattice parts in icetimeMiodrag Milanovic
2020-07-08Prevent rebuilding timing filesMiodrag Milanovic
2020-07-02Merge pull request #263 from YosysHQ/fix_vlog_up5kDavid Shah
Fix icebox_vlog for up5k
2020-06-29Fix icebox_vlog for up5kDavid Shah
Since ce1d811, SHIFTREG_DIV_MODE is now 2 bits for the up5k Signed-off-by: David Shah <dave@ds0.me>
2020-06-26Merge pull request #262 from whitequark/icebram-fixclairexen
Fix icebram
2020-06-26icebram: add WASI platform support.whitequark
2020-06-26icebram: refactor seeding logic.whitequark
2020-06-26Revert "Make icebram deterministic"whitequark
This reverts commit 2679c91b8a158aa4aca49dd726955e8c63cf7bef.
2020-06-25Merge pull request #257 from smunaut/ice40_shiftreg_div_modeClaire Wolf
icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE
2020-06-25Merge pull request #261 from whitequark/icepack-usageClaire Wolf
icepack: show program name in usage
2020-06-25Merge pull request #260 from whitequark/patch-1Claire Wolf
Make icebram deterministic
2020-06-25Merge pull request #254 from per-gron/fix-oobClaire Wolf
Fix array out of bounds access bug
2020-06-25Merge pull request #253 from SolraBizna/dummy-header-targetsClaire Wolf
Use -MP to eliminate one way that -MD can fatally confuse make
2020-06-25Merge pull request #256 from emaste/masterClaire Wolf
icetime: avoid string + int Clang warning
2020-06-24icepack: show program name in usage.whitequark
2020-06-23Make icebram deterministicwhitequark
2020-06-03icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5kSylvain Munaut
This allows selection of the div-by-5 mode of the PLL. This bit can't be fuzzed because it's not supported by the lattice tools at all ... This only works for sure on the UP5k. I tested HX8k and it didn't support it, so I'm only adding this on the known working FPGA. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-05-28icetime: avoid string + int Clang warningEd Maste
Clang warns that "adding 'int' to a string does not append to the string". Although a false positive it's trivially avoided by using the array index equivalent &PREFIX[1].
2020-05-25Fix array out of bounds access bugPer Grön
This is triggered for example when icetime is invoked with an empty design.
2020-05-09Add -MP to CFLAGS and CXXFLAGS, making it harder for make to get confused ↵Solra Bizna
out of even trying to build
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