| Age | Commit message (Collapse) | Author |
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I get this failure when building the up5k_rgb example:
ERROR: Max frequency for clock 'clk': 38.87 MHz (FAIL at 48.00 MHz)
(Tested with yosys 0.23 and nextpnr 0.4)
Annotate the clk line frequency to fix this.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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The example doesn't work out of the box with the iCEblink40-lp1k board.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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[examples] Made the example Makefiles easier to reuse.
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made make clean more conservative.
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remove trailing tab in hx8kboard example verilog
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