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hlc: parse '.sym>' to track signal names from HLC to ASC
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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'self.lut_bits is None' was always false. The _lut_ keyword is used by asc2hlc, so when converting asc->hlc->asc the lut_bits were always all zeros.
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Previously the 1k global networks were hard coded. This now uses the
values from the given part.
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icebox_hlc2asc: Allow data of ram to use verilog literal format
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Current code fails with the following;
```
Parse error in line 94:
span4_y3_g15_6 -> local_g0_3 -> D_OUT_0
```
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icebox_hlc2asc: Allow truth tables to be specified as init string.
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Remove bidir stuff in HLC
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As mentioned in ca6b2d9ebd521ecec58b9b5627c9380355adeab1, the 'routing'
switches are not actually bidirectional. This makes the '<->' specifier
very misleading.
Instead use '~>' to differentiate it from the 'buffer' switches.
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See ca6b2d9ebd521ecec58b9b5627c9380355adeab1.
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Examples;
```hlc
lutff_5 {
# - Parameters -------
# LUT_INIT = 0111111110000000
local_g3_4 -> lutff_5/in_0
local_g0_6 -> lutff_5/in_1
local_g2_7 -> lutff_5/in_2
lutff_5/out -> span4_x3_g12_11
lutff_5/out -> local_g3_5 -> lutff_5/in_3
out = 16'b0111111110000000
enable_dff
}
```
```hlc
lutff_4 {
local_g3_5 -> lutff_4/in_2
lutff_4/out -> span12_y12_g6_0
out = 16'b0000000000010000
enable_dff
}
```
```hlc
lutff_2 {
# - Parameters -------
# LUT_INIT = 01
lutff_2/out -> span12_y12_g8_0
lutff_2/out -> span12_x2_g14_0
lutff_2/out -> local_g0_2 -> lutff_2/in_0
out = 2'b01
enable_dff
}
```
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Now;
-----------------
Parse error in line 364:
span4_y9_g7_10 <-> span4_x3_g13_5
conflicting bits ['!B12[8]', '!B12[9]', 'B12[10]']
setting:{(12, 10)} - current clear:{(12, 10), (12, 8)}
clearing:{(12, 9), (12, 8)} - current set :{(12, 9)}
-----------------
Previously;
-----------------
File "icebox_hlc2asc.py", line 742, in apply_directive
self.set_bits(bits)
File "icebox_hlc2asc.py", line 762, in set_bits
raise ParseError("conflicting bits")
TypeError: __init__() takes 1 positional argument but 2 were given
-----------------
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Previously;
```
self.apply_directive('buffer', src, dst)
File "/usr/local/google/home/tansell/work/catx/vtr/env/conda/bin/icebox_hlc2asc", line 698, in apply_directive
bits, = [entry[0] for entry in self.db if entry[1:] == fields]
ValueError: not enough values to unpack (expected 1, got 0)
```
Now:
```
Parse error in line 2108:
span12_y4_g14_0 -> span4_y4_g11_7 <-> span4_x7_g4_0
No bit pattern for ['buffer', 'sp12_h_r_11', 'sp4_h_r_7'] in LogicTile(1k, 7, 4)
```
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IE
```
lutff_1 {
lutff_1/out -> local_g2_1 -> lutff_1/in_0
local_g2_2 -> lutff_1/in_3
local_g2_7 -> lutff_1/in_2
}
```
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Kind of fixes #145.
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# Conflicts:
# icebox/Makefile
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