| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-02-07 | Generate chip database HTML | Miodrag Milanovic | |
| 2025-01-20 | Do not add wires for module ports | Miodrag Milanovic | |
| 2024-12-11 | Resolve warning with python 3.12 | Miodrag Milanovic | |
| 2023-02-01 | icebox: Add PLL ICEGATE function | Sylvain Munaut | |
| Only tested on UP5k. For others, it was just deduced. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||
| 2022-03-25 | icebox: cb121 does have a PLL | gatecat | |
| Signed-off-by: gatecat <gatecat@ds0.me> | |||
| 2021-09-06 | Update variable name to PYTHON3 | Miodrag Milanovic | |
| 2021-09-06 | Merge pull request #239 from xobs/python-bin-name | Miodrag Milanović | |
| Use $(PYTHON) in Makefiles instead of `python3` | |||
| 2021-09-06 | Fixes for macOS | Miodrag Milanovic | |
| 2020-12-04 | added I2C and SPI for u4k to database | Nils Albartus | |
| 2020-06-29 | Fix icebox_vlog for up5k | David Shah | |
| Since ce1d811, SHIFTREG_DIV_MODE is now 2 bits for the up5k Signed-off-by: David Shah <dave@ds0.me> | |||
| 2020-06-03 | icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE on UP5k | Sylvain Munaut | |
| This allows selection of the div-by-5 mode of the PLL. This bit can't be fuzzed because it's not supported by the lattice tools at all ... This only works for sure on the UP5k. I tested HX8k and it didn't support it, so I'm only adding this on the known working FPGA. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||
| 2020-04-14 | Make sure that scripts find files on final install | Miodrag Milanovic | |
| 2020-04-10 | icebox: fix missing DESTDIR for icebox_chipdb | eine | |
| 2020-04-10 | Support custom PROGRAM_PREFIX | Miodrag Milanovic | |
| 2019-10-22 | icebox: use $(PYTHON) variable in Makefile | Sean Cross | |
| Allow `python` to be provided by an interpreter other than `python3`. Signed-off-by: Sean Cross <sean@xobs.io> | |||
| 2019-08-08 | Only dump memory initialization in icebox_vlog if present in ASC file, fixes ↵ | Clifford Wolf | |
| #228 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||
| 2019-07-03 | up5k: Fix TOPADDSUB_CARRYSELECT_0 override where it swaps with osc trimming | David Shah | |
| Signed-off-by: David Shah <dave@ds0.me> | |||
| 2019-06-10 | add RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | |
| 2019-06-08 | icebox_vlog: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_stat: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_maps: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_html: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_hlc2asc: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_explain: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_diff: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_colbuf: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox_asc2hlc: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox: Use cached re functions | Michael Buesch | |
| 2019-06-08 | icebox: Add helper functions to LRU cache regular expression results | Michael Buesch | |
| 2019-06-08 | icebox: Use LRU cache for often called function tile_has_net() | Michael Buesch | |
| 2019-02-22 | u4k: add SMCCLK cell location | Simon Schubert | |
| icecube uses SMCCLK.CLK to "legalize" output cells. Unclear what this is for, but it appears in almost all outputs. | |||
| 2019-02-22 | iCE40 Ultra = iCE5LP = u4k port | Simon Schubert | |
| 2018-10-10 | Merge pull request #178 from elmsfu/hlc/add_symbols_support | Clifford Wolf | |
| hlc: parse '.sym>' to track signal names from HLC to ASC | |||
| 2018-08-28 | Add support for cm36 and swg25tr lm4k packages. | Andrew Wygle | |
| 2018-08-09 | Add 5k support to hlc2asc. | Keith Rothman | |
| Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||
| 2018-07-26 | icebox: parse '.sym>' HLC to track signal names | Elms | |
| 2018-07-19 | icebox_hlc2asc: fix _lut_ keyword parsing | Elms | |
| 'self.lut_bits is None' was always false. The _lut_ keyword is used by asc2hlc, so when converting asc->hlc->asc the lut_bits were always all zeros. | |||
| 2018-07-19 | Spelling fixes in messages | Larry Doolittle | |
| 2018-07-16 | hlc: Use glb_network for current device. | Tim 'mithro' Ansell | |
| Previously the 1k global networks were hard coded. This now uses the values from the given part. | |||
| 2018-07-10 | Merge pull request #168 from elmsfu/hlc2asc/verilog_literal_ram_data | Clifford Wolf | |
| icebox_hlc2asc: Allow data of ram to use verilog literal format | |||
| 2018-07-10 | Merge pull request #167 from mithro/icebox_vlog_drivers | Clifford Wolf | |
| icebox_vlog: Better information about drivers for nets. | |||
| 2018-07-10 | Merge pull request #164 from mithro/global-fix | Clifford Wolf | |
| Fix spelling and io_X/GLOBAL_OUTPUT_NETWORK | |||
| 2018-07-08 | icebox_vlog: Fix constant LUT output. | Tim 'mithro' Ansell | |
| 2018-07-08 | icebox_vlog: Save error message to file and print it. | Tim 'mithro' Ansell | |
| Previously if you were doing; `icebox_vlog example.asc > example_bit.v` you would just get; ``` Traceback (most recent call last): File "icebox_vlog.py", line 947, in <module> assert False AssertionError ``` Now you get; ``` Traceback (most recent call last): File "icebox_vlog.py", line 948, in <module> assert False, "\n ".join(emsg) AssertionError: Single-driver-check failed for 2 nets: n10 has 0 drivers: [] n15 has 2 drivers: ['clk', 'clk2'] ``` | |||
| 2018-07-03 | icebox_hlc2asc: Allow data of ram to use verilog literal format | Elms | |
| 2018-07-03 | icebox_vlog: Better information about drivers for nets. | Tim 'mithro' Ansell | |
| 2018-06-22 | icebox_hlc2asc: Allow io_X/GLOBAL_OUTPUT_BUFFER | Tim 'mithro' Ansell | |
| 2018-06-22 | icebox_hlc2asc: Fix spelling in error message. | Tim 'mithro' Ansell | |
| 2018-06-20 | icebox_hlc2asc: update to support device by family | Elms | |
| 2018-06-20 | icebox_hlc2asc: Adding more descriptive errors messages | Elms | |
