| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-06-04 | Improve error message. | Tim 'mithro' Ansell | |
| Now; ----------------- Parse error in line 364: span4_y9_g7_10 <-> span4_x3_g13_5 conflicting bits ['!B12[8]', '!B12[9]', 'B12[10]'] setting:{(12, 10)} - current clear:{(12, 10), (12, 8)} clearing:{(12, 9), (12, 8)} - current set :{(12, 9)} ----------------- Previously; ----------------- File "icebox_hlc2asc.py", line 742, in apply_directive self.set_bits(bits) File "icebox_hlc2asc.py", line 762, in set_bits raise ParseError("conflicting bits") TypeError: __init__() takes 1 positional argument but 2 were given ----------------- | |||
| 2018-06-01 | Merge pull request #147 from mithro/hlc-fixes | Clifford Wolf | |
| Allow routing (bidir) entries to be looked up in either direction. | |||
| 2018-06-01 | Allow routing (bidir) entries to be looked up in either direction. | Tim 'mithro' Ansell | |
| 2018-05-31 | Merge pull request #146 from mithro/hlc-fixes | Clifford Wolf | |
| Support both `abc/123` and `123` forms of specifying tracks. | |||
| 2018-05-30 | Better error message when bit pattern is missing. | Tim 'mithro' Ansell | |
| Previously; ``` self.apply_directive('buffer', src, dst) File "/usr/local/google/home/tansell/work/catx/vtr/env/conda/bin/icebox_hlc2asc", line 698, in apply_directive bits, = [entry[0] for entry in self.db if entry[1:] == fields] ValueError: not enough values to unpack (expected 1, got 0) ``` Now: ``` Parse error in line 2108: span12_y4_g14_0 -> span4_y4_g11_7 <-> span4_x7_g4_0 No bit pattern for ['buffer', 'sp12_h_r_11', 'sp4_h_r_7'] in LogicTile(1k, 7, 4) ``` | |||
| 2018-05-30 | Allow prefixes in multiple chained statements. | Tim 'mithro' Ansell | |
| IE ``` lutff_1 { lutff_1/out -> local_g2_1 -> lutff_1/in_0 local_g2_2 -> lutff_1/in_3 local_g2_7 -> lutff_1/in_2 } ``` | |||
| 2018-05-30 | Support both `abc/123` and `123` forms of specifying tracks. | Tim 'mithro' Ansell | |
| Kind of fixes #145. | |||
| 2018-05-30 | icebox: Allow selecting package in icebox_vlog | David Shah | |
| Signed-off-by: David Shah <davey1576@gmail.com> | |||
| 2018-05-13 | Merge pull request #139 from awygle/lm_icebox | Clifford Wolf | |
| Icebox support for ice40 LM | |||
| 2018-05-13 | Extact reproducable chipdb-5k.txt | Clifford Wolf | |
| Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||
| 2018-05-13 | Add chipdb-lm4k.txt to .gitignore | Andrew Wygle | |
| 2018-05-13 | Correct internal global buffers for lm4k | Andrew Wygle | |
| 2018-05-13 | Added missing ieren entries for lm4k. | Andrew Wygle | |
| Config SPI pins weren't present in ioctrl_lm4k.sh | |||
| 2018-05-13 | Add lm4k chipdb to icebox Makefile. | Andrew Wygle | |
| 2018-05-13 | Support lm4k in icebox_chipdb.py. | Andrew Wygle | |
| 2018-05-12 | Completed first pass at icebox support for lm4k. | Andrew Wygle | |
| Needs testing. | |||
| 2018-05-12 | [WIP] Added colbuf and gbufin data for LM series | Andrew Wygle | |
| 2018-05-12 | [WIP] Add partial icebox support for lm4k. | Andrew Wygle | |
| 2018-04-02 | Add BG121 package variant and update docs | David Shah | |
| 2018-02-09 | Add UltraPlus I³C IO to chipdb | David Shah | |
| 2018-02-09 | Add RGB driver outputs to chipdb | David Shah | |
| 2018-01-16 | Add 5k UWG30 ieren data to db | David Shah | |
| 2018-01-16 | Remove seperate 5k RAM DB and share with 8k instead | David Shah | |
| This should ensure that the 5k RAM routing entries are now complete, fixing #115 | |||
| 2018-01-16 | Add pinout for 5k UWG30 package | David Shah | |
| 2018-01-16 | HFOSC trimming info | David Shah | |
| 2018-01-16 | New UltraPlus corner tracing algorithm | David Shah | |
| 2018-01-16 | Misc routing tweaks | David Shah | |
| 2018-01-16 | Figure out missing SPI config bits, and add to chipdb | David Shah | |
| 2017-11-26 | Chipdb fix for hard IP | David Shah | |
| 2017-11-24 | Add UltraPlus IP to chipdb | David Shah | |
| 2017-11-23 | Begin I2C/SPI IP reverse engineering | David Shah | |
| 2017-11-20 | Fix whitespace and a couple of typos | David Shah | |
| 2017-11-18 | Add all cf_bits and pullup strength notes | David Shah | |
| 2017-11-17 | Add missing 5k BRAM bits | David Shah | |
| 2017-11-17 | Make 5k db as a default target | David Shah | |
| 2017-11-17 | Remove non-existing routing resources (5k) | David Shah | |
| 2017-11-17 | Add support for UltraPlus SPRAM | David Shah | |
| 2017-11-17 | Add UltraPlus LED driver support and demo | David Shah | |
| 2017-11-17 | UltraPlus Internal Oscillator support | David Shah | |
| 2017-11-17 | UltraPlus DSPs working | David Shah | |
| 2017-11-17 | Add new tile types and MAC16s to chipdb | David Shah | |
| 2017-11-17 | Tidy up some of the icebox changes | David Shah | |
| 2017-11-17 | Fix 5k corner routing, and reverse engineer SPRAM | David Shah | |
| 2017-11-17 | Start UltraPlus DSP documentation | David Shah | |
| 2017-11-17 | Trace DSP routing | David Shah | |
| 2017-11-06 | Fix 5k gbin configuration | David Shah | |
| 2017-11-05 | Add more 5k RAM bits to db | David Shah | |
| 2017-11-05 | Fix 5k padin_glb_netwk bits | David Shah | |
| 2017-11-01 | Fix global network 1 padin bit | David Shah | |
| 2017-11-01 | Work on 5k global buffer pads | David Shah | |
 |
index : icestorm | |
| Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered) |
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