icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Age	Commit message (Collapse)	Author
2018-01-16	Remove seperate 5k RAM DB and share with 8k instead	David Shah
	This should ensure that the 5k RAM routing entries are now complete, fixing #115
2017-11-17	Create icefuzz scripts for DSP and 5k	David Shah

2017-11-08	Preparations for DSP and IpCon fuzzing	David Shah

2017-10-29	Share glb_netwk data between 5k and 8k parts	David Shah

2017-10-25	Add ColBufCtrl bits to database for 5k parts	David Shah

2017-07-31	Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from database	Clifford Wolf

2017-06-23	More work figuring out values in icebox.py	Scott Shawcroft

2017-06-22	Add icefuzz support for the UP5K and rework underlying device specification ↵	Scott Shawcroft
	for more flexibility.
2017-03-11	Disable propagation of LP384 ieren bits into iceboxdb.py	Clifford Wolf

2016-01-09	Fuzzed RamCascade bits	Clifford Wolf

2015-12-04	Added lutff_i/lout net to model	Clifford Wolf

2015-09-27	Added 1k timings	Clifford Wolf

2015-08-22	icefuzz: python 3	Clifford Wolf

2015-07-30	Replaced calls to "python" with "python2"	Clifford Wolf

2015-07-18	Imported full dev sources	Clifford Wolf