| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-06-10 | add RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | |
| 2019-02-22 | u4k: add SMCCLK cell location | Simon Schubert | |
| icecube uses SMCCLK.CLK to "legalize" output cells. Unclear what this is for, but it appears in almost all outputs. | |||
| 2019-02-22 | iCE40 Ultra = iCE5LP = u4k port | Simon Schubert | |
| 2018-01-29 | Updated 5k timing data, icetime regression fix | David Shah | |
| 2018-01-22 | More DSP timing fuzzing, start adding new tiles to icetime | David Shah | |
| 2018-01-22 | Seperate different DSP configs in timing data | David Shah | |
| 2018-01-20 | Fix 5k timing data | David Shah | |
| 2017-11-28 | Add uncommitted changes and tidy up some files | David Shah | |
| 2017-03-07 | tmedges.txt added, icebox-Makefile buildable | hermitsoft | |
| 2016-02-01 | Timing models for LP and HX devices | Clifford Wolf | |
 |
index : icestorm | |
| Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered) |
| aboutsummaryrefslogtreecommitdiff |