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2021-09-06Update variable name to PYTHON3Miodrag Milanovic
2021-09-06Merge pull request #239 from xobs/python-bin-nameMiodrag Milanović
Use $(PYTHON) in Makefiles instead of `python3`
2020-12-04added I2C and SPI for u4k to databaseNils Albartus
2019-10-22icefuzz: update Makefile to use $(PYTHON) variableSean Cross
Don't hardcode `python3` as the name of the Python interpreter. Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-10add RGB_DRV/LED_DRV_CUR for u4kSimon Schubert
2019-02-22u4k: add SMCCLK cell locationSimon Schubert
icecube uses SMCCLK.CLK to "legalize" output cells. Unclear what this is for, but it appears in almost all outputs.
2019-02-22iCE40 Ultra = iCE5LP = u4k portSimon Schubert
2018-05-13Added missing ieren entries for lm4k.Andrew Wygle
Config SPI pins weren't present in ioctrl_lm4k.sh
2018-05-12[WIP] Add partial icebox support for lm4k.Andrew Wygle
2018-05-12Add LM4K to icefuzz Makefile and fuzzconfig.py.Andrew Wygle
2018-05-06Add LM family support to icecube.shAndrew Wygle
2018-01-30Tidy upDavid Shah
2018-01-29Updated 5k timing data, icetime regression fixDavid Shah
2018-01-28DSP related fixesDavid Shah
2018-01-22More DSP timing fuzzing, start adding new tiles to icetimeDavid Shah
2018-01-22Seperate different DSP configs in timing dataDavid Shah
2018-01-20Fix 5k timing dataDavid Shah
2018-01-16I³C IO reverse engineered and documentedDavid Shah
2018-01-16Remove seperate 5k RAM DB and share with 8k insteadDavid Shah
This should ensure that the 5k RAM routing entries are now complete, fixing #115
2018-01-16Figure out missing SPI config bits, and add to chipdbDavid Shah
2017-11-28Whitespace fixesDavid Shah
2017-11-28Add uncommitted changes and tidy up some filesDavid Shah
2017-11-24Preparations for 5k icetimeDavid Shah
2017-11-24Documented I2C/SPI/LEDDA_IPDavid Shah
2017-11-24All 5k IP tracedDavid Shah
2017-11-24Work on UltraPlus IP tracingDavid Shah
2017-11-23Begin I2C/SPI IP reverse engineeringDavid Shah
2017-11-20Fix whitespace and a couple of typosDavid Shah
2017-11-17Add missing 5k BRAM bitsDavid Shah
2017-11-17Add support for UltraPlus SPRAMDavid Shah
2017-11-175k RGB driver reverse engineeredDavid Shah
2017-11-17Fix 5k corner routing, and reverse engineer SPRAMDavid Shah
2017-11-17Figure out DSP config bits for all locsDavid Shah
2017-11-17Trace DSP routingDavid Shah
2017-11-17Create icefuzz scripts for DSP and 5kDavid Shah
2017-11-08Preparations for DSP and IpCon fuzzingDavid Shah
2017-11-05Add more 5k RAM bits to dbDavid Shah
2017-11-02Add 5k colbuf fuzzing scriptsDavid Shah
2017-10-30PLL configuration fuzzing scriptDavid Shah
2017-10-29Share glb_netwk data between 5k and 8k partsDavid Shah
2017-10-25Add ColBufCtrl bits to database for 5k partsDavid Shah
2017-10-23Add some verilog tests for analysing up5k featuresDavid Shah
2017-10-23Fix IeRen database for up5kDavid Shah
2017-10-21Add DSP and IPConnect tile support to icepack and glbcheckDavid Shah
2017-10-20Fix make_ram40 for UltraPlusDavid Shah
Sometimes make_ram40 was assigning too many IO pins, causing a placment failure, and also sometimes connecting a global clock net to WCLKE or RCLKE which was also causing a placment failure.
2017-10-20Fix case where make_prim allocates all global buffer pinsDavid Shah
This is a low probability bug more likely to show up in low pin count devices with few GBINs. In rare cases make_prim would constrain all of the global buffer capable pins but not the clock input. icecube would then fail to place the clock input. This is fixed by always constraining the clock if all GBIN pins are used.
2017-10-20Quick fix of pin 23 issue (pending further discussion)David Shah
2017-08-01Squelch trailing whitespaceLarry Doolittle
2017-07-31Fix some bugs in two of the icefuzz make_*.py scriptsClifford Wolf
2017-07-31Fix icecube.sh to work with lin and lin64 dirs, remove hardcoded ICECUBEDIR=Clifford Wolf
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