icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Age	Commit message (Collapse)	Author
2018-01-22	Seperate different DSP configs in timing data	David Shah

2018-01-20	Fix 5k timing data	David Shah

2018-01-16	I³C IO reverse engineered and documented	David Shah

2018-01-16	Remove seperate 5k RAM DB and share with 8k instead	David Shah
	This should ensure that the 5k RAM routing entries are now complete, fixing #115
2018-01-16	Figure out missing SPI config bits, and add to chipdb	David Shah

2017-11-28	Whitespace fixes	David Shah

2017-11-28	Add uncommitted changes and tidy up some files	David Shah

2017-11-24	Preparations for 5k icetime	David Shah

2017-11-24	Documented I2C/SPI/LEDDA_IP	David Shah

2017-11-24	All 5k IP traced	David Shah

2017-11-24	Work on UltraPlus IP tracing	David Shah

2017-11-23	Begin I2C/SPI IP reverse engineering	David Shah

2017-11-20	Fix whitespace and a couple of typos	David Shah

2017-11-17	Add missing 5k BRAM bits	David Shah

2017-11-17	Add support for UltraPlus SPRAM	David Shah

2017-11-17	5k RGB driver reverse engineered	David Shah

2017-11-17	Fix 5k corner routing, and reverse engineer SPRAM	David Shah

2017-11-17	Figure out DSP config bits for all locs	David Shah

2017-11-17	Trace DSP routing	David Shah

2017-11-17	Create icefuzz scripts for DSP and 5k	David Shah

2017-11-08	Preparations for DSP and IpCon fuzzing	David Shah

2017-11-05	Add more 5k RAM bits to db	David Shah

2017-11-02	Add 5k colbuf fuzzing scripts	David Shah

2017-10-30	PLL configuration fuzzing script	David Shah

2017-10-29	Share glb_netwk data between 5k and 8k parts	David Shah

2017-10-25	Add ColBufCtrl bits to database for 5k parts	David Shah

2017-10-23	Add some verilog tests for analysing up5k features	David Shah

2017-10-23	Fix IeRen database for up5k	David Shah

2017-10-21	Add DSP and IPConnect tile support to icepack and glbcheck	David Shah

2017-10-20	Fix make_ram40 for UltraPlus	David Shah
	Sometimes make_ram40 was assigning too many IO pins, causing a placment failure, and also sometimes connecting a global clock net to WCLKE or RCLKE which was also causing a placment failure.
2017-10-20	Fix case where make_prim allocates all global buffer pins	David Shah
	This is a low probability bug more likely to show up in low pin count devices with few GBINs. In rare cases make_prim would constrain all of the global buffer capable pins but not the clock input. icecube would then fail to place the clock input. This is fixed by always constraining the clock if all GBIN pins are used.
2017-10-20	Quick fix of pin 23 issue (pending further discussion)	David Shah

2017-08-01	Squelch trailing whitespace	Larry Doolittle

2017-07-31	Fix some bugs in two of the icefuzz make_*.py scripts	Clifford Wolf

2017-07-31	Fix icecube.sh to work with lin and lin64 dirs, remove hardcoded ICECUBEDIR=	Clifford Wolf

2017-07-31	Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from database	Clifford Wolf

2017-07-02	Introduce device class into fuxx workign directories and have glbcheck ↵	Scott Shawcroft
	handle unsupported 5k tiles ok.
2017-06-23	More work figuring out values in icebox.py	Scott Shawcroft

2017-06-22	Add icefuzz support for the UP5K and rework underlying device specification ↵	Scott Shawcroft
	for more flexibility.
2017-06-20	icefuzz support for ice40UP5k FPGA	Scott Shawcroft

2017-03-11	Disable propagation of LP384 ieren bits into iceboxdb.py	Clifford Wolf

2017-03-10	icefuzz data and test scripts for LP384-CM49	hermitsoft

2017-03-09	make_mesh.py fix for even pin-distribution	hermitsoft

2017-03-09	Maximized icefuzz testcases for LP384-CM49	hermitsoft

2017-03-09	ieren and pin info for all LP384	hermitsoft

2017-03-09	Add icecube.sh support for lp384-cm36 and lp384-cm49, make cm49 default	Clifford Wolf

2017-03-08	Fix icecube.sh -384	Clifford Wolf

2017-03-08	Remove some trailing whitespaces	Clifford Wolf

2017-03-07	tmedges.txt added, icebox-Makefile buildable	hermitsoft

2017-03-07	LP384 timings exported too by Makefile	hermitsoft