icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Age	Commit message (Collapse)	Author
2022-05-30	Change help message	Miodrag Milanovic

2021-02-05	Add an option (-p) to force use of SB_PLL40_PAD	David Williams
	When a clock is applied to a dedicated clock pin, SB_PLL40_CORE is no longer the correct primitive to use. Also the name of the clock input must be PACKAGEPIN (rather than REFERENCECLK)
2020-04-22	Fix compiler warning in icepll	Claire Wolf
	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2019-12-31	Add iteration over list of frequencies for best solution	Mats Engstrom
	This patch adds support for icepll to try multiple input frequencies to find the best crystal for the desired output frequency. The values tested comes either from a specified file using-B, or from a default set of frequencies from Mousers "normally stocked" crystal oscillators.
2019-05-26	icepll: Add support for writing output data to stdout	Michael Buesch

2019-05-26	icepll: Avoid segmentation fault, if opening of output file fails	Michael Buesch

2019-05-25	icepll: In quiet mode don't print info about target file name	Michael Buesch

2018-03-31	Mount NODEFS if using emscripten and nodejs	Robert Ou
	Mounts root directory on `/hostfs` and the current working directory on `/hostcwd`
2018-03-10	Add -n <module_name> option	Tom Verbeure

2017-07-04	Fix coding style in icepll.cc	Clifford Wolf

2017-06-24	Update PLL DIVF range to be [0,127]	C-Elegans
	As discussed in issue #83, the range of the DIVF parameter in the iCE40 PLL Usage Guide is incorrectly listed as being 0-63, when it should actually be 0-127 when used in the SIMPLE feedback mode. This however does apply in other feedback modes, where the DIVF range should still be restricted to 0-63
2017-03-13	Remove trailing comma in icepll module output.	Josh Headapohl

2017-02-04	icepll: changes according to cliffordwolf/icestorm#67:	Matthias
	* corrected getopt argument * removed PLLOUT_SELECT("GENCLK") from output
2017-02-02	icepll: added -m option to choose between saving Verilog header or module	Matthias

2017-02-01	icepll: added -f option to export configuration as Verilog module	Matthias

2017-02-01	icepll: added -q option to suppress output to stdout	Matthias

2016-12-17	Fixed icepll divf range	Clifford Wolf

2016-05-15	Added FILTER_RANGE support to icepll	Clifford Wolf

2016-02-27	fix a few spelling errors	Ruben Undheim

2016-01-04	Added "icepll" PLL parameters calculator	Clifford Wolf