From d1e16d54ad7dd6bb7334494450917107615d0ef2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Oct 2015 14:06:54 +0200 Subject: Converted docs to proper HTML5 --- docs/format.html | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) (limited to 'docs/format.html') diff --git a/docs/format.html b/docs/format.html index 75397e0..8c21c00 100644 --- a/docs/format.html +++ b/docs/format.html @@ -1,4 +1,18 @@ + + + Project IceStorm – Bitstream File Format Documentation +

Project IceStorm – Bitstream File Format Documentation

@@ -31,8 +45,7 @@ follows the command in case of the CRAM and BRAM commands. The following commands are known:

-

- +
OpcodeDescription
0payload=0: CRAM Data
payload=3: BRAM Data
@@ -53,10 +66,9 @@ The following commands are known: payload=16: Enable cold boot
payload=32: Enable warm boot
-

-Use iceunpack -vv to display the commands as they are interpreted by the tool. +Use iceunpack -vv to display the commands as they are interpreted by the tool.

@@ -72,7 +84,7 @@ Most bytes in the bitstream are SRAM data bytes that should be written to the va in the FPGA. The following sequence is used to program an SRAM cell:

-

The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can @@ -104,7 +116,8 @@ The ordering of the data bits is in MSB first row-major order.

Organization of the CRAM

-

+

Mapping of tile config bits to 2D CRAM

The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant. @@ -129,14 +142,14 @@ RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM

The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit -positions are vertically permuted as well. The CramIndexConverter class in icepack.cc encapsulates the calculations +positions are vertically permuted as well. The CramIndexConverter class in icepack.cc encapsulates the calculations that are neccessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses.

The black pixels in the image correspond to CRAM bits that are not associated with any IO, LOGIC or RAM tile. -Some of them are unused, others are used by hard IPs or other global resources. The iceunpack tool reports -such bits, when set, with the ".extra_bit bank x y" statement in the ASCII output format. +Some of them are unused, others are used by hard IPs or other global resources. The iceunpack tool reports +such bits, when set, with the ".extra_bit bank x y" statement in the ASCII output format.

Organization of the BRAM

@@ -152,3 +165,4 @@ The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). Th the CRC to 0xFFFF. No zero padding is performed.

+ -- cgit v1.2.3