From 53d4a0be53776cb2cbc83d9bd245935594eb37f4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Jul 2015 22:39:38 +0200 Subject: Spelling fixes in documentation (by Larry Doolittle) --- docs/logic_tile.html | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'docs/logic_tile.html') diff --git a/docs/logic_tile.html b/docs/logic_tile.html index 8e3dcad..6404a80 100644 --- a/docs/logic_tile.html +++ b/docs/logic_tile.html @@ -70,7 +70,7 @@ For example, the wire sp4_h_r_0 in cell (x, y) has the following names:

-The image on the right shows the veritical span-4 wires of a logic or ram cell (click to enlarge). +The image on the right shows the vertical span-4 wires of a logic or ram cell (click to enlarge).

@@ -82,7 +82,7 @@ to sp4_v_b_12 to sp4_v_b_47.

But in addition to that, each cell also has access to sp4_v_b_0 to sp4_v_b_47 of its right neighbour. -This are the wires sp4_r_v_b_0 to sp4_r_v_b_47. So over all a single veritical span-4 wire +This are the wires sp4_r_v_b_0 to sp4_r_v_b_47. So over all a single vertical span-4 wire connects 9 cells. For example, the wire sp4_v_b_0 in cell (x, y) has the following names:

@@ -129,7 +129,7 @@ terminate in the cell. Wire names are normalized to sp12_v_r_2 to s

The local tracks are the gateway to the logic cell inputs. Signals from the span-wires -and the logic cell ouputs of the eight neighbour cells can be routed to the local tracks and +and the logic cell outputs of the eight neighbour cells can be routed to the local tracks and signals from the local tracks can be routed to the logic cell inputs.

@@ -223,7 +223,7 @@ Each logic tile has a logic block containing 8 logic cells. Each logic cell cont unit and a flip-flop. Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the bit that configures positive/negative edge for the flip flops. But the three configuration bits that specify if the flip flop should be used, if it is set or reset by the set/reset input, and if the set/reset is synchronous -or asynchrouns exist for each logic cell individually. +or asynchronous exist for each logic cell individually.

@@ -240,7 +240,7 @@ The carry unit calculates lutff_i/cout = lutff_i/in_1

Part of the functionality described above is documented as part of the routing -bitstream documentation (see the buffers for luttff_ inputs). The NegClk +bitstream documentation (see the buffers for lutff_ inputs). The NegClk bit switches all 8 FFs in the tile to negative edge mode. The CarryInSet bit drives the carry_in_mux high (it defaults to low when not driven via the buffer from carry_in). @@ -248,7 +248,7 @@ bit drives the carry_in_mux high (it defaults to low when not driven vi

The remaining functions of the logic cell are configured via the LC_i bits. This -are 20 bit per logic cell. We have arbitrarily labeld those bits as follows: +are 20 bit per logic cell. We have arbitrarily labeled those bits as follows:

-- cgit v1.2.3