From 88eebff7db9d76e418ccbddd884c4e617596a428 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 12 Nov 2017 19:13:55 +0000 Subject: Start UltraPlus DSP documentation --- docs/ultraplus.html | 157 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 docs/ultraplus.html (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html new file mode 100644 index 0000000..86fd857 --- /dev/null +++ b/docs/ultraplus.html @@ -0,0 +1,157 @@ + + + +Project IceStorm – UltraPlus Features Documentation + +

Project IceStorm – UltraPlus Features Documentation

+ +

+Project IceStorm aims at documenting the bitstream format of Lattice iCE40 +FPGAs and providing simple tools for analyzing and creating bitstream files. +This is work in progress. +

+ +

The ice40 UltraPlus devices have a number of new features compared to the older LP/HX series + devices, in particular: +

+ In order to implement these new features, a significant architecural change has been made: the + left and right sides of the device are no longer IO, but instead DSP and IPConnect tiles. +

+ +

DSP Tiles

+

Each MAC16 DSP comprises of 4 DSP tiles, all of which perform part of the DSP function and have +different routing bit configurations. Structually they are similar to logic tiles, but with the DSP +function wired into where the LUTs and DFFs would be. The four types of DSP tiles will be referred to +as DSP0 through DSP3, with DSP0 at the lowest y-position. One signal CO, is also routed through the +IPConnect tile above the DSP tile, referred to as IPCON4 in this context. + +A work-in-progress effort to determine where signals and configuration bits are located is below:

+

+Signal Assignments
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SB_MAC16 portDSP0DSP1DSP2DSP3IPCON4
CLK--lutff_global/clk--
CE--lutff_global/cen--
C[7:0]---lutff_[7:0]/in_3-
C[15:8]---lutff_[7:0]/in_1-
A[7:0]--lutff_[7:0]/in_3--
A[15:8]--lutff_[7:0]/in_1--
B[7:0]-lutff_[7:0]/in_3---
B[15:8]-lutff_[7:0]/in_1---
D[7:0]lutff_[7:0]/in_3----
D[15:8]lutff_[7:0]/in_1----
IRSTTOP-lutff_global/s_r---
IRSTBOTlutff_global/s_r----
ORSTTOP---lutff_global/s_r-
ORSTBOT--lutff_global/s_r--
AHOLD--lutff_0/in_0--
BHOLD-lutff_0/in_0---
CHOLD---lutff_0/in_0-
DHOLDlutff_0/in_0----
OHOLDTOP---lutff_1/in_0-
OHOLDBOTlutff_1/in_0----
ADDSUBTOP---lutff_3/in_0-
ADDSUBBOTlutff_3/in_0----
OLOADTOP---lutff_2/in_0-
OLOADBOTlutff_2/in_0----
CIlutff_4/in_0----
O[31:0]mult/O_[7:0]mult/O_[15:8]mult/O_[23:16]mult/O_[31:24]-
CO----slf_op_0
+ + +

+ +

+Configuration Bits
+

The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described asCBIT[24:0]. For most DSP tiles, + these follow a logical order where CBIT[7:0] maps to DSP0 CBIT[7:0]; CBIT[15:8] + to DSP1 CBIT[7:0], CBIT[23:16] to DSP2 CBIT[7:0] + and CBIT[24] to DSP3 CBIT0. +

+

However, there are some locations where configuration bits are swapped between DSP tiles and IPConnect tiles. For example, DSP1 (0, 16) CBIT[4:3] is used + for the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) CBIT[6:5].

+

The exact permutations are not yet known, but a script will be developed to find them.

+

+Other Implementation Notes
+

+ All active DSP tiles, and all IPConnect tiles whether used or not, have some bits set which reflect their logic tile heritage. The LC_x + bits which would be used to configure the logic cell, are set to the below pattern for each "logic cell" (interpreting them like a logic tile):
+
0000111100001111 0000

+ Coincidentally or not, this corresponds to a buffer passing through input 2 to the output. For each "cell" the cascade bit LC0x_inmux02_5 is + also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. It is not yet known if this serves any purpose, or is merely a remainder of Lattice's + internal testing. +

+

+

IPConnect Tiles

+

IPConnect tiles are used for connections to all of the other UltraPlus features, such as I2C/SPI, SPRAM, RGB and oscillators. Like DSP tiles, +they are structually similar to logic tiles. The outputs of IP functions are connected to nets named slf_op_0 through slf_op_7, +and the inputs use the LUT/FF inputs in the same way as DSP tiles.

+ + + +

Internal Oscillators

+ +Both of the internal oscillators are connected through IPConnect tiles, with their outputs optionally connected to the global networks, +by setting the "padin" extra bit (the used global networks 4 and 5 don't have physical pins on UltraPlus devices). + +

SB_HFOSC

+

The CLKHFPU input connects through IPConnect tile (0, 29) input lutff_0/in_1; +and the CLKHFEN input connects through input lutff_7/in_3 of the same tile.
+ +The CLKHF output of SB_HFOSC is connected to both IPConnect tile (0, 28) output slf_op_7 and to the padin + of glb_netwk_4.

+ +

Configuration bit CLKHF_DIV[1] maps to DSP1 tile (0, 16) config bit CBIT_4, and +CLKHF_DIV[0] maps to DSP1 tile (0, 16) config bit CBIT_3.

+ +

SB_LFOSC

+

The CLKLFPU input connects through IPConnect tile (25, 29) input lutff_0/in_1; +and the CLKLFEN input connects through input lutff_7/in_3 of the same tile.
+ +The CLKLF output of SB_LFOSC is connected to both IPConnect tile (25, 29) output slf_op_0 and to the padin + of glb_netwk_5.

+ +

SB_LFOSC has no configuration bits.

+ + -- cgit v1.2.3 From 64e3c1a9cd81e61d9a3b163c9e9f9390fa4c5c21 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 13 Nov 2017 16:15:16 +0000 Subject: Figure out DSP config bits for all locs --- docs/ultraplus.html | 45 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 86fd857..4220cad 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -109,9 +109,48 @@ A work-in-progress effort to determine where signals and configuration bits are to DSP1 CBIT[7:0], CBIT[23:16] to DSP2 CBIT[7:0] and CBIT[24] to DSP3 CBIT0.

-

However, there are some locations where configuration bits are swapped between DSP tiles and IPConnect tiles. For example, DSP1 (0, 16) CBIT[4:3] is used - for the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) CBIT[6:5].

-

The exact permutations are not yet known, but a script will be developed to find them.

+

However, there is one location where configuration bits are swapped between DSP tiles and IPConnect tiles. In DSP1 (0, 16) CBIT[4:1] are used + for IP such as the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) CBIT[6:3].

+

The full list of configuration bits, including the changes for the DSP at (0, 15) are described in the table below.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterNormal PositionDSP (0, 15)
Changes
C_REGDSP0.CBIT_0
A_REGDSP0.CBIT_1
B_REGDSP0.CBIT_2
D_REGDSP0.CBIT_3
TOP_8x8_MULT_REGDSP0.CBIT_4
BOT_8x8_MULT_REGDSP0.CBIT_5
PIPELINE_16x16_MULT_REG1DSP0.CBIT_6
PIPELINE_16x16_MULT_REG2DSP0.CBIT_7
TOPOUTPUT_SELECT[0]DSP1.CBIT_0
TOPOUTPUT_SELECT[1]DSP1.CBIT_1(0, 19).CBIT_3
TOPADDSUB_LOWERINPUT[1:0]DSP1.CBIT_[3:2](0, 19).CBIT_[5:4]
TOPADDSUB_UPPERINUTDSP1.CBIT_4(0, 19).CBIT_6
TOPADDSUB_CARRYSELECT[1:0]DSP1.CBIT_[6:5]
BOTOUTPUT_SELECT[0]DSP1.CBIT_7
BOTOUTPUT_SELECT[1]DSP2.CBIT_0
BOTADDSUB_LOWERINPUT[1:0]DSP2.CBIT_[2:1]
BOTADDSUB_UPPERINPUTDSP2.CBIT_3
BOTADDSUB_CARRYSELECTDSP2.CBIT_[5:4]
MODE_8x8DSP2.CBIT_6
A_SIGNEDDSP2.CBIT_7
B_SIGNEDDSP3.CBIT_0
+ +

Lattice document a limited number of supported configurations in the ICE Technology Library document, and Lattice's EDIF parser will + reject designs not following a supported configuration. It is not yet known whether unsupported configurations (such as mixed + signed and unsigned) function correctly or not. +

Other Implementation Notes

-- cgit v1.2.3 From 2f962ac92e018370793b9db3635fabd5b599afef Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 13 Nov 2017 16:51:28 +0000 Subject: Fix 5k corner routing, and reverse engineer SPRAM --- docs/ultraplus.html | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 4220cad..1074862 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -193,4 +193,28 @@ The CLKLF output of SB_LFOSC is conne

SB_LFOSC has no configuration bits.

+

SPRAM

+

The UltraPlus devices have 1Mbit of extra single-ported RAM, split into 4 256kbit blocks. The full list of connections for each SPRAM block in the 5k device is shown below, + as well as the location of the 1 configuration bit which is set to enable use of that SPRAM block.

+ + + + + + + + + + + + + + + + + + + +
SignalSPRAM (0, 0, 1)SPRAM (0, 0, 2)SPRAM (25, 0, 3)SPRAM (25, 0, 4)
ADDRESS[1:0](0, 2, lutff_[1:0]/in_1)(0, 2, lutff_[7:6]/in_0)(25, 2, lutff_[1:0]/in_1)(25, 2, lutff_[7:6]/in_0)
ADDRESS[7:2](0, 2, lutff_[7:2]/in_1)(0, 3, lutff_[5:0]/in_3)(25, 2, lutff_[7:2]/in_1)(25, 3, lutff_[5:0]/in_3)
ADDRESS[9:8](0, 2, lutff_[1:0]/in_0)(0, 3, lutff_[7:6]/in_3)(25, 2, lutff_[1:0]/in_0)(25, 3, lutff_[7:6]/in_3)
ADDRESS[13:10](0, 2, lutff_[5:2]/in_0)(0, 3, lutff_[3:0]/in_1)(25, 2, lutff_[5:2]/in_0)(25, 3, lutff_[3:0]/in_1)
DATAIN[7:0](0, 1, lutff_[7:0]/in_3)(0, 1, lutff_[7:0]/in_0)(25, 1, lutff_[7:0]/in_3)(25, 1, lutff_[7:0]/in_0)
DATAIN[15:8](0, 1, lutff_[7:0]/in_1)(0, 2, lutff_[7:0]/in_3)(25, 1, lutff_[7:0]/in_1)(25, 2, lutff_[7:0]/in_3)
MASKWREN[3:0](0, 3, lutff_[3:0]/in_0)(0, 3, lutff_[7:4]/in_0)(25, 3, lutff_[3:0]/in_0)(25, 3, lutff_[7:4]/in_0)
WREN(0, 3, lutff_4/in_1)(0, 3, lutff_5/in_1)(25, 3, lutff_4/in_1)(25, 3, lutff_5/in_1)
CHIPSELECT(0, 3, lutff_6/in_1)(0, 3, lutff_7/in_1)(25, 3, lutff_6/in_1)(25, 3, lutff_7/in_1)
CLOCK(0, 1, clk)(0, 2, clk)(25, 1, clk)(25, 2, clk)
STANDBY(0, 4, lutff_0/in_3)(0, 4, lutff_1/in_3)(25, 4, lutff_0/in_3)(25, 4, lutff_1/in_3)
SLEEP(0, 4, lutff_2/in_3)(0, 4, lutff_3/in_3)(25, 4, lutff_2/in_3)(25, 4, lutff_3/in_3)
POWEROFF(0, 4, lutff_4/in_3)(0, 4, lutff_5/in_3)(25, 4, lutff_4/in_3)(25, 4, lutff_5/in_3)
DATAOUT[7:0](0, 1, slf_op_[7:0])(0, 3, slf_op_[7:0])(25, 1, slf_op_[7:0])(25, 3, slf_op_[7:0])
DATAOUT[15:8](0, 2, slf_op_[7:0])(0, 4, slf_op_[7:0])(25, 2, slf_op_[7:0])(25, 4, slf_op_[7:0])
SPRAM_ENABLE(0, 1, CBIT_0)(0, 1, CBIT_1)(25, 1, CBIT_0)(25, 1, CBIT_1)
+ -- cgit v1.2.3 From 25ad7a24b96b021c6ab25e275059e20187b4f882 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 14 Nov 2017 14:06:38 +0000 Subject: 5k RGB driver reverse engineered --- docs/ultraplus.html | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 1074862..1b9e950 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -217,4 +217,32 @@ The CLKLF output of SB_LFOSC is conne SPRAM_ENABLE(0, 1, CBIT_0)(0, 1, CBIT_1)(25, 1, CBIT_0)(25, 1, CBIT_1) +

RGB LED Driver

+

The UltraPlus devices contain an internal 3-channel 2-24mA constant-current driver intended for RGB led driving (SB_RGBA_DRV). It is broken out onto 3 pins: 39, 40 and 41 on the QFN48 package. +The LED driver is implemented using the IPConnect tiles and is entirely seperate to the IO cells, if the LED driver is ignored or disabled on a pin then the pin +can be used as an open-drain IO using the standard IO cell.

+

Note that the UltraPlus devices also have a seperate PWM generator IP core, which would often be connected to this one to create LED effects such as "breathing" without + involving FPGA resources.

+

The LED driver connections are shown in the label below.

+ + + + + + + +
SignalNet
CURREN(25, 29, lutff_6/in_3)
RGBLEDEN(0, 30, lutff_1/in_1)
RGB0PWM(0, 30, lutff_2/in_1)
RGB1PWM(0, 30, lutff_3/in_1)
RGB2PWM(0, 30, lutff_4/in_1)
+

The configuration bits are as follows. As well as the documented bits, another bit "RGBA_DRV_EN" is set if any of the channels are enabled.

+ + + + + + + + + + + +
ParameterBit
RGBA_DRV_EN(0, 28, CBIT_5)
RGB0_CURRENT[1:0](0, 28, CBIT_[7:6])
RGB0_CURRENT[5:2](0, 29, CBIT_[3:0])
RGB1_CURRENT[3:0](0, 29, CBIT_[7:4])
RGB1_CURRENT[5:4](0, 30, CBIT_[1:0])
RGB2_CURRENT[5:0](0, 30, CBIT_[7:2])
CURRENT_MODE(0, 28, CBIT_4)
-- cgit v1.2.3 From 8fc49d07560f6bc434f9028086825388e5731a4f Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 18 Nov 2017 11:40:52 +0000 Subject: Corrections and changes to UltraPlus doc --- docs/ultraplus.html | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 1b9e950..e5706e6 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -35,9 +35,13 @@ This is work in progress.
  • 24mA constant current LED ouputs and PWM hard IP
    • In order to implement these new features, a significant architecural change has been made: the - left and right sides of the device are no longer IO, but instead DSP and IPConnect tiles. + left and right sides of the device are no longer IO, but instead DSP and IPConnect tiles. +

    +

    Currently icestorm and arachne-pnr support the DSPs (except for cascading), SPRAM , internal oscillators and constant current + LED drivers. Work to support the remaining features is underway.

    +

    DSP Tiles

    Each MAC16 DSP comprises of 4 DSP tiles, all of which perform part of the DSP function and have different routing bit configurations. Structually they are similar to logic tiles, but with the DSP @@ -45,7 +49,7 @@ function wired into where the LUTs and DFFs would be. The four types of DSP tile as DSP0 through DSP3, with DSP0 at the lowest y-position. One signal CO, is also routed through the IPConnect tile above the DSP tile, referred to as IPCON4 in this context. -A work-in-progress effort to determine where signals and configuration bits are located is below:

    +The location of signals and configuration bits is documented below.

    Signal Assignments
    @@ -101,10 +105,10 @@ A work-in-progress effort to determine where signals and configuration bits are

    - +

    Configuration Bits
    -

    The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described asCBIT[24:0]. For most DSP tiles, +

    The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described as CBIT[24:0]. For most DSP tiles, these follow a logical order where CBIT[7:0] maps to DSP0 CBIT[7:0]; CBIT[15:8] to DSP1 CBIT[7:0], CBIT[23:16] to DSP2 CBIT[7:0] and CBIT[24] to DSP3 CBIT0. @@ -138,7 +142,7 @@ A work-in-progress effort to determine where signals and configuration bits are

    - + @@ -158,8 +162,8 @@ A work-in-progress effort to determine where signals and configuration bits are bits which would be used to configure the logic cell, are set to the below pattern for each "logic cell" (interpreting them like a logic tile):

    0000111100001111 0000

    Coincidentally or not, this corresponds to a buffer passing through input 2 to the output. For each "cell" the cascade bit LC0x_inmux02_5 is - also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. It is not yet known if this serves any purpose, or is merely a remainder of Lattice's - internal testing. + also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. The DSPs at least will not function unless these bits are set correctly, so they + have some purpose and presumably indicate that the remains of a LUT are still present. There does not seem to be any case under which iCEcube generates a pattern other than this though.

    IPConnect Tiles

    @@ -171,7 +175,7 @@ and the inputs use the LUT/FF inputs in the same way as DSP tiles.

    Internal Oscillators

    -Both of the internal oscillators are connected through IPConnect tiles, with their outputs optionally connected to the global networks, +Both of the internal oscillators are connected through IPConnect tiles, with their outputs optionally connected to the global networks, by setting the "padin" extra bit (the used global networks 4 and 5 don't have physical pins on UltraPlus devices).

    SB_HFOSC

    @@ -181,7 +185,7 @@ and the CLKHFEN input connects throug The CLKHF output of SB_HFOSC is connected to both IPConnect tile (0, 28) output slf_op_7 and to the padin of glb_netwk_4.

    -

    Configuration bit CLKHF_DIV[1] maps to DSP1 tile (0, 16) config bit CBIT_4, and +

    Configuration bit CLKHF_DIV[1] maps to DSP1 tile (0, 16) config bit CBIT_4, and CLKHF_DIV[0] maps to DSP1 tile (0, 16) config bit CBIT_3.

    SB_LFOSC

    @@ -196,7 +200,7 @@ The CLKLF output of SB_LFOSC is conne

    SPRAM

    The UltraPlus devices have 1Mbit of extra single-ported RAM, split into 4 256kbit blocks. The full list of connections for each SPRAM block in the 5k device is shown below, as well as the location of the 1 configuration bit which is set to enable use of that SPRAM block.

    - +
    BOTADDSUB_LOWERINPUT[1:0]DSP2.CBIT_[2:1]
    BOTADDSUB_UPPERINPUTDSP2.CBIT_3
    BOTADDSUB_CARRYSELECTDSP2.CBIT_[5:4]
    BOTADDSUB_CARRYSELECT[1:0]DSP2.CBIT_[5:4]
    MODE_8x8DSP2.CBIT_6
    @@ -218,7 +222,7 @@ The CLKLF output of SB_LFOSC is conne
    SignalSPRAM (0, 0, 1)SPRAM (0, 0, 2)SPRAM (25, 0, 3)SPRAM (25, 0, 4)
    ADDRESS[1:0](0, 2, lutff_[1:0]/in_1)(0, 2, lutff_[7:6]/in_0)(25, 2, lutff_[1:0]/in_1)(25, 2, lutff_[7:6]/in_0)

    RGB LED Driver

    -

    The UltraPlus devices contain an internal 3-channel 2-24mA constant-current driver intended for RGB led driving (SB_RGBA_DRV). It is broken out onto 3 pins: 39, 40 and 41 on the QFN48 package. +

    The UltraPlus devices contain an internal 3-channel 2-24mA constant-current driver intended for RGB led driving (SB_RGBA_DRV). It is broken out onto 3 pins: 39, 40 and 41 on the QFN48 package. The LED driver is implemented using the IPConnect tiles and is entirely seperate to the IO cells, if the LED driver is ignored or disabled on a pin then the pin can be used as an open-drain IO using the standard IO cell.

    Note that the UltraPlus devices also have a seperate PWM generator IP core, which would often be connected to this one to create LED effects such as "breathing" without @@ -232,7 +236,7 @@ can be used as an open-drain IO using the standard IO cell.

    RGB1PWM(0, 30, lutff_3/in_1) RGB2PWM(0, 30, lutff_4/in_1) -

    The configuration bits are as follows. As well as the documented bits, another bit "RGBA_DRV_EN" is set if any of the channels are enabled.

    +

    The configuration bits are as follows. As well as the documented bits, another bit RGBA_DRV_EN is set if any of the channels are enabled.

    -- cgit v1.2.3 From b059f37b5006bd12ae10f3e847fb394b2540aa6a Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 18 Nov 2017 15:38:14 +0000 Subject: Add all cf_bits and pullup strength notes --- docs/ultraplus.html | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index e5706e6..da109b5 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -248,5 +248,20 @@ can be used as an open-drain IO using the standard IO cell.

     +
    ParameterBit
    RGB2_CURRENT[5:0](0, 30, CBIT_[7:2])
    CURRENT_MODE(0, 28, CBIT_4)
    + +

    IO Changes

    +

    The IO tiles contain a few new bits compared to earlier ice40 devices. + The bits padeb_test_0 and + padeb_test_1 are set for all pins, + even unused ones, unless set as an output.

    +

    There are also some new bits used to control the pullup strength:

    + + + + + + +
    StrengthCell 0Cell 1
    3.3kΩcf_bit_32
    B7[10]    		cf_bit_36
    B13[10]
    6.8kΩcf_bit_33
    B6[10]    		cf_bit_37
    B12[10]
    10kΩcf_bit_34
    B7[15]    		cf_bit_38
    B13[15]
    100kΩ
    (default)    		!cf_bit_35
    !B6[15]    		!cf_bit_39
    !B12[15]
    -- cgit v1.2.3