From 77eafa89b4b9d8852071cc68298f92465311470b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 6 Dec 2017 17:48:15 +0000 Subject: HFOSC trimming info --- docs/ultraplus.html | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 694b82d..dac648a 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -205,6 +205,14 @@ The CLKHF output of SB_HFOSC is conne

Configuration bit CLKHF_DIV[1] maps to DSP1 tile (0, 16) config bit CBIT_4, and CLKHF_DIV[0] maps to DSP1 tile (0, 16) config bit CBIT_3.

+

There is also an undocumented trimming function of the HFOSC, using the ports TRIM0 through TRIM9. This can only be accessed directly in iCECUBE if you modify the standard cell library. However + if you set the attribute VPP_2V5_TO_1P8V (which itself is not that well documented either) to 1 on the top level module, then the configuration bit + CBIT_5 of (0, 16) is set; and TRIM8 and TRIM4 are connected to + the same net as CLKHFPU.

+

TRIM[3:0] connect to (25, 28, lutff_[7:4]/in_0) and TRIM[9:4] + connect to (25, 29, lutff_[5:0]/in_3). CBIT_5 of (0, 16) must be set to enable trimming. The trim range +on the device used for testing was from 30.1 to 75.9 MHz. TRIM9 seemed to have no effect, the other inputs could broadly be considered to form a binary word, however it appeared neither linear +nor even monotonic.

SB_LFOSC

The CLKLFPU input connects through IPConnect tile (25, 29) input lutff_0/in_1; and the CLKLFEN input connects through input lutff_7/in_3 of the same tile.
-- cgit v1.2.3 From 35bd638b4cad985a235d19374f7a37f64c6b47c8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jan 2018 17:38:05 +0000 Subject: Add SPI enable bits to docs --- docs/ultraplus.html | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index dac648a..b5dda62 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -391,6 +391,10 @@ where multiple bits are used to enable an IP they are labeled as -- cgit v1.2.3 From 4b16c3735c0c183837994a4b4b07296f0bbba57c Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 13 Jan 2018 18:51:27 +0000 Subject: =?UTF-8?q?I=C2=B3C=20IO=20reverse=20engineered=20and=20documented?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- docs/ultraplus.html | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'docs/ultraplus.html') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index b5dda62..11e249d 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -290,6 +290,19 @@ can be used as an open-drain IO using the standard IO cell.

+

I3C capable IO

+

The UltraPlus devices have two IO pins designed for the new MIPI I3C standard (pins 23 and 25 in the SG48 package), +compared to normal IO pins they have two switchable pullups each. One of these pullups, the weak pullup, is fixed at 100k and the +other can be set to 3.3k, 6.8k or 10k using the mechanism above. The pullup control signals do not +connect directly to the IO tile, but instead connect through an IPConnect tile.

+ +

The connections are listed below:

+ + + + +
SignalPin 23
(19, 31, 0)		Pin 25
(19, 31, 1)
PU_ENB(25, 27, lutff_6/in_0)(25, 27, lutff_7/in_0)
WEAK_PU_ENB(25, 27, lutff_4/in_0)(25, 27, lutff_5/in_0)
+

Hard IP

The UltraPlus devices contain three types of Hard IP: I2C (SB_I2C), SPI (SB_SPI), and LED PWM generation -- cgit v1.2.3