From 70e01c1802bef592452cada1cba0224185e8029e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Jul 2017 18:37:47 +0200
Subject: Add pre- and post-synthesis testbench examples

---
 examples/icestick/Makefile | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'examples/icestick/Makefile')

diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile
index 9294608..d687d14 100644
--- a/examples/icestick/Makefile
+++ b/examples/icestick/Makefile
@@ -18,6 +18,21 @@ all: $(PROJ).rpt $(PROJ).bin
 %.rpt: %.asc
 	icetime -d $(DEVICE) -mtr $@ $<
 
+%_tb: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb
+	./$< +vcd=$@
+
+%_syn.v: %.blif
+	yosys -o $@ $^
+
+%_syntb: %_tb.v %_syn.v
+	iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
+
+%_syntb.vcd: %_syntb
+	./$< +vcd=$@
+
 prog: $(PROJ).bin
 	iceprog $<
 
-- 
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