From 70e01c1802bef592452cada1cba0224185e8029e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Jul 2017 18:37:47 +0200
Subject: Add pre- and post-synthesis testbench examples

---
 examples/icestick/.gitignore     |  5 +++
 examples/icestick/Makefile       | 15 ++++++++
 examples/icestick/rs232demo.v    |  8 +++++
 examples/icestick/rs232demo_tb.v | 75 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 103 insertions(+)
 create mode 100644 examples/icestick/rs232demo_tb.v

(limited to 'examples')

diff --git a/examples/icestick/.gitignore b/examples/icestick/.gitignore
index 539898f..bb30525 100644
--- a/examples/icestick/.gitignore
+++ b/examples/icestick/.gitignore
@@ -6,3 +6,8 @@ rs232demo.bin
 rs232demo.blif
 rs232demo.asc
 rs232demo.rpt
+rs232demo_tb
+rs232demo_tb.vcd
+rs232demo_syn.v
+rs232demo_syntb
+rs232demo_syntb.vcd
diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile
index 9294608..d687d14 100644
--- a/examples/icestick/Makefile
+++ b/examples/icestick/Makefile
@@ -18,6 +18,21 @@ all: $(PROJ).rpt $(PROJ).bin
 %.rpt: %.asc
 	icetime -d $(DEVICE) -mtr $@ $<
 
+%_tb: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb
+	./$< +vcd=$@
+
+%_syn.v: %.blif
+	yosys -o $@ $^
+
+%_syntb: %_tb.v %_syn.v
+	iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
+
+%_syntb.vcd: %_syntb
+	./$< +vcd=$@
+
 prog: $(PROJ).bin
 	iceprog $<
 
diff --git a/examples/icestick/rs232demo.v b/examples/icestick/rs232demo.v
index f9e7546..40347e8 100644
--- a/examples/icestick/rs232demo.v
+++ b/examples/icestick/rs232demo.v
@@ -19,6 +19,14 @@ module top (
 	reg [3:0] bit_cnt = 0;
 	reg recv = 0;
 
+	initial begin
+		LED1 = 0;
+		LED2 = 0;
+		LED3 = 0;
+		LED4 = 0;
+		LED5 = 0;
+	end
+
 	always @(posedge clk) begin
 		buffer_valid <= 0;
 		if (!recv) begin
diff --git a/examples/icestick/rs232demo_tb.v b/examples/icestick/rs232demo_tb.v
new file mode 100644
index 0000000..3e95abf
--- /dev/null
+++ b/examples/icestick/rs232demo_tb.v
@@ -0,0 +1,75 @@
+module testbench;
+	localparam integer PERIOD = 12000000 / 9600;
+
+	reg clk = 1;
+	always #5 clk = ~clk;
+
+	reg RX = 1;
+	wire TX;
+	wire LED1;
+	wire LED2;
+	wire LED3;
+	wire LED4;
+	wire LED5;
+
+	top uut (
+		.clk (clk ),
+		.RX  (RX  ),
+		.TX  (TX  ),
+		.LED1(LED1),
+		.LED2(LED2),
+		.LED3(LED3),
+		.LED4(LED4),
+		.LED5(LED5)
+	);
+
+	task send_byte;
+		input [7:0] c;
+		integer i;
+		begin
+			RX <= 0;
+			repeat (PERIOD) @(posedge clk);
+
+			for (i = 0; i < 8; i = i+1) begin
+				RX <= c[i];
+				repeat (PERIOD) @(posedge clk);
+			end
+
+			RX <= 1;
+			repeat (PERIOD) @(posedge clk);
+		end
+	endtask
+
+	reg [4095:0] vcdfile;
+
+	initial begin
+		if ($value$plusargs("vcd=%s", vcdfile)) begin
+			$dumpfile(vcdfile);
+			$dumpvars(0, testbench);
+		end
+
+		// send break
+		repeat (20 * PERIOD) @(posedge clk);
+		RX <= 0;
+		repeat (20 * PERIOD) @(posedge clk);
+		RX <= 1;
+		repeat (20 * PERIOD) @(posedge clk);
+
+		// turn all LEDs on
+		send_byte("1");
+		send_byte("2");
+		send_byte("3");
+		send_byte("4");
+		send_byte("5");
+
+		// turn all LEDs off
+		send_byte("1");
+		send_byte("2");
+		send_byte("3");
+		send_byte("4");
+		send_byte("5");
+
+		repeat (10 * PERIOD) @(posedge clk);
+		$finish;
+	end
+endmodule
-- 
cgit v1.2.3


From cb0a0f7ef81555cb5c8e51cabb806a302c92b91a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 19 Jul 2017 15:23:15 +0200
Subject: Improve rs232demo test bench

---
 examples/icestick/rs232demo_tb.v | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

(limited to 'examples')

diff --git a/examples/icestick/rs232demo_tb.v b/examples/icestick/rs232demo_tb.v
index 3e95abf..5b9aee1 100644
--- a/examples/icestick/rs232demo_tb.v
+++ b/examples/icestick/rs232demo_tb.v
@@ -1,8 +1,11 @@
 module testbench;
 	localparam integer PERIOD = 12000000 / 9600;
 
-	reg clk = 1;
-	always #5 clk = ~clk;
+	// reg clk = 0;
+	// initial #10 forever #5 clk = ~clk;
+
+	reg clk;
+	always #5 clk = (clk === 1'b0);
 
 	reg RX = 1;
 	wire TX;
@@ -48,12 +51,7 @@ module testbench;
 			$dumpvars(0, testbench);
 		end
 
-		// send break
-		repeat (20 * PERIOD) @(posedge clk);
-		RX <= 0;
-		repeat (20 * PERIOD) @(posedge clk);
-		RX <= 1;
-		repeat (20 * PERIOD) @(posedge clk);
+		repeat (10 * PERIOD) @(posedge clk);
 
 		// turn all LEDs on
 		send_byte("1");
@@ -70,6 +68,7 @@ module testbench;
 		send_byte("5");
 
 		repeat (10 * PERIOD) @(posedge clk);
+
 		$finish;
 	end
 endmodule
-- 
cgit v1.2.3


From 6124133269c7ff7bc550064e116c1bcfcbb412bf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Jul 2017 16:56:15 +0200
Subject: Add icestick "checker" example

---
 examples/icestick/.gitignore   |  9 +++++++
 examples/icestick/Makefile     |  7 +++---
 examples/icestick/checker.v    | 55 ++++++++++++++++++++++++++++++++++++++++++
 examples/icestick/checker_tb.v | 40 ++++++++++++++++++++++++++++++
 4 files changed, 108 insertions(+), 3 deletions(-)
 create mode 100644 examples/icestick/checker.v
 create mode 100644 examples/icestick/checker_tb.v

(limited to 'examples')

diff --git a/examples/icestick/.gitignore b/examples/icestick/.gitignore
index bb30525..c854ccc 100644
--- a/examples/icestick/.gitignore
+++ b/examples/icestick/.gitignore
@@ -11,3 +11,12 @@ rs232demo_tb.vcd
 rs232demo_syn.v
 rs232demo_syntb
 rs232demo_syntb.vcd
+checker.bin
+checker.blif
+checker.asc
+checker.rpt
+checker_tb
+checker_tb.vcd
+checker_syn.v
+checker_syntb
+checker_syntb.vcd
diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile
index d687d14..8b8e741 100644
--- a/examples/icestick/Makefile
+++ b/examples/icestick/Makefile
@@ -1,5 +1,6 @@
 PROJ = example
 # PROJ = rs232demo
+# PROJ = checker
 
 PIN_DEF = icestick.pcf
 DEVICE = hx1k
@@ -22,16 +23,16 @@ all: $(PROJ).rpt $(PROJ).bin
 	iverilog -o $@ $^
 
 %_tb.vcd: %_tb
-	./$< +vcd=$@
+	vvp -N $< +vcd=$@
 
 %_syn.v: %.blif
-	yosys -o $@ $^
+	yosys -p 'read_blif -wideports $^; write_verilog $@'
 
 %_syntb: %_tb.v %_syn.v
 	iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
 
 %_syntb.vcd: %_syntb
-	./$< +vcd=$@
+	vvp -N $< +vcd=$@
 
 prog: $(PROJ).bin
 	iceprog $<
diff --git a/examples/icestick/checker.v b/examples/icestick/checker.v
new file mode 100644
index 0000000..63c70fe
--- /dev/null
+++ b/examples/icestick/checker.v
@@ -0,0 +1,55 @@
+// A simple circuit that can be used to detect brownouts and other hardware issues
+
+module top (
+	input clk,
+	output LED1,
+	output LED2,
+	output LED3,
+	output LED4,
+	output LED5
+);
+	reg [7:0] reset_counter = 0;
+	reg resetn = 0;
+
+	always @(posedge clk) begin
+		reset_counter <= reset_counter + 1;
+		resetn <= resetn | &reset_counter;
+	end
+
+	reg error, rdmode, rdfin;
+
+	reg [31:0] scratchpad [0:1023];
+	reg [31:0] xorshift32_state;
+	reg [9:0] index;
+
+	reg [31:0] next_xorshift32_state;
+
+	always @* begin
+		next_xorshift32_state =      xorshift32_state ^ (     xorshift32_state << 13);
+		next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state >> 17);
+		next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state <<  5);
+	end
+
+	always @(posedge clk) begin
+		xorshift32_state <= &index ? 123456789 : next_xorshift32_state;
+		index <= index + 1;
+
+		if (!resetn) begin
+			xorshift32_state <= 123456789;
+			index <= 0;
+			error <= 0;
+			rdmode <= 0;
+			rdfin <= 0;
+		end else
+		if (!rdmode) begin
+			scratchpad[index] <= xorshift32_state;
+			rdmode <= &index;
+		end else begin
+			if (scratchpad[index] != xorshift32_state) error <= 1;
+			rdfin <= rdfin || &index;
+		end
+	end
+
+	wire ok = resetn && rdfin && !error;
+	assign LED1 = error, LED2 = error, LED3 = error, LED4 = error, LED5 = ok;
+endmodule
diff --git a/examples/icestick/checker_tb.v b/examples/icestick/checker_tb.v
new file mode 100644
index 0000000..241c89e
--- /dev/null
+++ b/examples/icestick/checker_tb.v
@@ -0,0 +1,40 @@
+module testbench;
+	reg clk;
+	always #5 clk = (clk === 1'b0);
+
+	wire ok;
+
+	top uut (
+		.clk(clk),
+		.LED5(ok)
+	);
+
+	reg [4095:0] vcdfile;
+
+	initial begin
+		if ($value$plusargs("vcd=%s", vcdfile)) begin
+			$dumpfile(vcdfile);
+			$dumpvars(0, testbench);
+		end
+	end
+
+	initial begin
+		@(posedge ok);
+		@(negedge ok);
+		$display("ERROR: detected falling edge on OK pin!");
+		$stop;
+	end
+
+	initial begin
+		repeat (3000) @(posedge clk);
+
+		if (!ok) begin
+			$display("ERROR: OK pin not asserted after 3000 cycles!");
+			$stop;
+		end
+
+		repeat (10000) @(posedge clk);
+		$display("SUCCESS: OK pin still asserted after 10000 cycles.");
+		$finish;
+	end
+endmodule
-- 
cgit v1.2.3


From 4ac8fff26c3f29372d98c2230ab8cab76650f3d5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Jul 2017 17:43:05 +0200
Subject: Use better error pattern in icestick checker example

---
 examples/icestick/checker.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'examples')

diff --git a/examples/icestick/checker.v b/examples/icestick/checker.v
index 63c70fe..a441845 100644
--- a/examples/icestick/checker.v
+++ b/examples/icestick/checker.v
@@ -51,5 +51,5 @@ module top (
 	end
 
 	wire ok = resetn && rdfin && !error;
-	assign LED1 = error, LED2 = error, LED3 = error, LED4 = error, LED5 = ok;
+	assign LED1 = 0, LED2 = error, LED3 = 0, LED4 = error, LED5 = ok;
 endmodule
-- 
cgit v1.2.3