From 2a7139115c08af847a5e9d19be3229dd627f4be9 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Thu, 22 Jun 2017 10:28:22 -0700 Subject: work in progress chipdb --- icebox/Makefile | 9 ++-- icebox/icebox.py | 123 +++++++++++++++++++++++++++++++++++++++++------- icebox/icebox_chipdb.py | 23 +++++---- 3 files changed, 128 insertions(+), 27 deletions(-) (limited to 'icebox') diff --git a/icebox/Makefile b/icebox/Makefile index 446fb18..fed3d6d 100644 --- a/icebox/Makefile +++ b/icebox/Makefile @@ -1,6 +1,6 @@ include ../config.mk -all: chipdb-384.txt chipdb-1k.txt chipdb-8k.txt +all: chipdb-384.txt chipdb-1k.txt chipdb-5k.txt chipdb-8k.txt chipdb-384.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py -3 > chipdb-384.new @@ -10,12 +10,16 @@ chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py > chipdb-1k.new mv chipdb-1k.new chipdb-1k.txt +chipdb-5k.txt: icebox.py iceboxdb.py icebox_chipdb.py + python3 icebox_chipdb.py -5 > chipdb-5k.new + mv chipdb-5k.new chipdb-5k.txt + chipdb-8k.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py -8 > chipdb-8k.new mv chipdb-8k.new chipdb-8k.txt clean: - rm -f chipdb-1k.txt chipdb-8k.txt chipdb-384.txt + rm -f chipdb-1k.txt chipdb-8k.txt chipdb-384.txt chipdb-5k.txt rm -f icebox.pyc iceboxdb.pyc install: all @@ -52,4 +56,3 @@ uninstall: -rmdir $(DESTDIR)$(PREFIX)/share/icebox .PHONY: all clean install uninstall - diff --git a/icebox/icebox.py b/icebox/icebox.py index 289f070..79608be 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -76,6 +76,26 @@ class iceconfig: self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)] self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)] + def setup_empty_5k(self): + self.clear() + self.device = "5k" + self.max_x = 26 + self.max_y = 33 + + for x in range(1, self.max_x): + for y in range(1, self.max_y): + if x in (6, 18): + if y % 2 == 1: + self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)] + else: + self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)] + else: + self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)] + + for x in range(1, self.max_x): + self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)] + self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)] + def setup_empty_8k(self): self.clear() self.device = "8k" @@ -116,6 +136,7 @@ class iceconfig: def pinloc_db(self): if self.device == "384": return pinloc_db["384-qn32"] if self.device == "1k": return pinloc_db["1k-tq144"] + if self.device == "5k": return pinloc_db["5k-sg48"] if self.device == "8k": return pinloc_db["8k-ct256"] assert False @@ -137,6 +158,8 @@ class iceconfig: def pll_list(self): if self.device == "1k": return ["1k"] + if self.device == "5k": + return ["5k"] if self.device == "8k": return ["8k_0", "8k_1"] if self.device == "384": @@ -474,6 +497,8 @@ class iceconfig: seed_segments.add((idx[0], idx[1], "lutff_7/cout")) if self.device == "1k": add_seed_segments(idx, tile, logictile_db) + elif self.device == "5k": + add_seed_segments(idx, tile, logictile_5k_db) elif self.device == "8k": add_seed_segments(idx, tile, logictile_8k_db) elif self.device == "384": @@ -484,6 +509,8 @@ class iceconfig: for idx, tile in self.ramb_tiles.items(): if self.device == "1k": add_seed_segments(idx, tile, rambtile_db) + elif self.device == "5k": + add_seed_segments(idx, tile, rambtile_5k_db) elif self.device == "8k": add_seed_segments(idx, tile, rambtile_8k_db) else: @@ -492,6 +519,8 @@ class iceconfig: for idx, tile in self.ramt_tiles.items(): if self.device == "1k": add_seed_segments(idx, tile, ramttile_db) + elif self.device == "5k": + add_seed_segments(idx, tile, ramttile_5k_db) elif self.device == "8k": add_seed_segments(idx, tile, ramttile_8k_db) else: @@ -611,7 +640,7 @@ class iceconfig: self.extra_bits.add((int(line[1]), int(line[2]), int(line[3]))) continue if line[0] == ".device": - assert line[1] in ["1k", "8k", "384"] + assert line[1] in ["1k", "5k", "8k", "384"] self.device = line[1] continue if line[0] == ".sym": @@ -1021,24 +1050,27 @@ def run_checks_neigh(): def run_checks(): run_checks_neigh() -def parse_db(text, grep_8k=False, grep_384=False): +def parse_db(text, device="1k"): db = list() for line in text.split("\n"): line_384 = line.replace("384_glb_netwk_", "glb_netwk_") line_1k = line.replace("1k_glb_netwk_", "glb_netwk_") + line_5k = line.replace("5k_glb_netwk_", "glb_netwk_") line_8k = line.replace("8k_glb_netwk_", "glb_netwk_") if line_1k != line: - if grep_8k: - continue - if grep_384: + if device != "1k": continue line = line_1k elif line_8k != line: - if not grep_8k: + if device != "8k": continue line = line_8k + elif line_5k != line: + if device != "5k": + continue + line = line_5k elif line_384 != line: - if not grep_384: + if device != "384": continue line = line_384 line = line.split("\t") @@ -1164,6 +1196,7 @@ noplls_db = { "1k-cb121": [ "1k" ], "1k-vq100": [ "1k" ], "384-qn32": [ "384" ], + "5k-sg48": [ "5k" ], } pllinfo_db = { @@ -1448,6 +1481,8 @@ pllinfo_db = { }, } +# TODO(tannewt): Correct these values for 5k once we figure out how to get the +# info. padin_pio_db = { "1k": [ (13, 8, 1), # glb_netwk_0 @@ -1459,6 +1494,16 @@ padin_pio_db = { ( 6, 0, 1), # glb_netwk_6 ( 6, 17, 1), # glb_netwk_7 ], + "5k": [ + (33, 16, 1), + ( 0, 16, 1), + (17, 33, 0), + (17, 0, 0), + ( 0, 17, 0), + (33, 17, 0), + (16, 0, 1), + (16, 33, 1), + ], "8k": [ (33, 16, 1), ( 0, 16, 1), @@ -1847,6 +1892,9 @@ ieren_db = { ], } +# This dictionary maps package variants to a table of pin names and their +# corresponding grid location (x, y, block). This is most easily found through +# the package view in iCEcube2 by hovering the mouse over each pin. pinloc_db = { "1k-swg16tr": [ ( "A2", 6, 17, 1), @@ -3850,17 +3898,61 @@ pinloc_db = { ( "G3", 3, 0, 0), ( "G4", 4, 0, 1), ( "G6", 5, 0, 1), - ] + ], + "5k-sg48": [ + ( "2", 8, 0, 0), + ( "3", 9, 0, 1), + ( "4", 9, 0, 0), + ( "6", 13, 0, 1), + ( "9", 15, 0, 0), + ( "10", 16, 0, 0), + ( "11", 17, 0, 0), + ( "12", 18, 0, 0), + ( "13", 19, 0, 0), + ( "14", 23, 0, 0), + ( "15", 24, 0, 0), + ( "16", 24, 0, 1), + ( "17", 23, 0, 1), + ( "18", 22, 0, 1), + ( "19", 21, 0, 1), + ( "20", 19, 0, 1), + ( "21", 18, 0, 1), + ( "23", 19, 31, 0), + ( "25", 19, 31, 1), + ( "26", 18, 31, 0), + ( "27", 18, 31, 1), + ( "28", 17, 31, 0), + ( "31", 16, 31, 1), + ( "32", 16, 31, 0), + ( "34", 13, 31, 1), + ( "35", 12, 31, 1), + ( "36", 9, 31, 1), + ( "37", 13, 31, 0), + ( "38", 8, 31, 1), + ( "39", 4, 31, 0), + ( "40", 5, 31, 0), + ( "41", 6, 31, 0), + ( "42", 8, 31, 0), + ( "43", 9, 31, 0), + ( "44", 6, 0, 1), + ( "45", 7, 0, 1), + ( "46", 5, 0, 0), + ( "47", 6, 0, 0), + ( "48", 7, 0, 0), + ], } iotile_full_db = parse_db(iceboxdb.database_io_txt) -logictile_db = parse_db(iceboxdb.database_logic_txt) -logictile_8k_db = parse_db(iceboxdb.database_logic_txt, True) -logictile_384_db = parse_db(iceboxdb.database_logic_txt, False, True) -rambtile_db = parse_db(iceboxdb.database_ramb_txt) -ramttile_db = parse_db(iceboxdb.database_ramt_txt) -rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, True) -ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, True) +logictile_db = parse_db(iceboxdb.database_logic_txt, "1k") +logictile_5k_db = parse_db(iceboxdb.database_logic_txt, "5k") +logictile_8k_db = parse_db(iceboxdb.database_logic_txt, "8k") +logictile_384_db = parse_db(iceboxdb.database_logic_txt, "384") +rambtile_db = parse_db(iceboxdb.database_ramb_txt, "1k") +ramttile_db = parse_db(iceboxdb.database_ramt_txt, "1k") +rambtile_5k_db = parse_db(iceboxdb.database_ramb_8k_txt, "5k") +ramttile_5k_db = parse_db(iceboxdb.database_ramt_8k_txt, "5k") +rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, "8k") +ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, "8k") iotile_l_db = list() iotile_r_db = list() @@ -3914,4 +4006,3 @@ for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, log if __name__ == "__main__": run_checks() - diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py index 7988e6a..ca7f483 100755 --- a/icebox/icebox_chipdb.py +++ b/icebox/icebox_chipdb.py @@ -19,6 +19,7 @@ import icebox import getopt, sys, re mode_384 = False +mode_5k = False mode_8k = False def usage(): @@ -28,19 +29,24 @@ Usage: icebox_chipdb [options] [bitmap.asc] -3 create chipdb for 384 device + -5 + create chipdb for 5k device + -8 create chipdb for 8k device """) sys.exit(0) try: - opts, args = getopt.getopt(sys.argv[1:], "38") + opts, args = getopt.getopt(sys.argv[1:], "358") except: usage() for o, a in opts: if o == "-8": mode_8k = True + elif o == "-5": + mode_5k = True elif o == "-3": mode_384 = True else: @@ -49,6 +55,8 @@ for o, a in opts: ic = icebox.iceconfig() if mode_8k: ic.setup_empty_8k() +elif mode_5k: + ic.setup_empty_5k() elif mode_384: ic.setup_empty_384() else: @@ -142,7 +150,7 @@ print("""# # # declares a special-purpose cell that is not part of the FPGA fabric # -# +# # .extra_bits # FUNCTION BANK_NUM ADDR_X ADDR_Y # ... @@ -233,21 +241,21 @@ print() def print_tile_nonrouting_bits(tile_type, idx): tx = idx[0] ty = idx[1] - + tile = ic.tile(tx, ty) - + print(".%s_tile_bits %d %d" % (tile_type, len(tile[0]), len(tile))) - + function_bits = dict() for entry in ic.tile_db(tx, ty): if not ic.tile_has_entry(tx, ty, entry): continue if entry[1] in ("routing", "buffer"): continue - + func = ".".join(entry[1:]) function_bits[func] = entry[0] - + for x in sorted(function_bits): print(" ".join([x] + function_bits[x])) print() @@ -318,4 +326,3 @@ for idx in sorted(all_tiles): assert (idx[0], idx[1], entry[2]) in seg_to_net print("%s %d" % (pattern, seg_to_net[(idx[0], idx[1], entry[2])])) print() - -- cgit v1.2.3 From a25c8679ac37df5219e1d7a8cdd932288cd596b1 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 23 Jun 2017 22:53:54 -0700 Subject: More work figuring out values in icebox.py --- icebox/icebox.py | 167 +++++++++++++++++++++++++++++++++++++---- icebox/icebox_vlog.py | 2 +- icefuzz/Makefile | 11 ++- icefuzz/cached_io.txt | 11 +++ icefuzz/database.py | 4 +- icefuzz/tests/io_latched_5k.sh | 27 +++++++ icepack/icepack.cc | 30 ++++++-- 7 files changed, 223 insertions(+), 29 deletions(-) create mode 100644 icefuzz/tests/io_latched_5k.sh (limited to 'icebox') diff --git a/icebox/icebox.py b/icebox/icebox.py index 79608be..577eaca 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -208,20 +208,28 @@ class iceconfig: assert False def tile_db(self, x, y): - if x == 0: return iotile_l_db + # Only these devices have IO on the left and right sides. + if self.device in ["384", "1k", "8k"]: + if x == 0: return iotile_l_db + if x == self.max_x: return iotile_r_db if y == 0: return iotile_b_db - if x == self.max_x: return iotile_r_db if y == self.max_y: return iotile_t_db if self.device == "1k": if (x, y) in self.logic_tiles: return logictile_db if (x, y) in self.ramb_tiles: return rambtile_db if (x, y) in self.ramt_tiles: return ramttile_db - if self.device == "8k": + elif self.device == "5k": + if (x, y) in self.logic_tiles: return logictile_5k_db + if (x, y) in self.ramb_tiles: return rambtile_5k_db + if (x, y) in self.ramt_tiles: return ramttile_5k_db + elif self.device == "8k": if (x, y) in self.logic_tiles: return logictile_8k_db if (x, y) in self.ramb_tiles: return rambtile_8k_db if (x, y) in self.ramt_tiles: return ramttile_8k_db - if self.device == "384": + elif self.device == "384": if (x, y) in self.logic_tiles: return logictile_384_db + + print("Tile type unknown at (%d, %d)" % (x, y)) assert False def tile_type(self, x, y): @@ -568,7 +576,9 @@ class iceconfig: for s in self.expand_net(queue.pop()): if s not in segments: segments.add(s) - assert s not in seen_segments + if s in seen_segments: + print("//", s, "has already been seen. Check your bitmapping.") + assert False seen_segments.add(s) seed_segments.discard(s) if s in connected_segments: @@ -1012,7 +1022,8 @@ def key_netname(netname): def run_checks_neigh(): print("Running consistency checks on neighbour finder..") ic = iceconfig() - ic.setup_empty_1k() + # ic.setup_empty_1k() + ic.setup_empty_5k() # ic.setup_empty_8k() # ic.setup_empty_384() @@ -1028,8 +1039,12 @@ def run_checks_neigh(): for x in range(ic.max_x+1): for y in range(ic.max_x+1): + # Skip the corners. if x in (0, ic.max_x) and y in (0, ic.max_y): continue + # Skip the sides of a 5k device. + if ic.device == "5k" and x in (0, ic.max_x): + continue add_segments((x, y), ic.tile_db(x, y)) if (x, y) in ic.logic_tiles: all_segments.add((x, y, "lutff_7/cout")) @@ -1091,6 +1106,16 @@ extra_bits_db = { (0, 330, 143): ("padin_glb_netwk", "6"), (0, 331, 143): ("padin_glb_netwk", "7"), }, + "5k": { + (0, 870, 270): ("padin_glb_netwk", "0"), + (0, 871, 270): ("padin_glb_netwk", "1"), + (1, 870, 271): ("padin_glb_netwk", "2"), + (1, 871, 271): ("padin_glb_netwk", "3"), + (1, 870, 270): ("padin_glb_netwk", "4"), + (1, 871, 270): ("padin_glb_netwk", "5"), + (0, 870, 271): ("padin_glb_netwk", "6"), + (0, 871, 271): ("padin_glb_netwk", "7"), + }, "8k": { (0, 870, 270): ("padin_glb_netwk", "0"), (0, 871, 270): ("padin_glb_netwk", "1"), @@ -1124,6 +1149,8 @@ gbufin_db = { ( 6, 0, 5), ( 6, 17, 4), ], + "5k": [ + ], "8k": [ (33, 16, 7), ( 0, 16, 6), @@ -1146,6 +1173,14 @@ gbufin_db = { ] } +# To figure these out: +# 1. Copy io_latched.sh and convert it for your pinout (like io_latched_5k.sh). +# 2. Run it. It will create an io_latched_.work directory with a bunch of files. +# 3. Grep the *.ve files in that directory for "'fabout')". The coordinates +# before it are where the io latches are. +# +# Note: This may not work if your icepack configuration of cell sizes is incorrect because +# icebox_vlog.py won't correctly interpret the meaning of particular bits. iolatch_db = { "1k": [ ( 0, 7), @@ -1153,6 +1188,10 @@ iolatch_db = { ( 5, 0), ( 8, 17), ], + "5k": [ + (14, 0), + (14, 31), + ], "8k": [ ( 0, 15), (33, 18), @@ -1167,12 +1206,20 @@ iolatch_db = { ], } +# The x, y cell locations of the WARMBOOT controls. Run tests/sb_warmboot.v +# through icecube.sh to determine these values. warmbootinfo_db = { "1k": { "BOOT": ( 12, 0, "fabout" ), "S0": ( 13, 1, "fabout" ), "S1": ( 13, 2, "fabout" ), }, + "5k": { + # These are the right locations but may be the wrong order. + "BOOT": ( 22, 0, "fabout" ), + "S0": ( 23, 0, "fabout" ), + "S1": ( 24, 0, "fabout" ), + }, "8k": { "BOOT": ( 31, 0, "fabout" ), "S0": ( 33, 1, "fabout" ), @@ -1293,6 +1340,99 @@ pllinfo_db = { "SDI": ( 4, 0, "fabout"), "SCLK": ( 3, 0, "fabout"), }, + "5k": { + "LOC" : (16, 0), + + # 3'b000 = "DISABLED" + # 3'b010 = "SB_PLL40_PAD" + # 3'b100 = "SB_PLL40_2_PAD" + # 3'b110 = "SB_PLL40_2F_PAD" + # 3'b011 = "SB_PLL40_CORE" + # 3'b111 = "SB_PLL40_2F_CORE" + "PLLTYPE_0": ( 16, 0, "PLLCONFIG_5"), + "PLLTYPE_1": ( 18, 0, "PLLCONFIG_1"), + "PLLTYPE_2": ( 18, 0, "PLLCONFIG_3"), + + # 3'b000 = "DELAY" + # 3'b001 = "SIMPLE" + # 3'b010 = "PHASE_AND_DELAY" + # 3'b110 = "EXTERNAL" + "FEEDBACK_PATH_0": ( 18, 0, "PLLCONFIG_5"), + "FEEDBACK_PATH_1": ( 15, 0, "PLLCONFIG_9"), + "FEEDBACK_PATH_2": ( 16, 0, "PLLCONFIG_1"), + + # 1'b0 = "FIXED" + # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111) + "DELAY_ADJMODE_FB": ( 17, 0, "PLLCONFIG_4"), + + # 1'b0 = "FIXED" + # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111) + "DELAY_ADJMODE_REL": ( 17, 0, "PLLCONFIG_9"), + + # 2'b00 = "GENCLK" + # 2'b01 = "GENCLK_HALF" + # 2'b10 = "SHIFTREG_90deg" + # 2'b11 = "SHIFTREG_0deg" + "PLLOUT_SELECT_A_0": ( 16, 0, "PLLCONFIG_6"), + "PLLOUT_SELECT_A_1": ( 16, 0, "PLLCONFIG_7"), + + # 2'b00 = "GENCLK" + # 2'b01 = "GENCLK_HALF" + # 2'b10 = "SHIFTREG_90deg" + # 2'b11 = "SHIFTREG_0deg" + "PLLOUT_SELECT_B_0": ( 16, 0, "PLLCONFIG_2"), + "PLLOUT_SELECT_B_1": ( 16, 0, "PLLCONFIG_3"), + + # Numeric Parameters + "SHIFTREG_DIV_MODE": ( 16, 0, "PLLCONFIG_4"), + "FDA_FEEDBACK_0": ( 16, 0, "PLLCONFIG_9"), + "FDA_FEEDBACK_1": ( 17, 0, "PLLCONFIG_1"), + "FDA_FEEDBACK_2": ( 17, 0, "PLLCONFIG_2"), + "FDA_FEEDBACK_3": ( 17, 0, "PLLCONFIG_3"), + "FDA_RELATIVE_0": ( 17, 0, "PLLCONFIG_5"), + "FDA_RELATIVE_1": ( 17, 0, "PLLCONFIG_6"), + "FDA_RELATIVE_2": ( 17, 0, "PLLCONFIG_7"), + "FDA_RELATIVE_3": ( 17, 0, "PLLCONFIG_8"), + "DIVR_0": ( 14, 0, "PLLCONFIG_1"), + "DIVR_1": ( 14, 0, "PLLCONFIG_2"), + "DIVR_2": ( 14, 0, "PLLCONFIG_3"), + "DIVR_3": ( 14, 0, "PLLCONFIG_4"), + "DIVF_0": ( 14, 0, "PLLCONFIG_5"), + "DIVF_1": ( 14, 0, "PLLCONFIG_6"), + "DIVF_2": ( 14, 0, "PLLCONFIG_7"), + "DIVF_3": ( 14, 0, "PLLCONFIG_8"), + "DIVF_4": ( 14, 0, "PLLCONFIG_9"), + "DIVF_5": ( 15, 0, "PLLCONFIG_1"), + "DIVF_6": ( 15, 0, "PLLCONFIG_2"), + "DIVQ_0": ( 15, 0, "PLLCONFIG_3"), + "DIVQ_1": ( 15, 0, "PLLCONFIG_4"), + "DIVQ_2": ( 15, 0, "PLLCONFIG_5"), + "FILTER_RANGE_0": ( 15, 0, "PLLCONFIG_6"), + "FILTER_RANGE_1": ( 15, 0, "PLLCONFIG_7"), + "FILTER_RANGE_2": ( 15, 0, "PLLCONFIG_8"), + "TEST_MODE": ( 16, 0, "PLLCONFIG_8"), + + # PLL Ports + "PLLOUT_A": ( 16, 0, 1), + "PLLOUT_B": ( 17, 0, 0), + "REFERENCECLK": ( 13, 0, "fabout"), + "EXTFEEDBACK": ( 14, 0, "fabout"), + "DYNAMICDELAY_0": ( 5, 0, "fabout"), + "DYNAMICDELAY_1": ( 6, 0, "fabout"), + "DYNAMICDELAY_2": ( 7, 0, "fabout"), + "DYNAMICDELAY_3": ( 8, 0, "fabout"), + "DYNAMICDELAY_4": ( 9, 0, "fabout"), + "DYNAMICDELAY_5": ( 10, 0, "fabout"), + "DYNAMICDELAY_6": ( 11, 0, "fabout"), + "DYNAMICDELAY_7": ( 12, 0, "fabout"), + "LOCK": ( 1, 1, "neigh_op_bnl_1"), + "BYPASS": ( 19, 0, "fabout"), + "RESETB": ( 20, 0, "fabout"), + "LATCHINPUTVALUE": ( 15, 0, "fabout"), + "SDO": ( 32, 1, "neigh_op_bnr_3"), + "SDI": ( 22, 0, "fabout"), + "SCLK": ( 21, 0, "fabout"), + }, "8k_0": { "LOC" : (16, 0), @@ -1481,8 +1621,6 @@ pllinfo_db = { }, } -# TODO(tannewt): Correct these values for 5k once we figure out how to get the -# info. padin_pio_db = { "1k": [ (13, 8, 1), # glb_netwk_0 @@ -1495,14 +1633,11 @@ padin_pio_db = { ( 6, 17, 1), # glb_netwk_7 ], "5k": [ - (33, 16, 1), - ( 0, 16, 1), - (17, 33, 0), - (17, 0, 0), - ( 0, 17, 0), - (33, 17, 0), - (16, 0, 1), - (16, 33, 1), + ( 6, 0, 1), + (19, 0, 1), + ( 6, 31, 0), + (12, 31, 1), + (13, 31, 0), ], "8k": [ (33, 16, 1), diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py index 4033f01..e046de1 100755 --- a/icebox/icebox_vlog.py +++ b/icebox/icebox_vlog.py @@ -728,7 +728,7 @@ for tile in ic.ramb_tiles: if len(wire_bits) > 1: return "{%s}" % ", ".join(wire_bits) return wire_bits[0] - if get_ram_config('PowerUp') == (ic.device == "8k"): + if get_ram_config('PowerUp') == (ic.device in ("8k", "5k")): if not strip_comments: text_func.append("// RAM TILE %d %d" % tile) text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else "")); diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 47aeb0c..b3e3b95 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -47,9 +47,14 @@ database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata ifneq ($(RAM_SUFFIX),) cp cached_ramb.txt bitdata_ramb.txt cp cached_ramt.txt bitdata_ramt.txt -else - cp cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt - cp cached_ramt$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt +endif +ifneq ($(RAM_SUFFIX),_8k) + cp cached_ramb_8k.txt bitdata_ramb_8k.txt + cp cached_ramt_8k.txt bitdata_ramt_8k.txt +endif +ifneq ($(RAM_SUFFIX),_5k) + cp cached_ramb_5k.txt bitdata_ramb_5k.txt + cp cached_ramt_5k.txt bitdata_ramt_5k.txt endif ICEDEVICE=$(DEVICECLASS) python3 database.py python3 export.py diff --git a/icefuzz/cached_io.txt b/icefuzz/cached_io.txt index ceab399..eb247af 100644 --- a/icefuzz/cached_io.txt +++ b/icefuzz/cached_io.txt @@ -553,9 +553,12 @@ (2 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_4 (2 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_4 (2 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_4 (2 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_4 +(2 2) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_4 (2 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_4 @@ -671,8 +674,12 @@ (3 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_5 (3 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_5 (3 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_5 +(3 2) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_5 (3 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_5 @@ -682,7 +689,9 @@ (3 3) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_3 (3 3) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_3 +(3 3) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_3 (3 3) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_3 (3 3) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_3 @@ -704,7 +713,9 @@ (3 5) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_6 +(3 5) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_6 (3 5) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_6 +(3 5) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_6 (3 5) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_6 (3 5) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_6 diff --git a/icefuzz/database.py b/icefuzz/database.py index 979b92b..50a28fc 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -138,11 +138,11 @@ with open("database_ramt.txt", "w") as f: for entry in read_database("bitdata_ramt.txt", "ramt"): print("\t".join(entry), file=f) -if device_class in ["5k", "8k"]: +for device_class in ["5k", "8k"]: with open("database_ramb_%s.txt" % (device_class, ), "w") as f: for entry in read_database("bitdata_ramb_%s.txt" % (device_class, ), "ramb_" + device_class): print("\t".join(entry), file=f) - with open("database_ramt_8k.txt", "w") as f: + with open("database_ramt_%s.txt" % (device_class, ), "w") as f: for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class): print("\t".join(entry), file=f) diff --git a/icefuzz/tests/io_latched_5k.sh b/icefuzz/tests/io_latched_5k.sh new file mode 100644 index 0000000..a43c77f --- /dev/null +++ b/icefuzz/tests/io_latched_5k.sh @@ -0,0 +1,27 @@ +#!/bin/bash + +set -ex + +mkdir -p io_latched_5k.work +cd io_latched_5k.work + +pins=" +2 3 4 6 9 10 11 12 +13 18 19 20 21 23 +25 26 27 28 31 32 34 35 36 +37 38 42 43 44 45 46 47 48 +" +pins="$( echo $pins )" + +for pin in $pins ; do + pf="io_latched_$pin" + cp ../io_latched.v ${pf}.v + read pin_latch pin_data < <( echo $pins | tr ' ' '\n' | grep -v $pin | sort -R; ) + { + echo "set_io pin $pin" + echo "set_io latch_in $pin_latch" + echo "set_io data_out $pin_data" + } > ${pf}.pcf + ICEDEV=up5k-sg48 bash ../../icecube.sh ${pf}.v + ../../../icebox/icebox_vlog.py -SP ${pf}.psb ${pf}.asc > ${pf}.ve +done diff --git a/icepack/icepack.cc b/icepack/icepack.cc index 90c5eb1..327a092 100644 --- a/icepack/icepack.cc +++ b/icepack/icepack.cc @@ -415,10 +415,11 @@ void FpgaConfig::write_bits(std::ostream &ofs) const for (auto byte : this->initblop) ofs << byte; - debug("Writing preamble.\n"); + info("Writing preamble.\n"); write_byte(ofs, crc_value, file_offset, 0x7E); write_byte(ofs, crc_value, file_offset, 0xAA); write_byte(ofs, crc_value, file_offset, 0x99); + info("blah"); write_byte(ofs, crc_value, file_offset, 0x7E); debug("Setting freqrange to '%s'.\n", this->freqrange.c_str()); @@ -773,7 +774,7 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const { CramIndexConverter cic(this, x, y); - if (cic.tile_type == "corner") + if (cic.tile_type == "corner" || cic.tile_type == "unsupported") continue; ofs << stringf(".%s_tile %d %d\n", cic.tile_type.c_str(), x, y); @@ -783,6 +784,12 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const int cram_bank, cram_x, cram_y; cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); tile_bits.insert(tile_bit_t(cram_bank, cram_x, cram_y)); + if (cram_x > int(this->cram[cram_bank].size())) { + error("cram_x %d (bit %d, %d) larger than bank size %lu\n", cram_x, bit_x, bit_y, this->cram[cram_bank].size()); + } + if (cram_y > int(this->cram[cram_bank][cram_x].size())) { + error("cram_y %d larger than bank size %lu\n", cram_y, this->cram[cram_bank][cram_x].size()); + } ofs << (this->cram[cram_bank][cram_x][cram_y] ? '1' : '0'); } ofs << '\n'; @@ -800,11 +807,11 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const int bram_bank, bram_x, bram_y; bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y); if (bram_x >= int(this->bram[bram_bank].size())) { - error("bram_x %u higher than loaded bram size %lu\n", bram_x, this->bram[bram_bank].size()); + error("%d %d bram_x %d higher than loaded bram size %lu\n",bit_x+i, bit_y, bram_x, this->bram[bram_bank].size()); break; } if (bram_y >= int(this->bram[bram_bank][bram_x].size())) { - error("bram_y %u higher than loaded bram size %lu\n", bram_y, this->bram[bram_bank][bram_x].size()); + error("bram_y %d higher than loaded bram size %lu\n", bram_y, this->bram[bram_bank][bram_x].size()); break; } if (this->bram[bram_bank][bram_x][bram_y]) @@ -905,7 +912,7 @@ vector FpgaConfig::chip_cols() const if (this->device == "384") return vector({18, 54, 54, 54, 54}); if (this->device == "1k") return vector({18, 54, 54, 42, 54, 54, 54}); // Its IPConnect or Mutiplier block, five logic, ram, six logic. - if (this->device == "5k") return vector({18, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54}); + if (this->device == "5k") return vector({54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54}); if (this->device == "8k") return vector({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54}); panic("Unknown chip type '%s'.\n", this->device.c_str()); } @@ -913,6 +920,8 @@ vector FpgaConfig::chip_cols() const string FpgaConfig::tile_type(int x, int y) const { if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner"; + // The sides on the 5k devices are unsupported tile types. + if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) return "unsupported"; if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io"; if (this->device == "384") return "logic"; @@ -942,6 +951,7 @@ int FpgaConfig::tile_width(const string &type) const if (type == "ramb") return 42; if (type == "ramt") return 42; if (type == "io") return 18; + if (type == "unsupported") return 76; panic("Unknown tile type '%s'.\n", type.c_str()); } @@ -1004,7 +1014,11 @@ CramIndexConverter::CramIndexConverter(const FpgaConfig *fpga, int tile_x, int t this->left_right_io = this->tile_x == 0 || this->tile_x == chip_width+1; this->right_half = this->tile_x > chip_width / 2; - this->top_half = this->tile_y > chip_height / 2; + if (this->fpga->device == "5k") { + this->top_half = this->tile_y > chip_height / 3; + } else { + this->top_half = this->tile_y > chip_height / 2; + } this->bank_num = 0; if (this->top_half) this->bank_num |= 1; @@ -1086,8 +1100,10 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t int y_offset = this->tile_y - 1; if (!top_half) { this->bank_num |= 1; - } else { + } else if (this->fpga->device == "5k") { y_offset = this->tile_y - chip_height / 3; + } else { + y_offset = this->tile_y - chip_height / 2; } if (right_half) this->bank_num |= 2; -- cgit v1.2.3