From ec3ad586835ec13cd5b3c32f6c2b7580247c562b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 29 Nov 2017 12:37:40 +0000 Subject: Figure out missing SPI config bits, and add to chipdb --- icefuzz/tests/ip/up5k_I2C_data.txt | 4 ++-- icefuzz/tests/ip/up5k_SPI_data.txt | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'icefuzz/tests') diff --git a/icefuzz/tests/ip/up5k_I2C_data.txt b/icefuzz/tests/ip/up5k_I2C_data.txt index a891b0c..f433663 100644 --- a/icefuzz/tests/ip/up5k_I2C_data.txt +++ b/icefuzz/tests/ip/up5k_I2C_data.txt @@ -43,8 +43,8 @@ ("I2C", (25, 31, 0)): { "I2CIRQ": (25, 30, "slf_op_7"), "I2CWKUP": (25, 29, "slf_op_5"), - "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_0"), - "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_1"), + "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_1"), + "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_0"), "SBACKO": (25, 30, "slf_op_6"), "SBADRI0": (25, 30, "lutff_1/in_0"), "SBADRI1": (25, 30, "lutff_2/in_0"), diff --git a/icefuzz/tests/ip/up5k_SPI_data.txt b/icefuzz/tests/ip/up5k_SPI_data.txt index 149c93a..be4be44 100644 --- a/icefuzz/tests/ip/up5k_SPI_data.txt +++ b/icefuzz/tests/ip/up5k_SPI_data.txt @@ -47,6 +47,10 @@ "SOE": (0, 20, "slf_op_5"), "SPIIRQ": (0, 20, "slf_op_2"), "SPIWKUP": (0, 20, "slf_op_3"), + "SPI_ENABLE_0": (7, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (7, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_2": (6, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_3": (6, 0, "cbit2usealt_in_1"), }, ("SPI", (25, 0, 1)): { "MCSNO0": (25, 21, "slf_op_2"), @@ -97,4 +101,8 @@ "SOE": (25, 20, "slf_op_5"), "SPIIRQ": (25, 20, "slf_op_2"), "SPIWKUP": (25, 20, "slf_op_3"), + "SPI_ENABLE_0": (23, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (24, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_2": (23, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_3": (24, 0, "cbit2usealt_in_1"), }, -- cgit v1.2.3 From 4b16c3735c0c183837994a4b4b07296f0bbba57c Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 13 Jan 2018 18:51:27 +0000 Subject: I³C IO reverse engineered and documented MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- docs/ultraplus.html | 13 +++++++++++++ icefuzz/tests/sb_io_i3c.pcf | 8 ++++++++ icefuzz/tests/sb_io_i3c.v | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 icefuzz/tests/sb_io_i3c.pcf create mode 100644 icefuzz/tests/sb_io_i3c.v (limited to 'icefuzz/tests') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index b5dda62..11e249d 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -290,6 +290,19 @@ can be used as an open-drain IO using the standard IO cell.

+

I3C capable IO

+

The UltraPlus devices have two IO pins designed for the new MIPI I3C standard (pins 23 and 25 in the SG48 package), +compared to normal IO pins they have two switchable pullups each. One of these pullups, the weak pullup, is fixed at 100k and the +other can be set to 3.3k, 6.8k or 10k using the mechanism above. The pullup control signals do not +connect directly to the IO tile, but instead connect through an IPConnect tile.

+ +

The connections are listed below:

+ + + + +
SignalPin 23
(19, 31, 0)		Pin 25
(19, 31, 1)
PU_ENB(25, 27, lutff_6/in_0)(25, 27, lutff_7/in_0)
WEAK_PU_ENB(25, 27, lutff_4/in_0)(25, 27, lutff_5/in_0)
+

Hard IP

The UltraPlus devices contain three types of Hard IP: I2C (SB_I2C), SPI (SB_SPI), and LED PWM generation diff --git a/icefuzz/tests/sb_io_i3c.pcf b/icefuzz/tests/sb_io_i3c.pcf new file mode 100644 index 0000000..cb3cd30 --- /dev/null +++ b/icefuzz/tests/sb_io_i3c.pcf @@ -0,0 +1,8 @@ +set_io pin_23 23 +set_io pin_25 25 + +set_io pin_23_puen 2 +set_io pin_23_wkpuen 3 + +set_io pin_25_puen 4 +set_io pin_25_wkpuen 6 diff --git a/icefuzz/tests/sb_io_i3c.v b/icefuzz/tests/sb_io_i3c.v new file mode 100644 index 0000000..5237283 --- /dev/null +++ b/icefuzz/tests/sb_io_i3c.v @@ -0,0 +1,35 @@ + +module top ( + inout pin_23, + inout pin_25, + input pin_23_puen, + input pin_23_wkpuen, + input pin_25_puen, + input pin_25_wkpuen); + + (* PULLUP_RESISTOR = "3P3K" *) + SB_IO_I3C #( + .PIN_TYPE(6'b000001), + .PULLUP(1'b1), + .WEAK_PULLUP(1'b1), + + .NEG_TRIGGER(1'b0) + ) IO_PIN_0 ( + .PACKAGE_PIN(pin_23), + .PU_ENB(pin_23_puen), + .WEAK_PU_ENB(pin_23_wkpuen) + ) ; + + (* PULLUP_RESISTOR = "3P3K" *) + SB_IO_I3C #( + .PIN_TYPE(6'b000001), + .PULLUP(1'b1), + .WEAK_PULLUP(1'b1), + + .NEG_TRIGGER(1'b0) + ) IO_PIN_1 ( + .PACKAGE_PIN(pin_25), + .PU_ENB(pin_25_puen), + .WEAK_PU_ENB(pin_25_wkpuen) + ); +endmodule -- cgit v1.2.3