From 629621642f4dd2d857edc914384b78161c438327 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Nov 2017 16:05:42 +0000 Subject: Preparations for DSP and IpCon fuzzing --- icefuzz/Makefile | 37 +++++++++++++++++++++++++++++++++++-- icefuzz/cached_dsp0_5k.txt | 0 icefuzz/cached_dsp1_5k.txt | 0 icefuzz/cached_dsp2_5k.txt | 0 icefuzz/cached_dsp3_5k.txt | 0 icefuzz/cached_ipcon_5k.txt | 0 icefuzz/database.py | 18 +++++++++++++++++- icefuzz/extract.py | 20 ++++++++++++++++++-- 8 files changed, 70 insertions(+), 5 deletions(-) create mode 100644 icefuzz/cached_dsp0_5k.txt create mode 100644 icefuzz/cached_dsp1_5k.txt create mode 100644 icefuzz/cached_dsp2_5k.txt create mode 100644 icefuzz/cached_dsp3_5k.txt create mode 100644 icefuzz/cached_ipcon_5k.txt (limited to 'icefuzz') diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 2e42889..57e9af0 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -43,7 +43,7 @@ ifneq ($(DEVICECLASS),384) TESTS += aig endif -database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt +database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt ifneq ($(RAM_SUFFIX),) cp cached_ramb.txt bitdata_ramb.txt cp cached_ramt.txt bitdata_ramt.txt @@ -55,6 +55,12 @@ endif ifneq ($(RAM_SUFFIX),_5k) cp cached_ramb_5k.txt bitdata_ramb_5k.txt cp cached_ramt_5k.txt bitdata_ramt_5k.txt + cp cached_dsp0_5k.txt bitdata_dsp0_5k.txt + cp cached_dsp1_5k.txt bitdata_dsp1_5k.txt + cp cached_dsp2_5k.txt bitdata_dsp2_5k.txt + cp cached_dsp3_5k.txt bitdata_dsp3_5k.txt + cp cached_ipcon_5k.txt bitdata_ipcon_5k.txt + endif ICEDEVICE=$(DEVICECLASS) python3 database.py python3 export.py @@ -62,6 +68,11 @@ endif diff -U0 cached_logic.txt bitdata_logic.txt || cp -v bitdata_logic.txt cached_logic.txt diff -U0 cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt || cp -v bitdata_ramb$(RAM_SUFFIX).txt cached_ramb$(RAM_SUFFIX).txt diff -U0 cached_ramt$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt || cp -v bitdata_ramt$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt + diff -U0 cached_dsp0_5k.txt bitdata_dsp0_5k.txt || cp -v bitdata_dsp0_5k.txt cached_dsp0_5k.txt + diff -U0 cached_dsp1_5k.txt bitdata_dsp1_5k.txt || cp -v bitdata_dsp1_5k.txt cached_dsp1_5k.txt + diff -U0 cached_dsp2_5k.txt bitdata_dsp2_5k.txt || cp -v bitdata_dsp2_5k.txt cached_dsp2_5k.txt + diff -U0 cached_dsp3_5k.txt bitdata_dsp3_5k.txt || cp -v bitdata_dsp3_5k.txt cached_dsp3_5k.txt + diff -U0 cached_ipcon_5k.txt bitdata_ipcon_5k.txt || cp -v bitdata_ipcon_5k.txt cached_ipcon_5k.txt timings: ifeq ($(DEVICECLASS),8k) @@ -97,11 +108,18 @@ timings_html: python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html python3 timings.py -h tmedges.txt -t timings_lp384.txt -l "LP384 with default temp/volt settings" > timings_lp384.html -data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt +data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cached_ramt$(RAM_SUFFIX).txt cached_dsp0_5k.txt cached_dsp1_5k.txt cached_dsp2_5k.txt cached_dsp3_5k.txt cached_ipcon_5k.txt gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new gawk '{ print "ramb$(RAM_SUFFIX)", $$0; }' cached_ramb$(RAM_SUFFIX).txt >> data_cached.new gawk '{ print "ramt$(RAM_SUFFIX)", $$0; }' cached_ramt$(RAM_SUFFIX).txt >> data_cached.new + + gawk '{ print "dsp0_5k", $$0; }' cached_dsp0_5k.txt >> data_cached.new + gawk '{ print "dsp1_5k", $$0; }' cached_dsp1_5k.txt >> data_cached.new + gawk '{ print "dsp2_5k", $$0; }' cached_dsp2_5k.txt >> data_cached.new + gawk '{ print "dsp3_5k", $$0; }' cached_dsp3_5k.txt >> data_cached.new + gawk '{ print "ipcon_5k", $$0; }' cached_ipcon_5k.txt >> data_cached.new + mv data_cached.new data_cached.txt bitdata_io.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) @@ -116,6 +134,21 @@ bitdata_ramb$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_, bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^ramt$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ +bitdata_dsp0_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^dsp0_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + +bitdata_dsp1_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^dsp1_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + +bitdata_dsp2_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^dsp2_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + +bitdata_dsp3_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^dsp3_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + +bitdata_ipcon_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) + grep ^ipcon_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) ../icepack/icepack: diff --git a/icefuzz/cached_dsp0_5k.txt b/icefuzz/cached_dsp0_5k.txt new file mode 100644 index 0000000..e69de29 diff --git a/icefuzz/cached_dsp1_5k.txt b/icefuzz/cached_dsp1_5k.txt new file mode 100644 index 0000000..e69de29 diff --git a/icefuzz/cached_dsp2_5k.txt b/icefuzz/cached_dsp2_5k.txt new file mode 100644 index 0000000..e69de29 diff --git a/icefuzz/cached_dsp3_5k.txt b/icefuzz/cached_dsp3_5k.txt new file mode 100644 index 0000000..e69de29 diff --git a/icefuzz/cached_ipcon_5k.txt b/icefuzz/cached_ipcon_5k.txt new file mode 100644 index 0000000..e69de29 diff --git a/icefuzz/database.py b/icefuzz/database.py index 8cb81d8..f8f3ccf 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -28,6 +28,9 @@ def read_database(filename, tile_type): line = re.sub(r"^Ram config bit:", "RamConfig", line) line = re.sub(r"^PLL config bit:", "PLL", line) line = re.sub(r"^Icegate Enable bit:", "Icegate", line) + line = re.sub(r"^MAC16 functional bit:", "DspConfig", line) + line = re.sub(r"^Hard IP config bit:", "IpConfig", line) + line = line.split() if line[0] == "routing": if line[3] == "wire_gbuf/in": line[3] = "fabout" @@ -61,7 +64,7 @@ def read_database(filename, tile_type): line[1] = re.sub(r"glb_netwk_", "1k_glb_netwk_", line[1]) raw_db.append((bit, (line[0], line[1]))) elif line[0] == "Cascade": - match = re.match("LH_LC0(\d)_inmux02_5", line[1]) + match = re.match("(MULT\d|LH)_LC0(\d)_inmux02_5", line[1]) if match: raw_db.append((bit, ("buffer", "wire_logic_cluster/lc_%d/lout" % (int(match.group(1))-1), "input_2_%s" % match.group(1)))) else: @@ -87,6 +90,11 @@ def read_database(filename, tile_type): raw_db.append((bit, (line[0],))) elif line[0] == "Carry_In_Mux": continue + elif line[0] == "DspConfig": + line[1] = re.sub(r"MULT\d_bram_cbit_", "CBIT_", line[1]) + elif line[0] == "IpConfig": + line[1] = re.sub(r"MULT\d_bram_cbit_", "CBIT_", line[1]) #not a typo, sometimes IP config bits are in DSP tiles and use a MULT prefix... + line[1] = re.sub(r"IPCON_bram_cbit_", "CBIT_", line[1]) else: print("unsupported statement: %s: %s" % (bit, line)) assert False @@ -149,3 +157,11 @@ for device_class in ["5k", "8k"]: with open("database_ramt_%s.txt" % (device_class, ), "w") as f: for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class): print("\t".join(entry), file=f) +if device_class == "5k": + for dsp_idx in range(4): + with open("database_dsp%d_5k.txt" % (dsp_idx, ), "w") as f: + for entry in read_database("bitdata_dsp%d_5k.txt" % (dsp_idx, ), "dsp%d_5" % (dsp_idx, )): + print("\t".join(entry), file=f) + with open("database_ipcon.txt", "w") as f: + for entry in read_database("bitdata_ipcon.txt", "ipcon"): + print("\t".join(entry), file=f) \ No newline at end of file diff --git a/icefuzz/extract.py b/icefuzz/extract.py index 75be225..6f8b8cc 100644 --- a/icefuzz/extract.py +++ b/icefuzz/extract.py @@ -37,8 +37,24 @@ for filename in sys.argv[1:]: else: cur_text_db = text_db.setdefault("ramt_" + device_class if device_class in ["5k", "8k"] else "ramt", set()) ignore = False - elif device_class == "5k" and line.startswith(("IpCon", "DSP")): - ignore = True + elif device_class == "5k" and line.startswith("IpCon"): + cur_text_db = text_db.setdefault("ipcon_5k", set()) + ignore = False + elif device_class == "5k" and line.startswith("DSP"): + match = re.match(r"DSP_Tile_\d+_(\d+)", line) + ypos = int(match.group(1)) + dsp_idx = None + if ypos in [5, 10, 15, 23]: + dsp_idx = 0 + if ypos in [6, 11, 16, 24]: + dsp_idx = 1 + if ypos in [7, 12, 17, 25]: + dsp_idx = 2 + if ypos in [8, 13, 18, 26]: + dsp_idx = 3 + assert dsp_idx != None + cur_text_db = text_db.setdefault("dsp%d_5k" % dsp_idx, set()) + ignore = False elif not ignore: print("'" + line + "'") assert line.startswith(" ") -- cgit v1.2.3 From 96b527bfeffb703baaa4119e48aae83ba0aa37cf Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Nov 2017 18:57:09 +0000 Subject: Create icefuzz scripts for DSP and 5k --- icefuzz/Makefile | 17 +- icefuzz/cached_dsp0_5k.txt | 3272 ++++++++++++++++++++++++++++++++++++++++ icefuzz/cached_dsp1_5k.txt | 3033 +++++++++++++++++++++++++++++++++++++ icefuzz/cached_dsp2_5k.txt | 3057 +++++++++++++++++++++++++++++++++++++ icefuzz/cached_dsp3_5k.txt | 3159 +++++++++++++++++++++++++++++++++++++++ icefuzz/cached_ipcon_5k.txt | 3471 +++++++++++++++++++++++++++++++++++++++++++ icefuzz/cached_ramb_5k.txt | 494 +----- icefuzz/cached_ramt_5k.txt | 459 +----- icefuzz/database.py | 27 +- icefuzz/fuzzconfig.py | 8 +- icefuzz/glbcheck.py | 44 +- icefuzz/make_dsp.py | 206 +++ icefuzz/make_upip.py | 218 +++ 13 files changed, 16479 insertions(+), 986 deletions(-) create mode 100755 icefuzz/make_dsp.py create mode 100755 icefuzz/make_upip.py (limited to 'icefuzz') diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 57e9af0..3aa02ef 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -42,8 +42,11 @@ ifneq ($(DEVICECLASS),384) TESTS += pll TESTS += aig endif - -database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt +ifeq ($(DEVICECLASS),5k) + TESTS += dsp + TESTS += upip +endif +database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt bitdata_dsp0_5k.txt bitdata_dsp1_5k.txt bitdata_dsp2_5k.txt bitdata_dsp3_5k.txt bitdata_ipcon_5k.txt ifneq ($(RAM_SUFFIX),) cp cached_ramb.txt bitdata_ramb.txt cp cached_ramt.txt bitdata_ramt.txt @@ -135,19 +138,19 @@ bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_, grep ^ramt$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp0_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp0_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp0_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp1_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp1_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp1_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp2_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp2_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp2_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp3_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp3_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp3_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_ipcon_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^ipcon_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^ipcon_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) diff --git a/icefuzz/cached_dsp0_5k.txt b/icefuzz/cached_dsp0_5k.txt index e69de29..8cfe2ba 100644 --- a/icefuzz/cached_dsp0_5k.txt +++ b/icefuzz/cached_dsp0_5k.txt @@ -0,0 +1,3272 @@ +(0 10) routing glb_netwk_2 glb2local_2 +(0 10) routing glb_netwk_3 glb2local_2 +(0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 +(0 11) routing glb_netwk_3 glb2local_2 +(0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_2 glb2local_3 +(0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 +(0 13) routing glb_netwk_1 glb2local_3 +(0 13) routing glb_netwk_3 glb2local_3 +(0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 +(0 14) routing glb_netwk_4 wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 6) routing glb_netwk_2 glb2local_0 +(0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 +(0 7) routing glb_netwk_1 glb2local_0 +(0 7) routing glb_netwk_3 glb2local_0 +(0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_2 glb2local_1 +(0 8) routing glb_netwk_3 glb2local_1 +(0 8) routing glb_netwk_6 glb2local_1 +(0 8) routing glb_netwk_7 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 +(0 9) routing glb_netwk_5 glb2local_1 +(0 9) routing glb_netwk_7 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 glb2local_2 +(1 11) routing glb_netwk_5 glb2local_2 +(1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 +(1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 +(1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 +(1 9) routing glb_netwk_5 glb2local_1 +(1 9) routing glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_7 glb2local_1 +(10 0) routing sp4_h_l_40 sp4_h_r_1 +(10 0) routing sp4_h_l_47 sp4_h_r_1 +(10 0) routing sp4_v_b_7 sp4_h_r_1 +(10 0) routing sp4_v_t_45 sp4_h_r_1 +(10 1) routing sp4_h_l_42 sp4_v_b_1 +(10 1) routing sp4_h_r_8 sp4_v_b_1 +(10 1) routing sp4_v_t_40 sp4_v_b_1 +(10 1) routing sp4_v_t_47 sp4_v_b_1 +(10 10) routing sp4_h_r_11 sp4_h_l_42 +(10 10) routing sp4_h_r_4 sp4_h_l_42 +(10 10) routing sp4_v_b_2 sp4_h_l_42 +(10 10) routing sp4_v_t_36 sp4_h_l_42 +(10 11) routing sp4_h_l_39 sp4_v_t_42 +(10 11) routing sp4_h_r_1 sp4_v_t_42 +(10 11) routing sp4_v_b_11 sp4_v_t_42 +(10 11) routing sp4_v_b_4 sp4_v_t_42 +(10 12) routing sp4_h_l_39 sp4_h_r_10 +(10 12) routing sp4_h_l_42 sp4_h_r_10 +(10 12) routing sp4_v_b_4 sp4_h_r_10 +(10 12) routing sp4_v_t_40 sp4_h_r_10 +(10 13) routing sp4_h_l_41 sp4_v_b_10 +(10 13) routing sp4_h_r_5 sp4_v_b_10 +(10 13) routing sp4_v_t_39 sp4_v_b_10 +(10 13) routing sp4_v_t_42 sp4_v_b_10 +(10 14) routing sp4_h_r_2 sp4_h_l_47 +(10 14) routing sp4_h_r_7 sp4_h_l_47 +(10 14) routing sp4_v_b_5 sp4_h_l_47 +(10 14) routing sp4_v_t_41 sp4_h_l_47 +(10 15) routing sp4_h_l_40 sp4_v_t_47 +(10 15) routing sp4_h_r_4 sp4_v_t_47 +(10 15) routing sp4_v_b_2 sp4_v_t_47 +(10 15) routing sp4_v_b_7 sp4_v_t_47 +(10 2) routing sp4_h_r_10 sp4_h_l_36 +(10 2) routing sp4_h_r_5 sp4_h_l_36 +(10 2) routing sp4_v_b_8 sp4_h_l_36 +(10 2) routing sp4_v_t_42 sp4_h_l_36 +(10 3) routing sp4_h_l_45 sp4_v_t_36 +(10 3) routing sp4_h_r_7 sp4_v_t_36 +(10 3) routing sp4_v_b_10 sp4_v_t_36 +(10 3) routing sp4_v_b_5 sp4_v_t_36 +(10 4) routing sp4_h_l_36 sp4_h_r_4 +(10 4) routing sp4_h_l_45 sp4_h_r_4 +(10 4) routing sp4_v_b_10 sp4_h_r_4 +(10 4) routing sp4_v_t_46 sp4_h_r_4 +(10 5) routing sp4_h_l_47 sp4_v_b_4 +(10 5) routing sp4_h_r_11 sp4_v_b_4 +(10 5) routing sp4_v_t_36 sp4_v_b_4 +(10 5) routing sp4_v_t_45 sp4_v_b_4 +(10 6) routing sp4_h_r_8 sp4_h_l_41 +(10 6) routing sp4_v_b_11 sp4_h_l_41 +(10 6) routing sp4_v_t_47 sp4_h_l_41 +(10 7) routing sp4_h_l_46 sp4_v_t_41 +(10 7) routing sp4_h_r_10 sp4_v_t_41 +(10 7) routing sp4_v_b_1 sp4_v_t_41 +(10 7) routing sp4_v_b_8 sp4_v_t_41 +(10 8) routing sp4_h_l_41 sp4_h_r_7 +(10 8) routing sp4_h_l_46 sp4_h_r_7 +(10 8) routing sp4_v_b_1 sp4_h_r_7 +(10 8) routing sp4_v_t_39 sp4_h_r_7 +(10 9) routing sp4_h_l_36 sp4_v_b_7 +(10 9) routing sp4_h_r_2 sp4_v_b_7 +(10 9) routing sp4_v_t_41 sp4_v_b_7 +(10 9) routing sp4_v_t_46 sp4_v_b_7 +(11 0) routing sp4_h_l_45 sp4_v_b_2 +(11 0) routing sp4_h_r_9 sp4_v_b_2 +(11 0) routing sp4_v_t_43 sp4_v_b_2 +(11 0) routing sp4_v_t_46 sp4_v_b_2 +(11 1) routing sp4_h_l_39 sp4_h_r_2 +(11 1) routing sp4_h_l_43 sp4_h_r_2 +(11 1) routing sp4_v_b_2 sp4_h_r_2 +(11 1) routing sp4_v_b_8 sp4_h_r_2 +(11 10) routing sp4_h_l_38 sp4_v_t_45 +(11 10) routing sp4_h_r_2 sp4_v_t_45 +(11 10) routing sp4_v_b_0 sp4_v_t_45 +(11 10) routing sp4_v_b_5 sp4_v_t_45 +(11 11) routing sp4_h_r_0 sp4_h_l_45 +(11 11) routing sp4_h_r_8 sp4_h_l_45 +(11 11) routing sp4_v_t_39 sp4_h_l_45 +(11 11) routing sp4_v_t_45 sp4_h_l_45 +(11 12) routing sp4_h_l_40 sp4_v_b_11 +(11 12) routing sp4_h_r_6 sp4_v_b_11 +(11 12) routing sp4_v_t_38 sp4_v_b_11 +(11 12) routing sp4_v_t_45 sp4_v_b_11 +(11 13) routing sp4_h_l_46 sp4_h_r_11 +(11 13) routing sp4_v_b_11 sp4_h_r_11 +(11 13) routing sp4_v_b_5 sp4_h_r_11 +(11 14) routing sp4_h_l_43 sp4_v_t_46 +(11 14) routing sp4_h_r_5 sp4_v_t_46 +(11 14) routing sp4_v_b_3 sp4_v_t_46 +(11 14) routing sp4_v_b_8 sp4_v_t_46 +(11 15) routing sp4_v_t_40 sp4_h_l_46 +(11 15) routing sp4_v_t_46 sp4_h_l_46 +(11 2) routing sp4_h_l_44 sp4_v_t_39 +(11 2) routing sp4_h_r_8 sp4_v_t_39 +(11 2) routing sp4_v_b_11 sp4_v_t_39 +(11 2) routing sp4_v_b_6 sp4_v_t_39 +(11 3) routing sp4_h_r_2 sp4_h_l_39 +(11 3) routing sp4_h_r_6 sp4_h_l_39 +(11 3) routing sp4_v_t_39 sp4_h_l_39 +(11 3) routing sp4_v_t_45 sp4_h_l_39 +(11 4) routing sp4_h_l_46 sp4_v_b_5 +(11 4) routing sp4_h_r_0 sp4_v_b_5 +(11 4) routing sp4_v_t_39 sp4_v_b_5 +(11 4) routing sp4_v_t_44 sp4_v_b_5 +(11 5) routing sp4_h_l_40 sp4_h_r_5 +(11 5) routing sp4_h_l_44 sp4_h_r_5 +(11 5) routing sp4_v_b_11 sp4_h_r_5 +(11 5) routing sp4_v_b_5 sp4_h_r_5 +(11 6) routing sp4_h_l_37 sp4_v_t_40 +(11 6) routing sp4_h_r_11 sp4_v_t_40 +(11 6) routing sp4_v_b_2 sp4_v_t_40 +(11 6) routing sp4_v_b_9 sp4_v_t_40 +(11 7) routing sp4_h_r_9 sp4_h_l_40 +(11 7) routing sp4_v_t_40 sp4_h_l_40 +(11 7) routing sp4_v_t_46 sp4_h_l_40 +(11 8) routing sp4_h_l_39 sp4_v_b_8 +(11 8) routing sp4_h_r_3 sp4_v_b_8 +(11 8) routing sp4_v_t_37 sp4_v_b_8 +(11 8) routing sp4_v_t_40 sp4_v_b_8 +(11 9) routing sp4_h_l_37 sp4_h_r_8 +(11 9) routing sp4_h_l_45 sp4_h_r_8 +(11 9) routing sp4_v_b_2 sp4_h_r_8 +(11 9) routing sp4_v_b_8 sp4_h_r_8 +(12 0) routing sp4_h_l_46 sp4_h_r_2 +(12 0) routing sp4_v_b_2 sp4_h_r_2 +(12 0) routing sp4_v_b_8 sp4_h_r_2 +(12 0) routing sp4_v_t_39 sp4_h_r_2 +(12 1) routing sp4_h_l_39 sp4_v_b_2 +(12 1) routing sp4_h_l_45 sp4_v_b_2 +(12 1) routing sp4_h_r_2 sp4_v_b_2 +(12 1) routing sp4_v_t_46 sp4_v_b_2 +(12 10) routing sp4_v_b_8 sp4_h_l_45 +(12 10) routing sp4_v_t_39 sp4_h_l_45 +(12 10) routing sp4_v_t_45 sp4_h_l_45 +(12 11) routing sp4_h_l_45 sp4_v_t_45 +(12 11) routing sp4_h_r_2 sp4_v_t_45 +(12 11) routing sp4_h_r_8 sp4_v_t_45 +(12 11) routing sp4_v_b_5 sp4_v_t_45 +(12 12) routing sp4_h_l_45 sp4_h_r_11 +(12 12) routing sp4_v_b_11 sp4_h_r_11 +(12 12) routing sp4_v_b_5 sp4_h_r_11 +(12 12) routing sp4_v_t_46 sp4_h_r_11 +(12 13) routing sp4_h_l_40 sp4_v_b_11 +(12 13) routing sp4_h_l_46 sp4_v_b_11 +(12 13) routing sp4_h_r_11 sp4_v_b_11 +(12 13) routing sp4_v_t_45 sp4_v_b_11 +(12 14) routing sp4_h_r_8 sp4_h_l_46 +(12 14) routing sp4_v_b_11 sp4_h_l_46 +(12 14) routing sp4_v_t_40 sp4_h_l_46 +(12 14) routing sp4_v_t_46 sp4_h_l_46 +(12 15) routing sp4_h_l_46 sp4_v_t_46 +(12 15) routing sp4_h_r_11 sp4_v_t_46 +(12 15) routing sp4_h_r_5 sp4_v_t_46 +(12 15) routing sp4_v_b_8 sp4_v_t_46 +(12 2) routing sp4_v_b_2 sp4_h_l_39 +(12 2) routing sp4_v_t_39 sp4_h_l_39 +(12 2) routing sp4_v_t_45 sp4_h_l_39 +(12 3) routing sp4_h_l_39 sp4_v_t_39 +(12 3) routing sp4_h_r_2 sp4_v_t_39 +(12 3) routing sp4_h_r_8 sp4_v_t_39 +(12 3) routing sp4_v_b_11 sp4_v_t_39 +(12 4) routing sp4_h_l_39 sp4_h_r_5 +(12 4) routing sp4_v_b_11 sp4_h_r_5 +(12 4) routing sp4_v_b_5 sp4_h_r_5 +(12 4) routing sp4_v_t_40 sp4_h_r_5 +(12 5) routing sp4_h_l_40 sp4_v_b_5 +(12 5) routing sp4_h_l_46 sp4_v_b_5 +(12 5) routing sp4_h_r_5 sp4_v_b_5 +(12 5) routing sp4_v_t_39 sp4_v_b_5 +(12 6) routing sp4_h_r_2 sp4_h_l_40 +(12 6) routing sp4_v_b_5 sp4_h_l_40 +(12 6) routing sp4_v_t_40 sp4_h_l_40 +(12 6) routing sp4_v_t_46 sp4_h_l_40 +(12 7) routing sp4_h_l_40 sp4_v_t_40 +(12 7) routing sp4_h_r_11 sp4_v_t_40 +(12 7) routing sp4_h_r_5 sp4_v_t_40 +(12 7) routing sp4_v_b_2 sp4_v_t_40 +(12 8) routing sp4_v_b_2 sp4_h_r_8 +(12 8) routing sp4_v_b_8 sp4_h_r_8 +(12 8) routing sp4_v_t_45 sp4_h_r_8 +(12 9) routing sp4_h_l_39 sp4_v_b_8 +(12 9) routing sp4_h_l_45 sp4_v_b_8 +(12 9) routing sp4_h_r_8 sp4_v_b_8 +(12 9) routing sp4_v_t_40 sp4_v_b_8 +(13 0) routing sp4_h_l_39 sp4_v_b_2 +(13 0) routing sp4_h_l_45 sp4_v_b_2 +(13 0) routing sp4_v_t_39 sp4_v_b_2 +(13 0) routing sp4_v_t_43 sp4_v_b_2 +(13 1) routing sp4_h_l_43 sp4_h_r_2 +(13 1) routing sp4_h_l_46 sp4_h_r_2 +(13 1) routing sp4_v_b_8 sp4_h_r_2 +(13 1) routing sp4_v_t_44 sp4_h_r_2 +(13 10) routing sp4_h_r_2 sp4_v_t_45 +(13 10) routing sp4_h_r_8 sp4_v_t_45 +(13 10) routing sp4_v_b_0 sp4_v_t_45 +(13 10) routing sp4_v_b_8 sp4_v_t_45 +(13 11) routing sp4_h_r_0 sp4_h_l_45 +(13 11) routing sp4_v_b_3 sp4_h_l_45 +(13 11) routing sp4_v_t_39 sp4_h_l_45 +(13 12) routing sp4_h_l_40 sp4_v_b_11 +(13 12) routing sp4_h_l_46 sp4_v_b_11 +(13 12) routing sp4_v_t_38 sp4_v_b_11 +(13 12) routing sp4_v_t_46 sp4_v_b_11 +(13 13) routing sp4_h_l_45 sp4_h_r_11 +(13 13) routing sp4_v_b_5 sp4_h_r_11 +(13 13) routing sp4_v_t_43 sp4_h_r_11 +(13 14) routing sp4_h_r_11 sp4_v_t_46 +(13 14) routing sp4_h_r_5 sp4_v_t_46 +(13 14) routing sp4_v_b_11 sp4_v_t_46 +(13 14) routing sp4_v_b_3 sp4_v_t_46 +(13 15) routing sp4_h_r_8 sp4_h_l_46 +(13 15) routing sp4_v_b_6 sp4_h_l_46 +(13 15) routing sp4_v_t_40 sp4_h_l_46 +(13 2) routing sp4_h_r_2 sp4_v_t_39 +(13 2) routing sp4_h_r_8 sp4_v_t_39 +(13 2) routing sp4_v_b_2 sp4_v_t_39 +(13 2) routing sp4_v_b_6 sp4_v_t_39 +(13 3) routing sp4_h_r_6 sp4_h_l_39 +(13 3) routing sp4_v_b_9 sp4_h_l_39 +(13 3) routing sp4_v_t_45 sp4_h_l_39 +(13 4) routing sp4_h_l_40 sp4_v_b_5 +(13 4) routing sp4_h_l_46 sp4_v_b_5 +(13 4) routing sp4_v_t_40 sp4_v_b_5 +(13 4) routing sp4_v_t_44 sp4_v_b_5 +(13 5) routing sp4_h_l_39 sp4_h_r_5 +(13 5) routing sp4_h_l_44 sp4_h_r_5 +(13 5) routing sp4_v_b_11 sp4_h_r_5 +(13 5) routing sp4_v_t_37 sp4_h_r_5 +(13 6) routing sp4_h_r_11 sp4_v_t_40 +(13 6) routing sp4_h_r_5 sp4_v_t_40 +(13 6) routing sp4_v_b_5 sp4_v_t_40 +(13 6) routing sp4_v_b_9 sp4_v_t_40 +(13 7) routing sp4_h_r_2 sp4_h_l_40 +(13 7) routing sp4_h_r_9 sp4_h_l_40 +(13 7) routing sp4_v_b_0 sp4_h_l_40 +(13 7) routing sp4_v_t_46 sp4_h_l_40 +(13 8) routing sp4_h_l_39 sp4_v_b_8 +(13 8) routing sp4_h_l_45 sp4_v_b_8 +(13 8) routing sp4_v_t_37 sp4_v_b_8 +(13 8) routing sp4_v_t_45 sp4_v_b_8 +(13 9) routing sp4_h_l_37 sp4_h_r_8 +(13 9) routing sp4_v_b_2 sp4_h_r_8 +(13 9) routing sp4_v_t_38 sp4_h_r_8 +(14 0) routing bnr_op_0 lc_trk_g0_0 +(14 0) routing lft_op_0 lc_trk_g0_0 +(14 0) routing sp12_h_r_0 lc_trk_g0_0 +(14 0) routing sp4_h_l_5 lc_trk_g0_0 +(14 0) routing sp4_h_r_8 lc_trk_g0_0 +(14 0) routing sp4_v_b_0 lc_trk_g0_0 +(14 0) routing sp4_v_b_8 lc_trk_g0_0 +(14 1) routing bnr_op_0 lc_trk_g0_0 +(14 1) routing sp12_h_l_15 lc_trk_g0_0 +(14 1) routing sp12_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_h_l_5 lc_trk_g0_0 +(14 1) routing sp4_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 +(14 1) routing sp4_v_b_8 lc_trk_g0_0 +(14 10) routing bnl_op_4 lc_trk_g2_4 +(14 10) routing rgt_op_4 lc_trk_g2_4 +(14 10) routing sp12_v_b_4 lc_trk_g2_4 +(14 10) routing sp4_h_l_33 lc_trk_g2_4 +(14 10) routing sp4_h_r_36 lc_trk_g2_4 +(14 10) routing sp4_v_b_28 lc_trk_g2_4 +(14 10) routing sp4_v_b_36 lc_trk_g2_4 +(14 11) routing bnl_op_4 lc_trk_g2_4 +(14 11) routing sp12_v_b_20 lc_trk_g2_4 +(14 11) routing sp12_v_b_4 lc_trk_g2_4 +(14 11) routing sp4_h_l_17 lc_trk_g2_4 +(14 11) routing sp4_h_l_33 lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 +(14 11) routing sp4_v_b_36 lc_trk_g2_4 +(14 11) routing tnl_op_4 lc_trk_g2_4 +(14 12) routing bnl_op_0 lc_trk_g3_0 +(14 12) routing rgt_op_0 lc_trk_g3_0 +(14 12) routing sp12_v_b_0 lc_trk_g3_0 +(14 12) routing sp4_h_l_29 lc_trk_g3_0 +(14 12) routing sp4_h_r_32 lc_trk_g3_0 +(14 12) routing sp4_v_b_24 lc_trk_g3_0 +(14 12) routing sp4_v_t_21 lc_trk_g3_0 +(14 13) routing bnl_op_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_0 lc_trk_g3_0 +(14 13) routing sp12_v_t_15 lc_trk_g3_0 +(14 13) routing sp4_h_l_13 lc_trk_g3_0 +(14 13) routing sp4_h_l_29 lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 +(14 13) routing sp4_v_t_21 lc_trk_g3_0 +(14 13) routing tnl_op_0 lc_trk_g3_0 +(14 14) routing bnl_op_4 lc_trk_g3_4 +(14 14) routing rgt_op_4 lc_trk_g3_4 +(14 14) routing sp12_v_b_4 lc_trk_g3_4 +(14 14) routing sp4_h_l_33 lc_trk_g3_4 +(14 14) routing sp4_h_r_36 lc_trk_g3_4 +(14 14) routing sp4_v_b_28 lc_trk_g3_4 +(14 14) routing sp4_v_b_36 lc_trk_g3_4 +(14 15) routing bnl_op_4 lc_trk_g3_4 +(14 15) routing sp12_v_b_20 lc_trk_g3_4 +(14 15) routing sp12_v_b_4 lc_trk_g3_4 +(14 15) routing sp4_h_l_17 lc_trk_g3_4 +(14 15) routing sp4_h_l_33 lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 +(14 15) routing sp4_v_b_36 lc_trk_g3_4 +(14 15) routing tnl_op_4 lc_trk_g3_4 +(14 2) routing bnr_op_4 lc_trk_g0_4 +(14 2) routing lft_op_4 lc_trk_g0_4 +(14 2) routing sp12_h_l_3 lc_trk_g0_4 +(14 2) routing sp4_h_r_12 lc_trk_g0_4 +(14 2) routing sp4_h_r_20 lc_trk_g0_4 +(14 2) routing sp4_v_b_4 lc_trk_g0_4 +(14 2) routing sp4_v_t_1 lc_trk_g0_4 +(14 3) routing bnr_op_4 lc_trk_g0_4 +(14 3) routing sp12_h_l_19 lc_trk_g0_4 +(14 3) routing sp12_h_l_3 lc_trk_g0_4 +(14 3) routing sp4_h_r_20 lc_trk_g0_4 +(14 3) routing sp4_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 +(14 3) routing sp4_v_t_1 lc_trk_g0_4 +(14 4) routing bnr_op_0 lc_trk_g1_0 +(14 4) routing lft_op_0 lc_trk_g1_0 +(14 4) routing sp12_h_r_0 lc_trk_g1_0 +(14 4) routing sp4_h_l_5 lc_trk_g1_0 +(14 4) routing sp4_h_r_8 lc_trk_g1_0 +(14 4) routing sp4_v_b_0 lc_trk_g1_0 +(14 4) routing sp4_v_b_8 lc_trk_g1_0 +(14 5) routing bnr_op_0 lc_trk_g1_0 +(14 5) routing sp12_h_l_15 lc_trk_g1_0 +(14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_l_5 lc_trk_g1_0 +(14 5) routing sp4_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 +(14 5) routing sp4_v_b_8 lc_trk_g1_0 +(14 6) routing bnr_op_4 lc_trk_g1_4 +(14 6) routing lft_op_4 lc_trk_g1_4 +(14 6) routing sp12_h_l_3 lc_trk_g1_4 +(14 6) routing sp4_h_r_12 lc_trk_g1_4 +(14 6) routing sp4_h_r_20 lc_trk_g1_4 +(14 6) routing sp4_v_b_4 lc_trk_g1_4 +(14 6) routing sp4_v_t_1 lc_trk_g1_4 +(14 7) routing bnr_op_4 lc_trk_g1_4 +(14 7) routing sp12_h_l_19 lc_trk_g1_4 +(14 7) routing sp12_h_l_3 lc_trk_g1_4 +(14 7) routing sp4_h_r_20 lc_trk_g1_4 +(14 7) routing sp4_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 +(14 7) routing sp4_v_t_1 lc_trk_g1_4 +(14 8) routing bnl_op_0 lc_trk_g2_0 +(14 8) routing rgt_op_0 lc_trk_g2_0 +(14 8) routing sp12_v_b_0 lc_trk_g2_0 +(14 8) routing sp4_h_l_29 lc_trk_g2_0 +(14 8) routing sp4_h_r_32 lc_trk_g2_0 +(14 8) routing sp4_v_b_24 lc_trk_g2_0 +(14 8) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing bnl_op_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_0 lc_trk_g2_0 +(14 9) routing sp12_v_t_15 lc_trk_g2_0 +(14 9) routing sp4_h_l_13 lc_trk_g2_0 +(14 9) routing sp4_h_l_29 lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 +(14 9) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing tnl_op_0 lc_trk_g2_0 +(15 0) routing lft_op_1 lc_trk_g0_1 +(15 0) routing sp12_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_17 lc_trk_g0_1 +(15 0) routing sp4_h_r_9 lc_trk_g0_1 +(15 0) routing sp4_v_t_4 lc_trk_g0_1 +(15 1) routing lft_op_0 lc_trk_g0_0 +(15 1) routing sp12_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_l_5 lc_trk_g0_0 +(15 1) routing sp4_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_8 lc_trk_g0_0 +(15 1) routing sp4_v_b_16 lc_trk_g0_0 +(15 10) routing rgt_op_5 lc_trk_g2_5 +(15 10) routing sp12_v_b_5 lc_trk_g2_5 +(15 10) routing sp4_h_l_24 lc_trk_g2_5 +(15 10) routing sp4_h_l_32 lc_trk_g2_5 +(15 10) routing sp4_h_r_29 lc_trk_g2_5 +(15 10) routing sp4_v_b_45 lc_trk_g2_5 +(15 10) routing tnl_op_5 lc_trk_g2_5 +(15 10) routing tnr_op_5 lc_trk_g2_5 +(15 11) routing rgt_op_4 lc_trk_g2_4 +(15 11) routing sp12_v_b_4 lc_trk_g2_4 +(15 11) routing sp4_h_l_17 lc_trk_g2_4 +(15 11) routing sp4_h_l_33 lc_trk_g2_4 +(15 11) routing sp4_h_r_36 lc_trk_g2_4 +(15 11) routing sp4_v_b_44 lc_trk_g2_4 +(15 11) routing tnl_op_4 lc_trk_g2_4 +(15 11) routing tnr_op_4 lc_trk_g2_4 +(15 12) routing rgt_op_1 lc_trk_g3_1 +(15 12) routing sp12_v_b_1 lc_trk_g3_1 +(15 12) routing sp4_h_l_20 lc_trk_g3_1 +(15 12) routing sp4_h_r_25 lc_trk_g3_1 +(15 12) routing sp4_h_r_41 lc_trk_g3_1 +(15 12) routing sp4_v_t_28 lc_trk_g3_1 +(15 12) routing tnl_op_1 lc_trk_g3_1 +(15 12) routing tnr_op_1 lc_trk_g3_1 +(15 13) routing rgt_op_0 lc_trk_g3_0 +(15 13) routing sp12_v_b_0 lc_trk_g3_0 +(15 13) routing sp4_h_l_13 lc_trk_g3_0 +(15 13) routing sp4_h_l_29 lc_trk_g3_0 +(15 13) routing sp4_h_r_32 lc_trk_g3_0 +(15 13) routing sp4_v_t_29 lc_trk_g3_0 +(15 13) routing tnl_op_0 lc_trk_g3_0 +(15 13) routing tnr_op_0 lc_trk_g3_0 +(15 14) routing rgt_op_5 lc_trk_g3_5 +(15 14) routing sp12_v_b_5 lc_trk_g3_5 +(15 14) routing sp4_h_l_24 lc_trk_g3_5 +(15 14) routing sp4_h_l_32 lc_trk_g3_5 +(15 14) routing sp4_h_r_29 lc_trk_g3_5 +(15 14) routing sp4_v_b_45 lc_trk_g3_5 +(15 14) routing tnl_op_5 lc_trk_g3_5 +(15 14) routing tnr_op_5 lc_trk_g3_5 +(15 15) routing rgt_op_4 lc_trk_g3_4 +(15 15) routing sp12_v_b_4 lc_trk_g3_4 +(15 15) routing sp4_h_l_17 lc_trk_g3_4 +(15 15) routing sp4_h_l_33 lc_trk_g3_4 +(15 15) routing sp4_h_r_36 lc_trk_g3_4 +(15 15) routing sp4_v_b_44 lc_trk_g3_4 +(15 15) routing tnl_op_4 lc_trk_g3_4 +(15 15) routing tnr_op_4 lc_trk_g3_4 +(15 2) routing lft_op_5 lc_trk_g0_5 +(15 2) routing sp12_h_l_2 lc_trk_g0_5 +(15 2) routing sp4_h_l_0 lc_trk_g0_5 +(15 2) routing sp4_h_l_8 lc_trk_g0_5 +(15 2) routing sp4_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_v_t_8 lc_trk_g0_5 +(15 3) routing lft_op_4 lc_trk_g0_4 +(15 3) routing sp12_h_l_3 lc_trk_g0_4 +(15 3) routing sp4_h_r_12 lc_trk_g0_4 +(15 3) routing sp4_h_r_20 lc_trk_g0_4 +(15 3) routing sp4_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_v_b_20 lc_trk_g0_4 +(15 4) routing lft_op_1 lc_trk_g1_1 +(15 4) routing sp12_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_17 lc_trk_g1_1 +(15 4) routing sp4_h_r_9 lc_trk_g1_1 +(15 4) routing sp4_v_t_4 lc_trk_g1_1 +(15 5) routing lft_op_0 lc_trk_g1_0 +(15 5) routing sp12_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_l_5 lc_trk_g1_0 +(15 5) routing sp4_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_8 lc_trk_g1_0 +(15 5) routing sp4_v_b_16 lc_trk_g1_0 +(15 6) routing lft_op_5 lc_trk_g1_5 +(15 6) routing sp12_h_l_2 lc_trk_g1_5 +(15 6) routing sp4_h_l_0 lc_trk_g1_5 +(15 6) routing sp4_h_l_8 lc_trk_g1_5 +(15 6) routing sp4_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_v_t_8 lc_trk_g1_5 +(15 7) routing lft_op_4 lc_trk_g1_4 +(15 7) routing sp12_h_l_3 lc_trk_g1_4 +(15 7) routing sp4_h_r_12 lc_trk_g1_4 +(15 7) routing sp4_h_r_20 lc_trk_g1_4 +(15 7) routing sp4_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_v_b_20 lc_trk_g1_4 +(15 8) routing rgt_op_1 lc_trk_g2_1 +(15 8) routing sp12_v_b_1 lc_trk_g2_1 +(15 8) routing sp4_h_l_20 lc_trk_g2_1 +(15 8) routing sp4_h_r_25 lc_trk_g2_1 +(15 8) routing sp4_h_r_41 lc_trk_g2_1 +(15 8) routing sp4_v_t_28 lc_trk_g2_1 +(15 8) routing tnl_op_1 lc_trk_g2_1 +(15 8) routing tnr_op_1 lc_trk_g2_1 +(15 9) routing rgt_op_0 lc_trk_g2_0 +(15 9) routing sp12_v_b_0 lc_trk_g2_0 +(15 9) routing sp4_h_l_13 lc_trk_g2_0 +(15 9) routing sp4_h_l_29 lc_trk_g2_0 +(15 9) routing sp4_h_r_32 lc_trk_g2_0 +(15 9) routing sp4_v_t_29 lc_trk_g2_0 +(15 9) routing tnl_op_0 lc_trk_g2_0 +(15 9) routing tnr_op_0 lc_trk_g2_0 +(16 0) routing sp12_h_l_14 lc_trk_g0_1 +(16 0) routing sp12_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_h_r_1 lc_trk_g0_1 +(16 0) routing sp4_h_r_17 lc_trk_g0_1 +(16 0) routing sp4_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_v_b_1 lc_trk_g0_1 +(16 0) routing sp4_v_b_9 lc_trk_g0_1 +(16 0) routing sp4_v_t_4 lc_trk_g0_1 +(16 1) routing sp12_h_l_15 lc_trk_g0_0 +(16 1) routing sp12_h_l_7 lc_trk_g0_0 +(16 1) routing sp4_h_l_5 lc_trk_g0_0 +(16 1) routing sp4_h_r_0 lc_trk_g0_0 +(16 1) routing sp4_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_v_b_0 lc_trk_g0_0 +(16 1) routing sp4_v_b_16 lc_trk_g0_0 +(16 1) routing sp4_v_b_8 lc_trk_g0_0 +(16 10) routing sp12_v_b_21 lc_trk_g2_5 +(16 10) routing sp12_v_t_10 lc_trk_g2_5 +(16 10) routing sp4_h_l_24 lc_trk_g2_5 +(16 10) routing sp4_h_l_32 lc_trk_g2_5 +(16 10) routing sp4_h_r_29 lc_trk_g2_5 +(16 10) routing sp4_v_b_29 lc_trk_g2_5 +(16 10) routing sp4_v_b_45 lc_trk_g2_5 +(16 10) routing sp4_v_t_24 lc_trk_g2_5 +(16 11) routing sp12_v_b_20 lc_trk_g2_4 +(16 11) routing sp12_v_t_11 lc_trk_g2_4 +(16 11) routing sp4_h_l_17 lc_trk_g2_4 +(16 11) routing sp4_h_l_33 lc_trk_g2_4 +(16 11) routing sp4_h_r_36 lc_trk_g2_4 +(16 11) routing sp4_v_b_28 lc_trk_g2_4 +(16 11) routing sp4_v_b_36 lc_trk_g2_4 +(16 11) routing sp4_v_b_44 lc_trk_g2_4 +(16 12) routing sp12_v_b_9 lc_trk_g3_1 +(16 12) routing sp12_v_t_14 lc_trk_g3_1 +(16 12) routing sp4_h_l_20 lc_trk_g3_1 +(16 12) routing sp4_h_r_25 lc_trk_g3_1 +(16 12) routing sp4_h_r_41 lc_trk_g3_1 +(16 12) routing sp4_v_b_25 lc_trk_g3_1 +(16 12) routing sp4_v_b_33 lc_trk_g3_1 +(16 12) routing sp4_v_t_28 lc_trk_g3_1 +(16 13) routing sp12_v_b_8 lc_trk_g3_0 +(16 13) routing sp12_v_t_15 lc_trk_g3_0 +(16 13) routing sp4_h_l_13 lc_trk_g3_0 +(16 13) routing sp4_h_l_29 lc_trk_g3_0 +(16 13) routing sp4_h_r_32 lc_trk_g3_0 +(16 13) routing sp4_v_b_24 lc_trk_g3_0 +(16 13) routing sp4_v_t_21 lc_trk_g3_0 +(16 13) routing sp4_v_t_29 lc_trk_g3_0 +(16 14) routing sp12_v_b_21 lc_trk_g3_5 +(16 14) routing sp12_v_t_10 lc_trk_g3_5 +(16 14) routing sp4_h_l_24 lc_trk_g3_5 +(16 14) routing sp4_h_l_32 lc_trk_g3_5 +(16 14) routing sp4_h_r_29 lc_trk_g3_5 +(16 14) routing sp4_v_b_29 lc_trk_g3_5 +(16 14) routing sp4_v_b_45 lc_trk_g3_5 +(16 14) routing sp4_v_t_24 lc_trk_g3_5 +(16 15) routing sp12_v_b_20 lc_trk_g3_4 +(16 15) routing sp12_v_t_11 lc_trk_g3_4 +(16 15) routing sp4_h_l_17 lc_trk_g3_4 +(16 15) routing sp4_h_l_33 lc_trk_g3_4 +(16 15) routing sp4_h_r_36 lc_trk_g3_4 +(16 15) routing sp4_v_b_28 lc_trk_g3_4 +(16 15) routing sp4_v_b_36 lc_trk_g3_4 +(16 15) routing sp4_v_b_44 lc_trk_g3_4 +(16 2) routing sp12_h_l_10 lc_trk_g0_5 +(16 2) routing sp12_h_r_21 lc_trk_g0_5 +(16 2) routing sp4_h_l_0 lc_trk_g0_5 +(16 2) routing sp4_h_l_8 lc_trk_g0_5 +(16 2) routing sp4_h_r_5 lc_trk_g0_5 +(16 2) routing sp4_v_b_13 lc_trk_g0_5 +(16 2) routing sp4_v_b_5 lc_trk_g0_5 +(16 2) routing sp4_v_t_8 lc_trk_g0_5 +(16 3) routing sp12_h_l_19 lc_trk_g0_4 +(16 3) routing sp12_h_r_12 lc_trk_g0_4 +(16 3) routing sp4_h_r_12 lc_trk_g0_4 +(16 3) routing sp4_h_r_20 lc_trk_g0_4 +(16 3) routing sp4_h_r_4 lc_trk_g0_4 +(16 3) routing sp4_v_b_20 lc_trk_g0_4 +(16 3) routing sp4_v_b_4 lc_trk_g0_4 +(16 3) routing sp4_v_t_1 lc_trk_g0_4 +(16 4) routing sp12_h_l_14 lc_trk_g1_1 +(16 4) routing sp12_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_h_r_1 lc_trk_g1_1 +(16 4) routing sp4_h_r_17 lc_trk_g1_1 +(16 4) routing sp4_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_v_b_1 lc_trk_g1_1 +(16 4) routing sp4_v_b_9 lc_trk_g1_1 +(16 4) routing sp4_v_t_4 lc_trk_g1_1 +(16 5) routing sp12_h_l_15 lc_trk_g1_0 +(16 5) routing sp12_h_l_7 lc_trk_g1_0 +(16 5) routing sp4_h_l_5 lc_trk_g1_0 +(16 5) routing sp4_h_r_0 lc_trk_g1_0 +(16 5) routing sp4_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_v_b_0 lc_trk_g1_0 +(16 5) routing sp4_v_b_16 lc_trk_g1_0 +(16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 6) routing sp12_h_l_10 lc_trk_g1_5 +(16 6) routing sp12_h_r_21 lc_trk_g1_5 +(16 6) routing sp4_h_l_0 lc_trk_g1_5 +(16 6) routing sp4_h_l_8 lc_trk_g1_5 +(16 6) routing sp4_h_r_5 lc_trk_g1_5 +(16 6) routing sp4_v_b_13 lc_trk_g1_5 +(16 6) routing sp4_v_b_5 lc_trk_g1_5 +(16 6) routing sp4_v_t_8 lc_trk_g1_5 +(16 7) routing sp12_h_l_19 lc_trk_g1_4 +(16 7) routing sp12_h_r_12 lc_trk_g1_4 +(16 7) routing sp4_h_r_12 lc_trk_g1_4 +(16 7) routing sp4_h_r_20 lc_trk_g1_4 +(16 7) routing sp4_h_r_4 lc_trk_g1_4 +(16 7) routing sp4_v_b_20 lc_trk_g1_4 +(16 7) routing sp4_v_b_4 lc_trk_g1_4 +(16 7) routing sp4_v_t_1 lc_trk_g1_4 +(16 8) routing sp12_v_b_9 lc_trk_g2_1 +(16 8) routing sp12_v_t_14 lc_trk_g2_1 +(16 8) routing sp4_h_l_20 lc_trk_g2_1 +(16 8) routing sp4_h_r_25 lc_trk_g2_1 +(16 8) routing sp4_h_r_41 lc_trk_g2_1 +(16 8) routing sp4_v_b_25 lc_trk_g2_1 +(16 8) routing sp4_v_b_33 lc_trk_g2_1 +(16 8) routing sp4_v_t_28 lc_trk_g2_1 +(16 9) routing sp12_v_b_8 lc_trk_g2_0 +(16 9) routing sp12_v_t_15 lc_trk_g2_0 +(16 9) routing sp4_h_l_13 lc_trk_g2_0 +(16 9) routing sp4_h_l_29 lc_trk_g2_0 +(16 9) routing sp4_h_r_32 lc_trk_g2_0 +(16 9) routing sp4_v_b_24 lc_trk_g2_0 +(16 9) routing sp4_v_t_21 lc_trk_g2_0 +(16 9) routing sp4_v_t_29 lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_7 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_32 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_15 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_32 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_19 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_7 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_19 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_15 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 lc_trk_g0_1 +(18 0) routing lft_op_1 lc_trk_g0_1 +(18 0) routing sp12_h_r_1 lc_trk_g0_1 +(18 0) routing sp4_h_r_17 lc_trk_g0_1 +(18 0) routing sp4_h_r_9 lc_trk_g0_1 +(18 0) routing sp4_v_b_1 lc_trk_g0_1 +(18 0) routing sp4_v_b_9 lc_trk_g0_1 +(18 1) routing bnr_op_1 lc_trk_g0_1 +(18 1) routing sp12_h_l_14 lc_trk_g0_1 +(18 1) routing sp12_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 +(18 1) routing sp4_v_b_9 lc_trk_g0_1 +(18 10) routing bnl_op_5 lc_trk_g2_5 +(18 10) routing rgt_op_5 lc_trk_g2_5 +(18 10) routing sp12_v_b_5 lc_trk_g2_5 +(18 10) routing sp4_h_l_24 lc_trk_g2_5 +(18 10) routing sp4_h_l_32 lc_trk_g2_5 +(18 10) routing sp4_v_b_29 lc_trk_g2_5 +(18 10) routing sp4_v_t_24 lc_trk_g2_5 +(18 11) routing bnl_op_5 lc_trk_g2_5 +(18 11) routing sp12_v_b_21 lc_trk_g2_5 +(18 11) routing sp12_v_b_5 lc_trk_g2_5 +(18 11) routing sp4_h_l_32 lc_trk_g2_5 +(18 11) routing sp4_h_r_29 lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 +(18 11) routing sp4_v_t_24 lc_trk_g2_5 +(18 11) routing tnl_op_5 lc_trk_g2_5 +(18 12) routing bnl_op_1 lc_trk_g3_1 +(18 12) routing rgt_op_1 lc_trk_g3_1 +(18 12) routing sp12_v_b_1 lc_trk_g3_1 +(18 12) routing sp4_h_l_20 lc_trk_g3_1 +(18 12) routing sp4_h_r_41 lc_trk_g3_1 +(18 12) routing sp4_v_b_25 lc_trk_g3_1 +(18 12) routing sp4_v_b_33 lc_trk_g3_1 +(18 13) routing bnl_op_1 lc_trk_g3_1 +(18 13) routing sp12_v_b_1 lc_trk_g3_1 +(18 13) routing sp12_v_t_14 lc_trk_g3_1 +(18 13) routing sp4_h_r_25 lc_trk_g3_1 +(18 13) routing sp4_h_r_41 lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 +(18 13) routing sp4_v_b_33 lc_trk_g3_1 +(18 13) routing tnl_op_1 lc_trk_g3_1 +(18 14) routing bnl_op_5 lc_trk_g3_5 +(18 14) routing rgt_op_5 lc_trk_g3_5 +(18 14) routing sp12_v_b_5 lc_trk_g3_5 +(18 14) routing sp4_h_l_24 lc_trk_g3_5 +(18 14) routing sp4_h_l_32 lc_trk_g3_5 +(18 14) routing sp4_v_b_29 lc_trk_g3_5 +(18 14) routing sp4_v_t_24 lc_trk_g3_5 +(18 15) routing bnl_op_5 lc_trk_g3_5 +(18 15) routing sp12_v_b_21 lc_trk_g3_5 +(18 15) routing sp12_v_b_5 lc_trk_g3_5 +(18 15) routing sp4_h_l_32 lc_trk_g3_5 +(18 15) routing sp4_h_r_29 lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 +(18 15) routing sp4_v_t_24 lc_trk_g3_5 +(18 15) routing tnl_op_5 lc_trk_g3_5 +(18 2) routing bnr_op_5 lc_trk_g0_5 +(18 2) routing lft_op_5 lc_trk_g0_5 +(18 2) routing sp12_h_l_2 lc_trk_g0_5 +(18 2) routing sp4_h_l_0 lc_trk_g0_5 +(18 2) routing sp4_h_l_8 lc_trk_g0_5 +(18 2) routing sp4_v_b_13 lc_trk_g0_5 +(18 2) routing sp4_v_b_5 lc_trk_g0_5 +(18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_l_2 lc_trk_g0_5 +(18 3) routing sp12_h_r_21 lc_trk_g0_5 +(18 3) routing sp4_h_l_8 lc_trk_g0_5 +(18 3) routing sp4_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 +(18 3) routing sp4_v_b_13 lc_trk_g0_5 +(18 4) routing bnr_op_1 lc_trk_g1_1 +(18 4) routing lft_op_1 lc_trk_g1_1 +(18 4) routing sp12_h_r_1 lc_trk_g1_1 +(18 4) routing sp4_h_r_17 lc_trk_g1_1 +(18 4) routing sp4_h_r_9 lc_trk_g1_1 +(18 4) routing sp4_v_b_1 lc_trk_g1_1 +(18 4) routing sp4_v_b_9 lc_trk_g1_1 +(18 5) routing bnr_op_1 lc_trk_g1_1 +(18 5) routing sp12_h_l_14 lc_trk_g1_1 +(18 5) routing sp12_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_17 lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 +(18 5) routing sp4_v_b_9 lc_trk_g1_1 +(18 6) routing bnr_op_5 lc_trk_g1_5 +(18 6) routing lft_op_5 lc_trk_g1_5 +(18 6) routing sp12_h_l_2 lc_trk_g1_5 +(18 6) routing sp4_h_l_0 lc_trk_g1_5 +(18 6) routing sp4_h_l_8 lc_trk_g1_5 +(18 6) routing sp4_v_b_13 lc_trk_g1_5 +(18 6) routing sp4_v_b_5 lc_trk_g1_5 +(18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_l_2 lc_trk_g1_5 +(18 7) routing sp12_h_r_21 lc_trk_g1_5 +(18 7) routing sp4_h_l_8 lc_trk_g1_5 +(18 7) routing sp4_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 +(18 7) routing sp4_v_b_13 lc_trk_g1_5 +(18 8) routing bnl_op_1 lc_trk_g2_1 +(18 8) routing rgt_op_1 lc_trk_g2_1 +(18 8) routing sp12_v_b_1 lc_trk_g2_1 +(18 8) routing sp4_h_l_20 lc_trk_g2_1 +(18 8) routing sp4_h_r_41 lc_trk_g2_1 +(18 8) routing sp4_v_b_25 lc_trk_g2_1 +(18 8) routing sp4_v_b_33 lc_trk_g2_1 +(18 9) routing bnl_op_1 lc_trk_g2_1 +(18 9) routing sp12_v_b_1 lc_trk_g2_1 +(18 9) routing sp12_v_t_14 lc_trk_g2_1 +(18 9) routing sp4_h_r_25 lc_trk_g2_1 +(18 9) routing sp4_h_r_41 lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 +(18 9) routing sp4_v_b_33 lc_trk_g2_1 +(18 9) routing tnl_op_1 lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_l_7 sp4_h_l_5 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_l_8 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_l_19 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_l_10 +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_r_19 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_r_20 +(21 0) routing bnr_op_3 lc_trk_g0_3 +(21 0) routing lft_op_3 lc_trk_g0_3 +(21 0) routing sp12_h_r_3 lc_trk_g0_3 +(21 0) routing sp4_h_r_11 lc_trk_g0_3 +(21 0) routing sp4_h_r_19 lc_trk_g0_3 +(21 0) routing sp4_v_b_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_3 lc_trk_g0_3 +(21 1) routing bnr_op_3 lc_trk_g0_3 +(21 1) routing sp12_h_l_16 lc_trk_g0_3 +(21 1) routing sp12_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_h_r_19 lc_trk_g0_3 +(21 1) routing sp4_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 +(21 1) routing sp4_v_b_11 lc_trk_g0_3 +(21 10) routing bnl_op_7 lc_trk_g2_7 +(21 10) routing rgt_op_7 lc_trk_g2_7 +(21 10) routing sp12_v_b_7 lc_trk_g2_7 +(21 10) routing sp4_h_r_39 lc_trk_g2_7 +(21 10) routing sp4_h_r_47 lc_trk_g2_7 +(21 10) routing sp4_v_b_39 lc_trk_g2_7 +(21 10) routing sp4_v_t_18 lc_trk_g2_7 +(21 11) routing bnl_op_7 lc_trk_g2_7 +(21 11) routing sp12_v_b_23 lc_trk_g2_7 +(21 11) routing sp12_v_b_7 lc_trk_g2_7 +(21 11) routing sp4_h_l_18 lc_trk_g2_7 +(21 11) routing sp4_h_r_47 lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 +(21 11) routing sp4_v_b_39 lc_trk_g2_7 +(21 11) routing tnl_op_7 lc_trk_g2_7 +(21 12) routing bnl_op_3 lc_trk_g3_3 +(21 12) routing rgt_op_3 lc_trk_g3_3 +(21 12) routing sp12_v_t_0 lc_trk_g3_3 +(21 12) routing sp4_h_l_22 lc_trk_g3_3 +(21 12) routing sp4_h_l_30 lc_trk_g3_3 +(21 12) routing sp4_v_b_27 lc_trk_g3_3 +(21 12) routing sp4_v_t_22 lc_trk_g3_3 +(21 13) routing bnl_op_3 lc_trk_g3_3 +(21 13) routing sp12_v_b_19 lc_trk_g3_3 +(21 13) routing sp12_v_t_0 lc_trk_g3_3 +(21 13) routing sp4_h_l_14 lc_trk_g3_3 +(21 13) routing sp4_h_l_30 lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 +(21 13) routing sp4_v_t_22 lc_trk_g3_3 +(21 13) routing tnl_op_3 lc_trk_g3_3 +(21 14) routing bnl_op_7 lc_trk_g3_7 +(21 14) routing rgt_op_7 lc_trk_g3_7 +(21 14) routing sp12_v_b_7 lc_trk_g3_7 +(21 14) routing sp4_h_r_39 lc_trk_g3_7 +(21 14) routing sp4_h_r_47 lc_trk_g3_7 +(21 14) routing sp4_v_b_39 lc_trk_g3_7 +(21 14) routing sp4_v_t_18 lc_trk_g3_7 +(21 15) routing bnl_op_7 lc_trk_g3_7 +(21 15) routing sp12_v_b_23 lc_trk_g3_7 +(21 15) routing sp12_v_b_7 lc_trk_g3_7 +(21 15) routing sp4_h_l_18 lc_trk_g3_7 +(21 15) routing sp4_h_r_47 lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 +(21 15) routing sp4_v_b_39 lc_trk_g3_7 +(21 15) routing tnl_op_7 lc_trk_g3_7 +(21 2) routing bnr_op_7 lc_trk_g0_7 +(21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_r_7 lc_trk_g0_7 +(21 2) routing sp4_h_l_10 lc_trk_g0_7 +(21 2) routing sp4_h_r_15 lc_trk_g0_7 +(21 2) routing sp4_v_b_7 lc_trk_g0_7 +(21 2) routing sp4_v_t_2 lc_trk_g0_7 +(21 3) routing bnr_op_7 lc_trk_g0_7 +(21 3) routing sp12_h_l_20 lc_trk_g0_7 +(21 3) routing sp12_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_h_l_10 lc_trk_g0_7 +(21 3) routing sp4_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 +(21 3) routing sp4_v_t_2 lc_trk_g0_7 +(21 4) routing bnr_op_3 lc_trk_g1_3 +(21 4) routing lft_op_3 lc_trk_g1_3 +(21 4) routing sp12_h_r_3 lc_trk_g1_3 +(21 4) routing sp4_h_r_11 lc_trk_g1_3 +(21 4) routing sp4_h_r_19 lc_trk_g1_3 +(21 4) routing sp4_v_b_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_3 lc_trk_g1_3 +(21 5) routing bnr_op_3 lc_trk_g1_3 +(21 5) routing sp12_h_l_16 lc_trk_g1_3 +(21 5) routing sp12_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_h_r_19 lc_trk_g1_3 +(21 5) routing sp4_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 +(21 5) routing sp4_v_b_11 lc_trk_g1_3 +(21 6) routing bnr_op_7 lc_trk_g1_7 +(21 6) routing lft_op_7 lc_trk_g1_7 +(21 6) routing sp12_h_r_7 lc_trk_g1_7 +(21 6) routing sp4_h_l_10 lc_trk_g1_7 +(21 6) routing sp4_h_r_15 lc_trk_g1_7 +(21 6) routing sp4_v_b_7 lc_trk_g1_7 +(21 6) routing sp4_v_t_2 lc_trk_g1_7 +(21 7) routing bnr_op_7 lc_trk_g1_7 +(21 7) routing sp12_h_l_20 lc_trk_g1_7 +(21 7) routing sp12_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_h_l_10 lc_trk_g1_7 +(21 7) routing sp4_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 +(21 7) routing sp4_v_t_2 lc_trk_g1_7 +(21 8) routing bnl_op_3 lc_trk_g2_3 +(21 8) routing rgt_op_3 lc_trk_g2_3 +(21 8) routing sp12_v_t_0 lc_trk_g2_3 +(21 8) routing sp4_h_l_22 lc_trk_g2_3 +(21 8) routing sp4_h_l_30 lc_trk_g2_3 +(21 8) routing sp4_v_b_27 lc_trk_g2_3 +(21 8) routing sp4_v_t_22 lc_trk_g2_3 +(21 9) routing bnl_op_3 lc_trk_g2_3 +(21 9) routing sp12_v_b_19 lc_trk_g2_3 +(21 9) routing sp12_v_t_0 lc_trk_g2_3 +(21 9) routing sp4_h_l_14 lc_trk_g2_3 +(21 9) routing sp4_h_l_30 lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 +(21 9) routing sp4_v_t_22 lc_trk_g2_3 +(21 9) routing tnl_op_3 lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_13 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_13 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 lc_trk_g0_3 +(23 0) routing sp12_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_19 lc_trk_g0_3 +(23 0) routing sp4_h_r_3 lc_trk_g0_3 +(23 0) routing sp4_v_b_11 lc_trk_g0_3 +(23 0) routing sp4_v_b_3 lc_trk_g0_3 +(23 0) routing sp4_v_t_6 lc_trk_g0_3 +(23 1) routing sp12_h_l_17 lc_trk_g0_2 +(23 1) routing sp12_h_l_9 lc_trk_g0_2 +(23 1) routing sp4_h_l_7 lc_trk_g0_2 +(23 1) routing sp4_h_r_10 lc_trk_g0_2 +(23 1) routing sp4_h_r_2 lc_trk_g0_2 +(23 1) routing sp4_v_b_10 lc_trk_g0_2 +(23 1) routing sp4_v_b_18 lc_trk_g0_2 +(23 1) routing sp4_v_b_2 lc_trk_g0_2 +(23 10) routing sp12_v_b_23 lc_trk_g2_7 +(23 10) routing sp12_v_t_12 lc_trk_g2_7 +(23 10) routing sp4_h_l_18 lc_trk_g2_7 +(23 10) routing sp4_h_r_39 lc_trk_g2_7 +(23 10) routing sp4_h_r_47 lc_trk_g2_7 +(23 10) routing sp4_v_b_39 lc_trk_g2_7 +(23 10) routing sp4_v_t_18 lc_trk_g2_7 +(23 10) routing sp4_v_t_34 lc_trk_g2_7 +(23 11) routing sp12_v_t_13 lc_trk_g2_6 +(23 11) routing sp12_v_t_21 lc_trk_g2_6 +(23 11) routing sp4_h_l_35 lc_trk_g2_6 +(23 11) routing sp4_h_r_30 lc_trk_g2_6 +(23 11) routing sp4_h_r_38 lc_trk_g2_6 +(23 11) routing sp4_v_b_30 lc_trk_g2_6 +(23 11) routing sp4_v_b_38 lc_trk_g2_6 +(23 11) routing sp4_v_b_46 lc_trk_g2_6 +(23 12) routing sp12_v_b_19 lc_trk_g3_3 +(23 12) routing sp12_v_t_8 lc_trk_g3_3 +(23 12) routing sp4_h_l_14 lc_trk_g3_3 +(23 12) routing sp4_h_l_22 lc_trk_g3_3 +(23 12) routing sp4_h_l_30 lc_trk_g3_3 +(23 12) routing sp4_v_b_27 lc_trk_g3_3 +(23 12) routing sp4_v_b_43 lc_trk_g3_3 +(23 12) routing sp4_v_t_22 lc_trk_g3_3 +(23 13) routing sp12_v_b_10 lc_trk_g3_2 +(23 13) routing sp12_v_t_17 lc_trk_g3_2 +(23 13) routing sp4_h_l_23 lc_trk_g3_2 +(23 13) routing sp4_h_l_31 lc_trk_g3_2 +(23 13) routing sp4_h_r_26 lc_trk_g3_2 +(23 13) routing sp4_v_t_15 lc_trk_g3_2 +(23 13) routing sp4_v_t_23 lc_trk_g3_2 +(23 13) routing sp4_v_t_31 lc_trk_g3_2 +(23 14) routing sp12_v_b_23 lc_trk_g3_7 +(23 14) routing sp12_v_t_12 lc_trk_g3_7 +(23 14) routing sp4_h_l_18 lc_trk_g3_7 +(23 14) routing sp4_h_r_39 lc_trk_g3_7 +(23 14) routing sp4_h_r_47 lc_trk_g3_7 +(23 14) routing sp4_v_b_39 lc_trk_g3_7 +(23 14) routing sp4_v_t_18 lc_trk_g3_7 +(23 14) routing sp4_v_t_34 lc_trk_g3_7 +(23 15) routing sp12_v_t_13 lc_trk_g3_6 +(23 15) routing sp12_v_t_21 lc_trk_g3_6 +(23 15) routing sp4_h_l_35 lc_trk_g3_6 +(23 15) routing sp4_h_r_30 lc_trk_g3_6 +(23 15) routing sp4_h_r_38 lc_trk_g3_6 +(23 15) routing sp4_v_b_30 lc_trk_g3_6 +(23 15) routing sp4_v_b_38 lc_trk_g3_6 +(23 15) routing sp4_v_b_46 lc_trk_g3_6 +(23 2) routing sp12_h_l_12 lc_trk_g0_7 +(23 2) routing sp12_h_l_20 lc_trk_g0_7 +(23 2) routing sp4_h_l_10 lc_trk_g0_7 +(23 2) routing sp4_h_r_15 lc_trk_g0_7 +(23 2) routing sp4_h_r_7 lc_trk_g0_7 +(23 2) routing sp4_v_b_7 lc_trk_g0_7 +(23 2) routing sp4_v_t_10 lc_trk_g0_7 +(23 2) routing sp4_v_t_2 lc_trk_g0_7 +(23 3) routing sp12_h_r_14 lc_trk_g0_6 +(23 3) routing sp12_h_r_22 lc_trk_g0_6 +(23 3) routing sp4_h_l_11 lc_trk_g0_6 +(23 3) routing sp4_h_l_3 lc_trk_g0_6 +(23 3) routing sp4_h_r_6 lc_trk_g0_6 +(23 3) routing sp4_v_b_14 lc_trk_g0_6 +(23 3) routing sp4_v_b_6 lc_trk_g0_6 +(23 3) routing sp4_v_t_11 lc_trk_g0_6 +(23 4) routing sp12_h_l_16 lc_trk_g1_3 +(23 4) routing sp12_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_19 lc_trk_g1_3 +(23 4) routing sp4_h_r_3 lc_trk_g1_3 +(23 4) routing sp4_v_b_11 lc_trk_g1_3 +(23 4) routing sp4_v_b_3 lc_trk_g1_3 +(23 4) routing sp4_v_t_6 lc_trk_g1_3 +(23 5) routing sp12_h_l_17 lc_trk_g1_2 +(23 5) routing sp12_h_l_9 lc_trk_g1_2 +(23 5) routing sp4_h_l_7 lc_trk_g1_2 +(23 5) routing sp4_h_r_10 lc_trk_g1_2 +(23 5) routing sp4_h_r_2 lc_trk_g1_2 +(23 5) routing sp4_v_b_10 lc_trk_g1_2 +(23 5) routing sp4_v_b_18 lc_trk_g1_2 +(23 5) routing sp4_v_b_2 lc_trk_g1_2 +(23 6) routing sp12_h_l_12 lc_trk_g1_7 +(23 6) routing sp12_h_l_20 lc_trk_g1_7 +(23 6) routing sp4_h_l_10 lc_trk_g1_7 +(23 6) routing sp4_h_r_15 lc_trk_g1_7 +(23 6) routing sp4_h_r_7 lc_trk_g1_7 +(23 6) routing sp4_v_b_7 lc_trk_g1_7 +(23 6) routing sp4_v_t_10 lc_trk_g1_7 +(23 6) routing sp4_v_t_2 lc_trk_g1_7 +(23 7) routing sp12_h_r_14 lc_trk_g1_6 +(23 7) routing sp12_h_r_22 lc_trk_g1_6 +(23 7) routing sp4_h_l_11 lc_trk_g1_6 +(23 7) routing sp4_h_l_3 lc_trk_g1_6 +(23 7) routing sp4_h_r_6 lc_trk_g1_6 +(23 7) routing sp4_v_b_14 lc_trk_g1_6 +(23 7) routing sp4_v_b_6 lc_trk_g1_6 +(23 7) routing sp4_v_t_11 lc_trk_g1_6 +(23 8) routing sp12_v_b_19 lc_trk_g2_3 +(23 8) routing sp12_v_t_8 lc_trk_g2_3 +(23 8) routing sp4_h_l_14 lc_trk_g2_3 +(23 8) routing sp4_h_l_22 lc_trk_g2_3 +(23 8) routing sp4_h_l_30 lc_trk_g2_3 +(23 8) routing sp4_v_b_27 lc_trk_g2_3 +(23 8) routing sp4_v_b_43 lc_trk_g2_3 +(23 8) routing sp4_v_t_22 lc_trk_g2_3 +(23 9) routing sp12_v_b_10 lc_trk_g2_2 +(23 9) routing sp12_v_t_17 lc_trk_g2_2 +(23 9) routing sp4_h_l_23 lc_trk_g2_2 +(23 9) routing sp4_h_l_31 lc_trk_g2_2 +(23 9) routing sp4_h_r_26 lc_trk_g2_2 +(23 9) routing sp4_v_t_15 lc_trk_g2_2 +(23 9) routing sp4_v_t_23 lc_trk_g2_2 +(23 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 0) routing lft_op_3 lc_trk_g0_3 +(24 0) routing sp12_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_h_r_11 lc_trk_g0_3 +(24 0) routing sp4_h_r_19 lc_trk_g0_3 +(24 0) routing sp4_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_v_t_6 lc_trk_g0_3 +(24 1) routing lft_op_2 lc_trk_g0_2 +(24 1) routing sp12_h_l_1 lc_trk_g0_2 +(24 1) routing sp4_h_l_7 lc_trk_g0_2 +(24 1) routing sp4_h_r_10 lc_trk_g0_2 +(24 1) routing sp4_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_v_b_18 lc_trk_g0_2 +(24 10) routing rgt_op_7 lc_trk_g2_7 +(24 10) routing sp12_v_b_7 lc_trk_g2_7 +(24 10) routing sp4_h_l_18 lc_trk_g2_7 +(24 10) routing sp4_h_r_39 lc_trk_g2_7 +(24 10) routing sp4_h_r_47 lc_trk_g2_7 +(24 10) routing sp4_v_t_34 lc_trk_g2_7 +(24 10) routing tnl_op_7 lc_trk_g2_7 +(24 10) routing tnr_op_7 lc_trk_g2_7 +(24 11) routing rgt_op_6 lc_trk_g2_6 +(24 11) routing sp12_v_b_6 lc_trk_g2_6 +(24 11) routing sp4_h_l_35 lc_trk_g2_6 +(24 11) routing sp4_h_r_30 lc_trk_g2_6 +(24 11) routing sp4_h_r_38 lc_trk_g2_6 +(24 11) routing sp4_v_b_46 lc_trk_g2_6 +(24 11) routing tnl_op_6 lc_trk_g2_6 +(24 11) routing tnr_op_6 lc_trk_g2_6 +(24 12) routing rgt_op_3 lc_trk_g3_3 +(24 12) routing sp12_v_t_0 lc_trk_g3_3 +(24 12) routing sp4_h_l_14 lc_trk_g3_3 +(24 12) routing sp4_h_l_22 lc_trk_g3_3 +(24 12) routing sp4_h_l_30 lc_trk_g3_3 +(24 12) routing sp4_v_b_43 lc_trk_g3_3 +(24 12) routing tnl_op_3 lc_trk_g3_3 +(24 12) routing tnr_op_3 lc_trk_g3_3 +(24 13) routing rgt_op_2 lc_trk_g3_2 +(24 13) routing sp12_v_b_2 lc_trk_g3_2 +(24 13) routing sp4_h_l_23 lc_trk_g3_2 +(24 13) routing sp4_h_l_31 lc_trk_g3_2 +(24 13) routing sp4_h_r_26 lc_trk_g3_2 +(24 13) routing sp4_v_t_31 lc_trk_g3_2 +(24 13) routing tnl_op_2 lc_trk_g3_2 +(24 13) routing tnr_op_2 lc_trk_g3_2 +(24 14) routing rgt_op_7 lc_trk_g3_7 +(24 14) routing sp12_v_b_7 lc_trk_g3_7 +(24 14) routing sp4_h_l_18 lc_trk_g3_7 +(24 14) routing sp4_h_r_39 lc_trk_g3_7 +(24 14) routing sp4_h_r_47 lc_trk_g3_7 +(24 14) routing sp4_v_t_34 lc_trk_g3_7 +(24 14) routing tnl_op_7 lc_trk_g3_7 +(24 14) routing tnr_op_7 lc_trk_g3_7 +(24 15) routing rgt_op_6 lc_trk_g3_6 +(24 15) routing sp12_v_b_6 lc_trk_g3_6 +(24 15) routing sp4_h_l_35 lc_trk_g3_6 +(24 15) routing sp4_h_r_30 lc_trk_g3_6 +(24 15) routing sp4_h_r_38 lc_trk_g3_6 +(24 15) routing sp4_v_b_46 lc_trk_g3_6 +(24 15) routing tnl_op_6 lc_trk_g3_6 +(24 15) routing tnr_op_6 lc_trk_g3_6 +(24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_h_l_10 lc_trk_g0_7 +(24 2) routing sp4_h_r_15 lc_trk_g0_7 +(24 2) routing sp4_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_v_t_10 lc_trk_g0_7 +(24 3) routing lft_op_6 lc_trk_g0_6 +(24 3) routing sp12_h_l_5 lc_trk_g0_6 +(24 3) routing sp4_h_l_11 lc_trk_g0_6 +(24 3) routing sp4_h_l_3 lc_trk_g0_6 +(24 3) routing sp4_h_r_6 lc_trk_g0_6 +(24 3) routing sp4_v_t_11 lc_trk_g0_6 +(24 4) routing lft_op_3 lc_trk_g1_3 +(24 4) routing sp12_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_h_r_11 lc_trk_g1_3 +(24 4) routing sp4_h_r_19 lc_trk_g1_3 +(24 4) routing sp4_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_v_t_6 lc_trk_g1_3 +(24 5) routing lft_op_2 lc_trk_g1_2 +(24 5) routing sp12_h_l_1 lc_trk_g1_2 +(24 5) routing sp4_h_l_7 lc_trk_g1_2 +(24 5) routing sp4_h_r_10 lc_trk_g1_2 +(24 5) routing sp4_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_v_b_18 lc_trk_g1_2 +(24 6) routing lft_op_7 lc_trk_g1_7 +(24 6) routing sp12_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_h_l_10 lc_trk_g1_7 +(24 6) routing sp4_h_r_15 lc_trk_g1_7 +(24 6) routing sp4_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_v_t_10 lc_trk_g1_7 +(24 7) routing lft_op_6 lc_trk_g1_6 +(24 7) routing sp12_h_l_5 lc_trk_g1_6 +(24 7) routing sp4_h_l_11 lc_trk_g1_6 +(24 7) routing sp4_h_l_3 lc_trk_g1_6 +(24 7) routing sp4_h_r_6 lc_trk_g1_6 +(24 7) routing sp4_v_t_11 lc_trk_g1_6 +(24 8) routing rgt_op_3 lc_trk_g2_3 +(24 8) routing sp12_v_t_0 lc_trk_g2_3 +(24 8) routing sp4_h_l_14 lc_trk_g2_3 +(24 8) routing sp4_h_l_22 lc_trk_g2_3 +(24 8) routing sp4_h_l_30 lc_trk_g2_3 +(24 8) routing sp4_v_b_43 lc_trk_g2_3 +(24 8) routing tnl_op_3 lc_trk_g2_3 +(24 8) routing tnr_op_3 lc_trk_g2_3 +(24 9) routing rgt_op_2 lc_trk_g2_2 +(24 9) routing sp12_v_b_2 lc_trk_g2_2 +(24 9) routing sp4_h_l_23 lc_trk_g2_2 +(24 9) routing sp4_h_l_31 lc_trk_g2_2 +(24 9) routing sp4_h_r_26 lc_trk_g2_2 +(24 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 9) routing tnl_op_2 lc_trk_g2_2 +(24 9) routing tnr_op_2 lc_trk_g2_2 +(25 0) routing bnr_op_2 lc_trk_g0_2 +(25 0) routing lft_op_2 lc_trk_g0_2 +(25 0) routing sp12_h_l_1 lc_trk_g0_2 +(25 0) routing sp4_h_l_7 lc_trk_g0_2 +(25 0) routing sp4_h_r_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_2 lc_trk_g0_2 +(25 1) routing bnr_op_2 lc_trk_g0_2 +(25 1) routing sp12_h_l_1 lc_trk_g0_2 +(25 1) routing sp12_h_l_17 lc_trk_g0_2 +(25 1) routing sp4_h_l_7 lc_trk_g0_2 +(25 1) routing sp4_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 +(25 1) routing sp4_v_b_10 lc_trk_g0_2 +(25 10) routing bnl_op_6 lc_trk_g2_6 +(25 10) routing rgt_op_6 lc_trk_g2_6 +(25 10) routing sp12_v_b_6 lc_trk_g2_6 +(25 10) routing sp4_h_l_35 lc_trk_g2_6 +(25 10) routing sp4_h_r_38 lc_trk_g2_6 +(25 10) routing sp4_v_b_30 lc_trk_g2_6 +(25 10) routing sp4_v_b_38 lc_trk_g2_6 +(25 11) routing bnl_op_6 lc_trk_g2_6 +(25 11) routing sp12_v_b_6 lc_trk_g2_6 +(25 11) routing sp12_v_t_21 lc_trk_g2_6 +(25 11) routing sp4_h_l_35 lc_trk_g2_6 +(25 11) routing sp4_h_r_30 lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 +(25 11) routing sp4_v_b_38 lc_trk_g2_6 +(25 11) routing tnl_op_6 lc_trk_g2_6 +(25 12) routing bnl_op_2 lc_trk_g3_2 +(25 12) routing rgt_op_2 lc_trk_g3_2 +(25 12) routing sp12_v_b_2 lc_trk_g3_2 +(25 12) routing sp4_h_l_23 lc_trk_g3_2 +(25 12) routing sp4_h_l_31 lc_trk_g3_2 +(25 12) routing sp4_v_t_15 lc_trk_g3_2 +(25 12) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing bnl_op_2 lc_trk_g3_2 +(25 13) routing sp12_v_b_2 lc_trk_g3_2 +(25 13) routing sp12_v_t_17 lc_trk_g3_2 +(25 13) routing sp4_h_l_31 lc_trk_g3_2 +(25 13) routing sp4_h_r_26 lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 +(25 13) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing tnl_op_2 lc_trk_g3_2 +(25 14) routing bnl_op_6 lc_trk_g3_6 +(25 14) routing rgt_op_6 lc_trk_g3_6 +(25 14) routing sp12_v_b_6 lc_trk_g3_6 +(25 14) routing sp4_h_l_35 lc_trk_g3_6 +(25 14) routing sp4_h_r_38 lc_trk_g3_6 +(25 14) routing sp4_v_b_30 lc_trk_g3_6 +(25 14) routing sp4_v_b_38 lc_trk_g3_6 +(25 15) routing bnl_op_6 lc_trk_g3_6 +(25 15) routing sp12_v_b_6 lc_trk_g3_6 +(25 15) routing sp12_v_t_21 lc_trk_g3_6 +(25 15) routing sp4_h_l_35 lc_trk_g3_6 +(25 15) routing sp4_h_r_30 lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 +(25 15) routing sp4_v_b_38 lc_trk_g3_6 +(25 15) routing tnl_op_6 lc_trk_g3_6 +(25 2) routing bnr_op_6 lc_trk_g0_6 +(25 2) routing lft_op_6 lc_trk_g0_6 +(25 2) routing sp12_h_l_5 lc_trk_g0_6 +(25 2) routing sp4_h_l_11 lc_trk_g0_6 +(25 2) routing sp4_h_l_3 lc_trk_g0_6 +(25 2) routing sp4_v_b_14 lc_trk_g0_6 +(25 2) routing sp4_v_b_6 lc_trk_g0_6 +(25 3) routing bnr_op_6 lc_trk_g0_6 +(25 3) routing sp12_h_l_5 lc_trk_g0_6 +(25 3) routing sp12_h_r_22 lc_trk_g0_6 +(25 3) routing sp4_h_l_11 lc_trk_g0_6 +(25 3) routing sp4_h_r_6 lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 +(25 3) routing sp4_v_b_14 lc_trk_g0_6 +(25 4) routing bnr_op_2 lc_trk_g1_2 +(25 4) routing lft_op_2 lc_trk_g1_2 +(25 4) routing sp12_h_l_1 lc_trk_g1_2 +(25 4) routing sp4_h_l_7 lc_trk_g1_2 +(25 4) routing sp4_h_r_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_2 lc_trk_g1_2 +(25 5) routing bnr_op_2 lc_trk_g1_2 +(25 5) routing sp12_h_l_1 lc_trk_g1_2 +(25 5) routing sp12_h_l_17 lc_trk_g1_2 +(25 5) routing sp4_h_l_7 lc_trk_g1_2 +(25 5) routing sp4_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 +(25 5) routing sp4_v_b_10 lc_trk_g1_2 +(25 6) routing bnr_op_6 lc_trk_g1_6 +(25 6) routing lft_op_6 lc_trk_g1_6 +(25 6) routing sp12_h_l_5 lc_trk_g1_6 +(25 6) routing sp4_h_l_11 lc_trk_g1_6 +(25 6) routing sp4_h_l_3 lc_trk_g1_6 +(25 6) routing sp4_v_b_14 lc_trk_g1_6 +(25 6) routing sp4_v_b_6 lc_trk_g1_6 +(25 7) routing bnr_op_6 lc_trk_g1_6 +(25 7) routing sp12_h_l_5 lc_trk_g1_6 +(25 7) routing sp12_h_r_22 lc_trk_g1_6 +(25 7) routing sp4_h_l_11 lc_trk_g1_6 +(25 7) routing sp4_h_r_6 lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 +(25 7) routing sp4_v_b_14 lc_trk_g1_6 +(25 8) routing bnl_op_2 lc_trk_g2_2 +(25 8) routing rgt_op_2 lc_trk_g2_2 +(25 8) routing sp12_v_b_2 lc_trk_g2_2 +(25 8) routing sp4_h_l_23 lc_trk_g2_2 +(25 8) routing sp4_h_l_31 lc_trk_g2_2 +(25 8) routing sp4_v_t_15 lc_trk_g2_2 +(25 8) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing bnl_op_2 lc_trk_g2_2 +(25 9) routing sp12_v_b_2 lc_trk_g2_2 +(25 9) routing sp12_v_t_17 lc_trk_g2_2 +(25 9) routing sp4_h_l_31 lc_trk_g2_2 +(25 9) routing sp4_h_r_26 lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 +(25 9) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing tnl_op_2 lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(26 2) routing lc_trk_g0_5 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g0_7 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_4 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_6 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_5 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_7 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_4 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_3 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_7 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_2 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_6 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_3 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_7 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_2 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(26 4) routing lc_trk_g0_4 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g0_6 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_5 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_7 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_4 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_6 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_5 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_2 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_6 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_3 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_7 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_2 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_6 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_3 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(26 6) routing lc_trk_g0_5 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g0_7 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_4 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_6 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_5 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_7 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_4 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_3 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_7 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_2 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_6 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_3 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_7 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_2 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(26 8) routing lc_trk_g0_4 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g0_6 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g1_5 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g1_7 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g2_4 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g2_6 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g3_5 wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g3_7 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g0_2 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g0_6 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g1_3 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g1_7 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g2_2 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g2_6 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g3_3 wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g3_7 wire_mult/lc_4/in_0 +(27 0) routing lc_trk_g1_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(27 3) routing lc_trk_g1_0 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_2 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_4 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_6 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_0 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_2 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_4 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(27 4) routing lc_trk_g1_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(27 5) routing lc_trk_g1_1 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_3 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_5 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_7 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_1 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_3 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_5 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(27 6) routing lc_trk_g1_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(27 7) routing lc_trk_g1_0 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_2 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_4 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_6 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_0 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_2 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_4 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(27 8) routing lc_trk_g1_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(27 9) routing lc_trk_g1_1 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g1_3 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g1_5 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g1_7 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_1 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_3 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_5 wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_7 wire_mult/lc_4/in_0 +(28 0) routing lc_trk_g2_1 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(28 3) routing lc_trk_g2_1 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_3 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_5 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_7 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_0 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_2 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_4 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(28 4) routing lc_trk_g2_1 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(28 5) routing lc_trk_g2_0 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_2 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_4 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_6 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_1 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_3 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_5 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(28 6) routing lc_trk_g2_0 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(28 7) routing lc_trk_g2_1 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_3 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_5 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_7 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_0 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_2 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_4 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(28 8) routing lc_trk_g2_1 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(28 9) routing lc_trk_g2_0 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g2_2 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g2_4 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g2_6 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_1 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_3 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_5 wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_7 wire_mult/lc_4/in_0 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_6 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_6 wire_mult/lc_1/in_0 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_7 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_7 wire_mult/lc_2/in_0 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_6 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_6 wire_mult/lc_3/in_0 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_0 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_2 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_4 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_6 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_1 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_3 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_5 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_7 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_0 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_2 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_4 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_6 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_1 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_3 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_5 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_7 wire_mult/lc_4/in_0 +(3 0) routing sp12_h_r_0 sp12_v_b_0 +(3 0) routing sp12_v_t_23 sp12_v_b_0 +(3 1) routing sp12_h_l_23 sp12_v_b_0 +(3 1) routing sp12_h_r_0 sp12_v_b_0 +(3 10) routing sp12_v_t_22 sp12_h_l_22 +(3 11) routing sp12_v_b_1 sp12_h_l_22 +(3 12) routing sp12_v_b_1 sp12_h_r_1 +(3 12) routing sp12_v_t_22 sp12_h_r_1 +(3 13) routing sp12_h_l_22 sp12_h_r_1 +(3 13) routing sp12_v_b_1 sp12_h_r_1 +(3 14) routing sp12_h_r_1 sp12_v_t_22 +(3 14) routing sp12_v_b_1 sp12_v_t_22 +(3 15) routing sp12_h_l_22 sp12_v_t_22 +(3 15) routing sp12_h_r_1 sp12_v_t_22 +(3 2) routing sp12_h_r_0 sp12_h_l_23 +(3 2) routing sp12_v_t_23 sp12_h_l_23 +(3 3) routing sp12_h_r_0 sp12_h_l_23 +(3 3) routing sp12_v_b_0 sp12_h_l_23 +(3 4) routing sp12_v_b_0 sp12_h_r_0 +(3 4) routing sp12_v_t_23 sp12_h_r_0 +(3 5) routing sp12_h_l_23 sp12_h_r_0 +(3 5) routing sp12_v_b_0 sp12_h_r_0 +(3 6) routing sp12_h_r_0 sp12_v_t_23 +(3 6) routing sp12_v_b_0 sp12_v_t_23 +(3 7) routing sp12_h_l_23 sp12_v_t_23 +(3 7) routing sp12_h_r_0 sp12_v_t_23 +(3 8) routing sp12_h_r_1 sp12_v_b_1 +(3 8) routing sp12_v_t_22 sp12_v_b_1 +(3 9) routing sp12_h_l_22 sp12_v_b_1 +(3 9) routing sp12_h_r_1 sp12_v_b_1 +(30 0) routing lc_trk_g0_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 sp4_v_b_0 +(4 0) routing sp4_h_l_43 sp4_v_b_0 +(4 0) routing sp4_v_t_37 sp4_v_b_0 +(4 0) routing sp4_v_t_41 sp4_v_b_0 +(4 1) routing sp4_h_l_41 sp4_h_r_0 +(4 1) routing sp4_v_b_6 sp4_h_r_0 +(4 1) routing sp4_v_t_42 sp4_h_r_0 +(4 10) routing sp4_h_r_0 sp4_v_t_43 +(4 10) routing sp4_h_r_6 sp4_v_t_43 +(4 10) routing sp4_v_b_10 sp4_v_t_43 +(4 10) routing sp4_v_b_6 sp4_v_t_43 +(4 11) routing sp4_h_r_10 sp4_h_l_43 +(4 11) routing sp4_v_b_1 sp4_h_l_43 +(4 11) routing sp4_v_t_37 sp4_h_l_43 +(4 12) routing sp4_h_l_38 sp4_v_b_9 +(4 12) routing sp4_h_l_44 sp4_v_b_9 +(4 12) routing sp4_v_t_36 sp4_v_b_9 +(4 12) routing sp4_v_t_44 sp4_v_b_9 +(4 13) routing sp4_v_b_3 sp4_h_r_9 +(4 13) routing sp4_v_t_41 sp4_h_r_9 +(4 14) routing sp4_h_r_3 sp4_v_t_44 +(4 14) routing sp4_h_r_9 sp4_v_t_44 +(4 14) routing sp4_v_b_1 sp4_v_t_44 +(4 14) routing sp4_v_b_9 sp4_v_t_44 +(4 15) routing sp4_h_r_6 sp4_h_l_44 +(4 15) routing sp4_v_b_4 sp4_h_l_44 +(4 15) routing sp4_v_t_38 sp4_h_l_44 +(4 2) routing sp4_h_r_0 sp4_v_t_37 +(4 2) routing sp4_h_r_6 sp4_v_t_37 +(4 2) routing sp4_v_b_0 sp4_v_t_37 +(4 2) routing sp4_v_b_4 sp4_v_t_37 +(4 3) routing sp4_h_r_4 sp4_h_l_37 +(4 3) routing sp4_h_r_9 sp4_h_l_37 +(4 3) routing sp4_v_b_7 sp4_h_l_37 +(4 3) routing sp4_v_t_43 sp4_h_l_37 +(4 4) routing sp4_h_l_38 sp4_v_b_3 +(4 4) routing sp4_h_l_44 sp4_v_b_3 +(4 4) routing sp4_v_t_38 sp4_v_b_3 +(4 4) routing sp4_v_t_42 sp4_v_b_3 +(4 5) routing sp4_h_l_37 sp4_h_r_3 +(4 5) routing sp4_h_l_42 sp4_h_r_3 +(4 5) routing sp4_v_b_9 sp4_h_r_3 +(4 5) routing sp4_v_t_47 sp4_h_r_3 +(4 6) routing sp4_h_r_3 sp4_v_t_38 +(4 6) routing sp4_h_r_9 sp4_v_t_38 +(4 6) routing sp4_v_b_3 sp4_v_t_38 +(4 6) routing sp4_v_b_7 sp4_v_t_38 +(4 7) routing sp4_h_r_0 sp4_h_l_38 +(4 7) routing sp4_v_b_10 sp4_h_l_38 +(4 7) routing sp4_v_t_44 sp4_h_l_38 +(4 8) routing sp4_h_l_37 sp4_v_b_6 +(4 8) routing sp4_h_l_43 sp4_v_b_6 +(4 8) routing sp4_v_t_43 sp4_v_b_6 +(4 8) routing sp4_v_t_47 sp4_v_b_6 +(4 9) routing sp4_h_l_38 sp4_h_r_6 +(4 9) routing sp4_h_l_47 sp4_h_r_6 +(4 9) routing sp4_v_b_0 sp4_h_r_6 +(4 9) routing sp4_v_t_36 sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_0 sp4_h_l_5 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_0 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_5 sp4_h_r_26 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_5 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_6 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_6 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_7 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_7 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_1 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_1 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_2 sp4_h_r_20 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_2 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_3 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_3 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_4 sp4_h_l_13 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_4 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_0 sp12_h_l_7 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_0 sp4_h_r_32 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_5 sp12_h_l_1 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_5 sp4_h_l_31 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_6 sp12_h_l_3 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_6 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_7 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_7 sp4_h_l_35 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_1 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_1 sp4_h_l_23 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_2 sp12_h_r_12 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_2 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_3 sp12_h_r_14 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_3 sp4_h_r_38 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_4 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_4 sp4_h_l_29 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_0 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_0 sp4_v_b_16 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_5 sp12_h_l_17 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_5 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_6 sp12_h_l_19 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_6 sp4_v_t_1 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_7 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_7 sp4_v_b_14 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_1 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_1 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_2 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_2 sp4_v_b_20 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_3 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_3 sp4_v_t_11 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_4 sp12_h_l_15 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_4 sp4_v_b_8 +(5 0) routing sp4_v_b_0 sp4_h_r_0 +(5 0) routing sp4_v_b_6 sp4_h_r_0 +(5 0) routing sp4_v_t_37 sp4_h_r_0 +(5 1) routing sp4_h_l_37 sp4_v_b_0 +(5 1) routing sp4_h_l_43 sp4_v_b_0 +(5 1) routing sp4_h_r_0 sp4_v_b_0 +(5 1) routing sp4_v_t_44 sp4_v_b_0 +(5 10) routing sp4_v_b_6 sp4_h_l_43 +(5 10) routing sp4_v_t_37 sp4_h_l_43 +(5 10) routing sp4_v_t_43 sp4_h_l_43 +(5 11) routing sp4_h_l_43 sp4_v_t_43 +(5 11) routing sp4_h_r_0 sp4_v_t_43 +(5 11) routing sp4_h_r_6 sp4_v_t_43 +(5 11) routing sp4_v_b_3 sp4_v_t_43 +(5 12) routing sp4_v_b_3 sp4_h_r_9 +(5 12) routing sp4_v_b_9 sp4_h_r_9 +(5 12) routing sp4_v_t_44 sp4_h_r_9 +(5 13) routing sp4_h_l_38 sp4_v_b_9 +(5 13) routing sp4_h_l_44 sp4_v_b_9 +(5 13) routing sp4_h_r_9 sp4_v_b_9 +(5 13) routing sp4_v_t_43 sp4_v_b_9 +(5 14) routing sp4_h_r_6 sp4_h_l_44 +(5 14) routing sp4_v_b_9 sp4_h_l_44 +(5 14) routing sp4_v_t_38 sp4_h_l_44 +(5 14) routing sp4_v_t_44 sp4_h_l_44 +(5 15) routing sp4_h_l_44 sp4_v_t_44 +(5 15) routing sp4_h_r_3 sp4_v_t_44 +(5 15) routing sp4_h_r_9 sp4_v_t_44 +(5 15) routing sp4_v_b_6 sp4_v_t_44 +(5 2) routing sp4_h_r_9 sp4_h_l_37 +(5 2) routing sp4_v_b_0 sp4_h_l_37 +(5 2) routing sp4_v_t_37 sp4_h_l_37 +(5 2) routing sp4_v_t_43 sp4_h_l_37 +(5 3) routing sp4_h_l_37 sp4_v_t_37 +(5 3) routing sp4_h_r_0 sp4_v_t_37 +(5 3) routing sp4_h_r_6 sp4_v_t_37 +(5 3) routing sp4_v_b_9 sp4_v_t_37 +(5 4) routing sp4_h_l_37 sp4_h_r_3 +(5 4) routing sp4_v_b_3 sp4_h_r_3 +(5 4) routing sp4_v_b_9 sp4_h_r_3 +(5 4) routing sp4_v_t_38 sp4_h_r_3 +(5 5) routing sp4_h_l_38 sp4_v_b_3 +(5 5) routing sp4_h_l_44 sp4_v_b_3 +(5 5) routing sp4_h_r_3 sp4_v_b_3 +(5 5) routing sp4_v_t_37 sp4_v_b_3 +(5 6) routing sp4_h_r_0 sp4_h_l_38 +(5 6) routing sp4_v_b_3 sp4_h_l_38 +(5 6) routing sp4_v_t_38 sp4_h_l_38 +(5 6) routing sp4_v_t_44 sp4_h_l_38 +(5 7) routing sp4_h_l_38 sp4_v_t_38 +(5 7) routing sp4_h_r_3 sp4_v_t_38 +(5 7) routing sp4_h_r_9 sp4_v_t_38 +(5 7) routing sp4_v_b_0 sp4_v_t_38 +(5 8) routing sp4_h_l_38 sp4_h_r_6 +(5 8) routing sp4_v_b_0 sp4_h_r_6 +(5 8) routing sp4_v_b_6 sp4_h_r_6 +(5 8) routing sp4_v_t_43 sp4_h_r_6 +(5 9) routing sp4_h_l_37 sp4_v_b_6 +(5 9) routing sp4_h_l_43 sp4_v_b_6 +(5 9) routing sp4_h_r_6 sp4_v_b_6 +(5 9) routing sp4_v_t_38 sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT0_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT0_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT0_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT0_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT0_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT0_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT0_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT0_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_0 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_0 sp4_v_t_21 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_5 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_5 sp4_v_t_15 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_6 sp4_v_b_44 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_6 sp4_v_b_28 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_7 sp4_v_b_46 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_7 sp4_v_b_30 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_1 sp12_v_b_2 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_1 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_2 sp12_v_b_4 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_2 sp4_v_b_36 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_3 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_3 sp4_v_b_38 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_4 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_4 sp4_v_b_24 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_0 sp12_v_t_15 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_0 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_5 sp12_v_b_10 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_5 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_6 sp12_v_t_11 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_6 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_7 sp12_v_t_13 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_7 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_1 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_1 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_2 sp12_v_b_20 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_2 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_3 sp12_v_t_21 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_3 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_4 sp12_v_b_8 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_4 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_0 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_0 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_5 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_5 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_6 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_6 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_7 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_7 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_1 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_1 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_2 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_2 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_3 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_3 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_4 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_4 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 sp4_v_b_0 +(6 0) routing sp4_h_r_7 sp4_v_b_0 +(6 0) routing sp4_v_t_41 sp4_v_b_0 +(6 0) routing sp4_v_t_44 sp4_v_b_0 +(6 1) routing sp4_h_l_41 sp4_h_r_0 +(6 1) routing sp4_v_b_0 sp4_h_r_0 +(6 1) routing sp4_v_b_6 sp4_h_r_0 +(6 10) routing sp4_h_l_36 sp4_v_t_43 +(6 10) routing sp4_h_r_0 sp4_v_t_43 +(6 10) routing sp4_v_b_10 sp4_v_t_43 +(6 10) routing sp4_v_b_3 sp4_v_t_43 +(6 11) routing sp4_h_r_10 sp4_h_l_43 +(6 11) routing sp4_h_r_6 sp4_h_l_43 +(6 11) routing sp4_v_t_37 sp4_h_l_43 +(6 11) routing sp4_v_t_43 sp4_h_l_43 +(6 12) routing sp4_h_l_38 sp4_v_b_9 +(6 12) routing sp4_h_r_4 sp4_v_b_9 +(6 12) routing sp4_v_t_36 sp4_v_b_9 +(6 12) routing sp4_v_t_43 sp4_v_b_9 +(6 13) routing sp4_h_l_44 sp4_h_r_9 +(6 13) routing sp4_v_b_3 sp4_h_r_9 +(6 13) routing sp4_v_b_9 sp4_h_r_9 +(6 14) routing sp4_h_l_41 sp4_v_t_44 +(6 14) routing sp4_h_r_3 sp4_v_t_44 +(6 14) routing sp4_v_b_1 sp4_v_t_44 +(6 14) routing sp4_v_b_6 sp4_v_t_44 +(6 15) routing sp4_v_t_38 sp4_h_l_44 +(6 15) routing sp4_v_t_44 sp4_h_l_44 +(6 2) routing sp4_h_l_42 sp4_v_t_37 +(6 2) routing sp4_h_r_6 sp4_v_t_37 +(6 2) routing sp4_v_b_4 sp4_v_t_37 +(6 2) routing sp4_v_b_9 sp4_v_t_37 +(6 3) routing sp4_h_r_0 sp4_h_l_37 +(6 3) routing sp4_h_r_4 sp4_h_l_37 +(6 3) routing sp4_v_t_37 sp4_h_l_37 +(6 3) routing sp4_v_t_43 sp4_h_l_37 +(6 4) routing sp4_h_l_44 sp4_v_b_3 +(6 4) routing sp4_h_r_10 sp4_v_b_3 +(6 4) routing sp4_v_t_37 sp4_v_b_3 +(6 4) routing sp4_v_t_42 sp4_v_b_3 +(6 5) routing sp4_h_l_38 sp4_h_r_3 +(6 5) routing sp4_h_l_42 sp4_h_r_3 +(6 5) routing sp4_v_b_3 sp4_h_r_3 +(6 5) routing sp4_v_b_9 sp4_h_r_3 +(6 6) routing sp4_h_l_47 sp4_v_t_38 +(6 6) routing sp4_h_r_9 sp4_v_t_38 +(6 6) routing sp4_v_b_0 sp4_v_t_38 +(6 6) routing sp4_v_b_7 sp4_v_t_38 +(6 7) routing sp4_h_r_3 sp4_h_l_38 +(6 7) routing sp4_v_t_38 sp4_h_l_38 +(6 7) routing sp4_v_t_44 sp4_h_l_38 +(6 8) routing sp4_h_l_37 sp4_v_b_6 +(6 8) routing sp4_h_r_1 sp4_v_b_6 +(6 8) routing sp4_v_t_38 sp4_v_b_6 +(6 8) routing sp4_v_t_47 sp4_v_b_6 +(6 9) routing sp4_h_l_47 sp4_h_r_6 +(6 9) routing sp4_v_b_0 sp4_h_r_6 +(6 9) routing sp4_v_b_6 sp4_h_r_6 +(7 0) MAC16 functional bit: MULT0_bram_cbit_1 +(7 1) MAC16 functional bit: MULT0_bram_cbit_0 +(7 10) Column buffer control bit: MULT0_colbuf_cntl_3 +(7 11) Column buffer control bit: MULT0_colbuf_cntl_2 +(7 12) Column buffer control bit: MULT0_colbuf_cntl_5 +(7 13) Column buffer control bit: MULT0_colbuf_cntl_4 +(7 14) Column buffer control bit: MULT0_colbuf_cntl_7 +(7 15) Column buffer control bit: MULT0_colbuf_cntl_6 +(7 2) MAC16 functional bit: MULT0_bram_cbit_3 +(7 3) MAC16 functional bit: MULT0_bram_cbit_2 +(7 4) MAC16 functional bit: MULT0_bram_cbit_5 +(7 5) MAC16 functional bit: MULT0_bram_cbit_4 +(7 6) MAC16 functional bit: MULT0_bram_cbit_7 +(7 7) MAC16 functional bit: MULT0_bram_cbit_6 +(7 8) Column buffer control bit: MULT0_colbuf_cntl_1 +(7 9) Column buffer control bit: MULT0_colbuf_cntl_0 +(8 0) routing sp4_h_l_40 sp4_h_r_1 +(8 0) routing sp4_v_b_1 sp4_h_r_1 +(8 0) routing sp4_v_b_7 sp4_h_r_1 +(8 1) routing sp4_h_l_36 sp4_v_b_1 +(8 1) routing sp4_h_l_42 sp4_v_b_1 +(8 1) routing sp4_h_r_1 sp4_v_b_1 +(8 1) routing sp4_v_t_47 sp4_v_b_1 +(8 10) routing sp4_h_r_11 sp4_h_l_42 +(8 10) routing sp4_v_t_36 sp4_h_l_42 +(8 10) routing sp4_v_t_42 sp4_h_l_42 +(8 11) routing sp4_h_l_42 sp4_v_t_42 +(8 11) routing sp4_h_r_1 sp4_v_t_42 +(8 11) routing sp4_h_r_7 sp4_v_t_42 +(8 11) routing sp4_v_b_4 sp4_v_t_42 +(8 12) routing sp4_h_l_39 sp4_h_r_10 +(8 12) routing sp4_h_l_47 sp4_h_r_10 +(8 12) routing sp4_v_b_10 sp4_h_r_10 +(8 12) routing sp4_v_b_4 sp4_h_r_10 +(8 13) routing sp4_h_l_41 sp4_v_b_10 +(8 13) routing sp4_h_l_47 sp4_v_b_10 +(8 13) routing sp4_h_r_10 sp4_v_b_10 +(8 13) routing sp4_v_t_42 sp4_v_b_10 +(8 14) routing sp4_h_r_2 sp4_h_l_47 +(8 14) routing sp4_v_t_41 sp4_h_l_47 +(8 14) routing sp4_v_t_47 sp4_h_l_47 +(8 15) routing sp4_h_l_47 sp4_v_t_47 +(8 15) routing sp4_h_r_10 sp4_v_t_47 +(8 15) routing sp4_h_r_4 sp4_v_t_47 +(8 15) routing sp4_v_b_7 sp4_v_t_47 +(8 2) routing sp4_h_r_5 sp4_h_l_36 +(8 2) routing sp4_v_t_36 sp4_h_l_36 +(8 2) routing sp4_v_t_42 sp4_h_l_36 +(8 3) routing sp4_h_l_36 sp4_v_t_36 +(8 3) routing sp4_h_r_1 sp4_v_t_36 +(8 3) routing sp4_h_r_7 sp4_v_t_36 +(8 3) routing sp4_v_b_10 sp4_v_t_36 +(8 4) routing sp4_h_l_41 sp4_h_r_4 +(8 4) routing sp4_h_l_45 sp4_h_r_4 +(8 4) routing sp4_v_b_10 sp4_h_r_4 +(8 4) routing sp4_v_b_4 sp4_h_r_4 +(8 5) routing sp4_h_l_41 sp4_v_b_4 +(8 5) routing sp4_h_l_47 sp4_v_b_4 +(8 5) routing sp4_h_r_4 sp4_v_b_4 +(8 5) routing sp4_v_t_36 sp4_v_b_4 +(8 6) routing sp4_h_r_4 sp4_h_l_41 +(8 6) routing sp4_h_r_8 sp4_h_l_41 +(8 6) routing sp4_v_t_41 sp4_h_l_41 +(8 6) routing sp4_v_t_47 sp4_h_l_41 +(8 7) routing sp4_h_l_41 sp4_v_t_41 +(8 7) routing sp4_h_r_10 sp4_v_t_41 +(8 7) routing sp4_h_r_4 sp4_v_t_41 +(8 7) routing sp4_v_b_1 sp4_v_t_41 +(8 8) routing sp4_h_l_42 sp4_h_r_7 +(8 8) routing sp4_h_l_46 sp4_h_r_7 +(8 8) routing sp4_v_b_1 sp4_h_r_7 +(8 8) routing sp4_v_b_7 sp4_h_r_7 +(8 9) routing sp4_h_l_36 sp4_v_b_7 +(8 9) routing sp4_h_l_42 sp4_v_b_7 +(8 9) routing sp4_h_r_7 sp4_v_b_7 +(8 9) routing sp4_v_t_41 sp4_v_b_7 +(9 0) routing sp4_h_l_47 sp4_h_r_1 +(9 0) routing sp4_v_b_1 sp4_h_r_1 +(9 0) routing sp4_v_b_7 sp4_h_r_1 +(9 0) routing sp4_v_t_36 sp4_h_r_1 +(9 1) routing sp4_h_l_36 sp4_v_b_1 +(9 1) routing sp4_h_l_42 sp4_v_b_1 +(9 1) routing sp4_v_t_36 sp4_v_b_1 +(9 1) routing sp4_v_t_40 sp4_v_b_1 +(9 10) routing sp4_h_r_4 sp4_h_l_42 +(9 10) routing sp4_v_b_7 sp4_h_l_42 +(9 10) routing sp4_v_t_36 sp4_h_l_42 +(9 10) routing sp4_v_t_42 sp4_h_l_42 +(9 11) routing sp4_h_r_1 sp4_v_t_42 +(9 11) routing sp4_h_r_7 sp4_v_t_42 +(9 11) routing sp4_v_b_11 sp4_v_t_42 +(9 11) routing sp4_v_b_7 sp4_v_t_42 +(9 12) routing sp4_h_l_42 sp4_h_r_10 +(9 12) routing sp4_v_b_10 sp4_h_r_10 +(9 12) routing sp4_v_b_4 sp4_h_r_10 +(9 12) routing sp4_v_t_47 sp4_h_r_10 +(9 13) routing sp4_h_l_41 sp4_v_b_10 +(9 13) routing sp4_h_l_47 sp4_v_b_10 +(9 13) routing sp4_v_t_39 sp4_v_b_10 +(9 13) routing sp4_v_t_47 sp4_v_b_10 +(9 14) routing sp4_h_r_7 sp4_h_l_47 +(9 14) routing sp4_v_b_10 sp4_h_l_47 +(9 14) routing sp4_v_t_41 sp4_h_l_47 +(9 14) routing sp4_v_t_47 sp4_h_l_47 +(9 15) routing sp4_h_r_10 sp4_v_t_47 +(9 15) routing sp4_h_r_4 sp4_v_t_47 +(9 15) routing sp4_v_b_10 sp4_v_t_47 +(9 15) routing sp4_v_b_2 sp4_v_t_47 +(9 2) routing sp4_h_r_10 sp4_h_l_36 +(9 2) routing sp4_v_b_1 sp4_h_l_36 +(9 2) routing sp4_v_t_36 sp4_h_l_36 +(9 2) routing sp4_v_t_42 sp4_h_l_36 +(9 3) routing sp4_h_r_1 sp4_v_t_36 +(9 3) routing sp4_h_r_7 sp4_v_t_36 +(9 3) routing sp4_v_b_1 sp4_v_t_36 +(9 3) routing sp4_v_b_5 sp4_v_t_36 +(9 4) routing sp4_h_l_36 sp4_h_r_4 +(9 4) routing sp4_v_b_10 sp4_h_r_4 +(9 4) routing sp4_v_b_4 sp4_h_r_4 +(9 4) routing sp4_v_t_41 sp4_h_r_4 +(9 5) routing sp4_h_l_41 sp4_v_b_4 +(9 5) routing sp4_h_l_47 sp4_v_b_4 +(9 5) routing sp4_v_t_41 sp4_v_b_4 +(9 5) routing sp4_v_t_45 sp4_v_b_4 +(9 6) routing sp4_v_b_4 sp4_h_l_41 +(9 6) routing sp4_v_t_41 sp4_h_l_41 +(9 6) routing sp4_v_t_47 sp4_h_l_41 +(9 7) routing sp4_h_r_10 sp4_v_t_41 +(9 7) routing sp4_h_r_4 sp4_v_t_41 +(9 7) routing sp4_v_b_4 sp4_v_t_41 +(9 7) routing sp4_v_b_8 sp4_v_t_41 +(9 8) routing sp4_h_l_41 sp4_h_r_7 +(9 8) routing sp4_v_b_1 sp4_h_r_7 +(9 8) routing sp4_v_b_7 sp4_h_r_7 +(9 8) routing sp4_v_t_42 sp4_h_r_7 +(9 9) routing sp4_h_l_36 sp4_v_b_7 +(9 9) routing sp4_h_l_42 sp4_v_b_7 +(9 9) routing sp4_v_t_42 sp4_v_b_7 +(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/cached_dsp1_5k.txt b/icefuzz/cached_dsp1_5k.txt index e69de29..c844129 100644 --- a/icefuzz/cached_dsp1_5k.txt +++ b/icefuzz/cached_dsp1_5k.txt @@ -0,0 +1,3033 @@ +(0 10) routing glb_netwk_2 glb2local_2 +(0 10) routing glb_netwk_3 glb2local_2 +(0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 +(0 11) routing glb_netwk_3 glb2local_2 +(0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_2 glb2local_3 +(0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 +(0 13) routing glb_netwk_1 glb2local_3 +(0 13) routing glb_netwk_3 glb2local_3 +(0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 +(0 14) routing glb_netwk_4 wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 +(0 7) routing glb_netwk_1 glb2local_0 +(0 7) routing glb_netwk_3 glb2local_0 +(0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_3 glb2local_1 +(0 8) routing glb_netwk_6 glb2local_1 +(0 8) routing glb_netwk_7 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 +(0 9) routing glb_netwk_5 glb2local_1 +(0 9) routing glb_netwk_7 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 glb2local_2 +(1 11) routing glb_netwk_5 glb2local_2 +(1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 +(1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_l_4 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 +(1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 +(1 9) routing glb_netwk_5 glb2local_1 +(1 9) routing glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_7 glb2local_1 +(10 0) routing sp4_h_l_40 sp4_h_r_1 +(10 0) routing sp4_v_b_7 sp4_h_r_1 +(10 0) routing sp4_v_t_45 sp4_h_r_1 +(10 1) routing sp4_h_l_42 sp4_v_b_1 +(10 1) routing sp4_h_r_8 sp4_v_b_1 +(10 1) routing sp4_v_t_40 sp4_v_b_1 +(10 1) routing sp4_v_t_47 sp4_v_b_1 +(10 10) routing sp4_h_r_4 sp4_h_l_42 +(10 10) routing sp4_v_b_2 sp4_h_l_42 +(10 10) routing sp4_v_t_36 sp4_h_l_42 +(10 11) routing sp4_h_l_39 sp4_v_t_42 +(10 11) routing sp4_h_r_1 sp4_v_t_42 +(10 11) routing sp4_v_b_11 sp4_v_t_42 +(10 11) routing sp4_v_b_4 sp4_v_t_42 +(10 12) routing sp4_v_b_4 sp4_h_r_10 +(10 12) routing sp4_v_t_40 sp4_h_r_10 +(10 13) routing sp4_h_l_41 sp4_v_b_10 +(10 13) routing sp4_h_r_5 sp4_v_b_10 +(10 13) routing sp4_v_t_39 sp4_v_b_10 +(10 13) routing sp4_v_t_42 sp4_v_b_10 +(10 14) routing sp4_h_r_2 sp4_h_l_47 +(10 14) routing sp4_v_b_5 sp4_h_l_47 +(10 14) routing sp4_v_t_41 sp4_h_l_47 +(10 15) routing sp4_h_l_40 sp4_v_t_47 +(10 15) routing sp4_h_r_4 sp4_v_t_47 +(10 15) routing sp4_v_b_2 sp4_v_t_47 +(10 15) routing sp4_v_b_7 sp4_v_t_47 +(10 2) routing sp4_h_r_10 sp4_h_l_36 +(10 2) routing sp4_v_b_8 sp4_h_l_36 +(10 2) routing sp4_v_t_42 sp4_h_l_36 +(10 3) routing sp4_h_l_45 sp4_v_t_36 +(10 3) routing sp4_h_r_7 sp4_v_t_36 +(10 3) routing sp4_v_b_10 sp4_v_t_36 +(10 3) routing sp4_v_b_5 sp4_v_t_36 +(10 4) routing sp4_h_l_45 sp4_h_r_4 +(10 4) routing sp4_v_b_10 sp4_h_r_4 +(10 4) routing sp4_v_t_46 sp4_h_r_4 +(10 5) routing sp4_h_l_47 sp4_v_b_4 +(10 5) routing sp4_h_r_11 sp4_v_b_4 +(10 5) routing sp4_v_t_36 sp4_v_b_4 +(10 5) routing sp4_v_t_45 sp4_v_b_4 +(10 6) routing sp4_h_r_8 sp4_h_l_41 +(10 6) routing sp4_v_b_11 sp4_h_l_41 +(10 6) routing sp4_v_t_47 sp4_h_l_41 +(10 7) routing sp4_h_l_46 sp4_v_t_41 +(10 7) routing sp4_h_r_10 sp4_v_t_41 +(10 7) routing sp4_v_b_1 sp4_v_t_41 +(10 7) routing sp4_v_b_8 sp4_v_t_41 +(10 8) routing sp4_h_l_41 sp4_h_r_7 +(10 8) routing sp4_v_b_1 sp4_h_r_7 +(10 8) routing sp4_v_t_39 sp4_h_r_7 +(10 9) routing sp4_h_l_36 sp4_v_b_7 +(10 9) routing sp4_h_r_2 sp4_v_b_7 +(10 9) routing sp4_v_t_41 sp4_v_b_7 +(10 9) routing sp4_v_t_46 sp4_v_b_7 +(11 0) routing sp4_h_l_45 sp4_v_b_2 +(11 0) routing sp4_h_r_9 sp4_v_b_2 +(11 0) routing sp4_v_t_43 sp4_v_b_2 +(11 0) routing sp4_v_t_46 sp4_v_b_2 +(11 1) routing sp4_v_b_2 sp4_h_r_2 +(11 1) routing sp4_v_b_8 sp4_h_r_2 +(11 10) routing sp4_h_l_38 sp4_v_t_45 +(11 10) routing sp4_h_r_2 sp4_v_t_45 +(11 10) routing sp4_v_b_0 sp4_v_t_45 +(11 10) routing sp4_v_b_5 sp4_v_t_45 +(11 11) routing sp4_h_r_0 sp4_h_l_45 +(11 11) routing sp4_h_r_8 sp4_h_l_45 +(11 11) routing sp4_v_t_39 sp4_h_l_45 +(11 11) routing sp4_v_t_45 sp4_h_l_45 +(11 12) routing sp4_h_l_40 sp4_v_b_11 +(11 12) routing sp4_h_r_6 sp4_v_b_11 +(11 12) routing sp4_v_t_38 sp4_v_b_11 +(11 12) routing sp4_v_t_45 sp4_v_b_11 +(11 13) routing sp4_v_b_11 sp4_h_r_11 +(11 13) routing sp4_v_b_5 sp4_h_r_11 +(11 14) routing sp4_h_l_43 sp4_v_t_46 +(11 14) routing sp4_h_r_5 sp4_v_t_46 +(11 14) routing sp4_v_b_3 sp4_v_t_46 +(11 14) routing sp4_v_b_8 sp4_v_t_46 +(11 15) routing sp4_h_r_3 sp4_h_l_46 +(11 15) routing sp4_v_t_40 sp4_h_l_46 +(11 15) routing sp4_v_t_46 sp4_h_l_46 +(11 2) routing sp4_h_l_44 sp4_v_t_39 +(11 2) routing sp4_h_r_8 sp4_v_t_39 +(11 2) routing sp4_v_b_11 sp4_v_t_39 +(11 2) routing sp4_v_b_6 sp4_v_t_39 +(11 3) routing sp4_h_r_2 sp4_h_l_39 +(11 3) routing sp4_h_r_6 sp4_h_l_39 +(11 3) routing sp4_v_t_39 sp4_h_l_39 +(11 3) routing sp4_v_t_45 sp4_h_l_39 +(11 4) routing sp4_h_l_46 sp4_v_b_5 +(11 4) routing sp4_h_r_0 sp4_v_b_5 +(11 4) routing sp4_v_t_39 sp4_v_b_5 +(11 4) routing sp4_v_t_44 sp4_v_b_5 +(11 5) routing sp4_v_b_11 sp4_h_r_5 +(11 5) routing sp4_v_b_5 sp4_h_r_5 +(11 6) routing sp4_h_l_37 sp4_v_t_40 +(11 6) routing sp4_h_r_11 sp4_v_t_40 +(11 6) routing sp4_v_b_2 sp4_v_t_40 +(11 6) routing sp4_v_b_9 sp4_v_t_40 +(11 7) routing sp4_v_t_40 sp4_h_l_40 +(11 7) routing sp4_v_t_46 sp4_h_l_40 +(11 8) routing sp4_h_l_39 sp4_v_b_8 +(11 8) routing sp4_h_r_3 sp4_v_b_8 +(11 8) routing sp4_v_t_37 sp4_v_b_8 +(11 8) routing sp4_v_t_40 sp4_v_b_8 +(11 9) routing sp4_h_l_37 sp4_h_r_8 +(11 9) routing sp4_v_b_2 sp4_h_r_8 +(11 9) routing sp4_v_b_8 sp4_h_r_8 +(12 0) routing sp4_v_b_2 sp4_h_r_2 +(12 0) routing sp4_v_b_8 sp4_h_r_2 +(12 0) routing sp4_v_t_39 sp4_h_r_2 +(12 1) routing sp4_h_l_39 sp4_v_b_2 +(12 1) routing sp4_h_l_45 sp4_v_b_2 +(12 1) routing sp4_h_r_2 sp4_v_b_2 +(12 1) routing sp4_v_t_46 sp4_v_b_2 +(12 10) routing sp4_v_b_8 sp4_h_l_45 +(12 10) routing sp4_v_t_39 sp4_h_l_45 +(12 10) routing sp4_v_t_45 sp4_h_l_45 +(12 11) routing sp4_h_l_45 sp4_v_t_45 +(12 11) routing sp4_h_r_2 sp4_v_t_45 +(12 11) routing sp4_h_r_8 sp4_v_t_45 +(12 11) routing sp4_v_b_5 sp4_v_t_45 +(12 12) routing sp4_v_b_11 sp4_h_r_11 +(12 12) routing sp4_v_b_5 sp4_h_r_11 +(12 12) routing sp4_v_t_46 sp4_h_r_11 +(12 13) routing sp4_h_l_40 sp4_v_b_11 +(12 13) routing sp4_h_l_46 sp4_v_b_11 +(12 13) routing sp4_h_r_11 sp4_v_b_11 +(12 13) routing sp4_v_t_45 sp4_v_b_11 +(12 14) routing sp4_h_r_8 sp4_h_l_46 +(12 14) routing sp4_v_b_11 sp4_h_l_46 +(12 14) routing sp4_v_t_40 sp4_h_l_46 +(12 14) routing sp4_v_t_46 sp4_h_l_46 +(12 15) routing sp4_h_l_46 sp4_v_t_46 +(12 15) routing sp4_h_r_11 sp4_v_t_46 +(12 15) routing sp4_h_r_5 sp4_v_t_46 +(12 15) routing sp4_v_b_8 sp4_v_t_46 +(12 2) routing sp4_h_r_11 sp4_h_l_39 +(12 2) routing sp4_v_b_2 sp4_h_l_39 +(12 2) routing sp4_v_t_39 sp4_h_l_39 +(12 2) routing sp4_v_t_45 sp4_h_l_39 +(12 3) routing sp4_h_l_39 sp4_v_t_39 +(12 3) routing sp4_h_r_2 sp4_v_t_39 +(12 3) routing sp4_h_r_8 sp4_v_t_39 +(12 3) routing sp4_v_b_11 sp4_v_t_39 +(12 4) routing sp4_v_b_11 sp4_h_r_5 +(12 4) routing sp4_v_b_5 sp4_h_r_5 +(12 4) routing sp4_v_t_40 sp4_h_r_5 +(12 5) routing sp4_h_l_40 sp4_v_b_5 +(12 5) routing sp4_h_l_46 sp4_v_b_5 +(12 5) routing sp4_h_r_5 sp4_v_b_5 +(12 5) routing sp4_v_t_39 sp4_v_b_5 +(12 6) routing sp4_h_r_2 sp4_h_l_40 +(12 6) routing sp4_v_b_5 sp4_h_l_40 +(12 6) routing sp4_v_t_40 sp4_h_l_40 +(12 6) routing sp4_v_t_46 sp4_h_l_40 +(12 7) routing sp4_h_l_40 sp4_v_t_40 +(12 7) routing sp4_h_r_11 sp4_v_t_40 +(12 7) routing sp4_h_r_5 sp4_v_t_40 +(12 7) routing sp4_v_b_2 sp4_v_t_40 +(12 8) routing sp4_h_l_40 sp4_h_r_8 +(12 8) routing sp4_v_b_2 sp4_h_r_8 +(12 8) routing sp4_v_b_8 sp4_h_r_8 +(12 8) routing sp4_v_t_45 sp4_h_r_8 +(12 9) routing sp4_h_l_39 sp4_v_b_8 +(12 9) routing sp4_h_l_45 sp4_v_b_8 +(12 9) routing sp4_h_r_8 sp4_v_b_8 +(12 9) routing sp4_v_t_40 sp4_v_b_8 +(13 0) routing sp4_h_l_39 sp4_v_b_2 +(13 0) routing sp4_h_l_45 sp4_v_b_2 +(13 0) routing sp4_v_t_39 sp4_v_b_2 +(13 0) routing sp4_v_t_43 sp4_v_b_2 +(13 1) routing sp4_v_b_8 sp4_h_r_2 +(13 1) routing sp4_v_t_44 sp4_h_r_2 +(13 10) routing sp4_h_r_2 sp4_v_t_45 +(13 10) routing sp4_h_r_8 sp4_v_t_45 +(13 10) routing sp4_v_b_0 sp4_v_t_45 +(13 10) routing sp4_v_b_8 sp4_v_t_45 +(13 11) routing sp4_h_r_0 sp4_h_l_45 +(13 11) routing sp4_v_b_3 sp4_h_l_45 +(13 11) routing sp4_v_t_39 sp4_h_l_45 +(13 12) routing sp4_h_l_40 sp4_v_b_11 +(13 12) routing sp4_h_l_46 sp4_v_b_11 +(13 12) routing sp4_v_t_38 sp4_v_b_11 +(13 12) routing sp4_v_t_46 sp4_v_b_11 +(13 13) routing sp4_v_b_5 sp4_h_r_11 +(13 13) routing sp4_v_t_43 sp4_h_r_11 +(13 14) routing sp4_h_r_11 sp4_v_t_46 +(13 14) routing sp4_h_r_5 sp4_v_t_46 +(13 14) routing sp4_v_b_11 sp4_v_t_46 +(13 14) routing sp4_v_b_3 sp4_v_t_46 +(13 15) routing sp4_h_r_3 sp4_h_l_46 +(13 15) routing sp4_h_r_8 sp4_h_l_46 +(13 15) routing sp4_v_b_6 sp4_h_l_46 +(13 15) routing sp4_v_t_40 sp4_h_l_46 +(13 2) routing sp4_h_r_2 sp4_v_t_39 +(13 2) routing sp4_h_r_8 sp4_v_t_39 +(13 2) routing sp4_v_b_2 sp4_v_t_39 +(13 2) routing sp4_v_b_6 sp4_v_t_39 +(13 3) routing sp4_h_r_11 sp4_h_l_39 +(13 3) routing sp4_h_r_6 sp4_h_l_39 +(13 3) routing sp4_v_b_9 sp4_h_l_39 +(13 3) routing sp4_v_t_45 sp4_h_l_39 +(13 4) routing sp4_h_l_40 sp4_v_b_5 +(13 4) routing sp4_h_l_46 sp4_v_b_5 +(13 4) routing sp4_v_t_40 sp4_v_b_5 +(13 4) routing sp4_v_t_44 sp4_v_b_5 +(13 5) routing sp4_v_b_11 sp4_h_r_5 +(13 5) routing sp4_v_t_37 sp4_h_r_5 +(13 6) routing sp4_h_r_11 sp4_v_t_40 +(13 6) routing sp4_h_r_5 sp4_v_t_40 +(13 6) routing sp4_v_b_5 sp4_v_t_40 +(13 6) routing sp4_v_b_9 sp4_v_t_40 +(13 7) routing sp4_h_r_2 sp4_h_l_40 +(13 7) routing sp4_v_b_0 sp4_h_l_40 +(13 7) routing sp4_v_t_46 sp4_h_l_40 +(13 8) routing sp4_h_l_39 sp4_v_b_8 +(13 8) routing sp4_h_l_45 sp4_v_b_8 +(13 8) routing sp4_v_t_37 sp4_v_b_8 +(13 8) routing sp4_v_t_45 sp4_v_b_8 +(13 9) routing sp4_h_l_37 sp4_h_r_8 +(13 9) routing sp4_h_l_40 sp4_h_r_8 +(13 9) routing sp4_v_b_2 sp4_h_r_8 +(13 9) routing sp4_v_t_38 sp4_h_r_8 +(14 0) routing bnr_op_0 lc_trk_g0_0 +(14 0) routing lft_op_0 lc_trk_g0_0 +(14 0) routing sp12_h_r_0 lc_trk_g0_0 +(14 0) routing sp4_h_r_16 lc_trk_g0_0 +(14 0) routing sp4_h_r_8 lc_trk_g0_0 +(14 0) routing sp4_v_b_0 lc_trk_g0_0 +(14 0) routing sp4_v_b_8 lc_trk_g0_0 +(14 1) routing bnr_op_0 lc_trk_g0_0 +(14 1) routing sp12_h_l_15 lc_trk_g0_0 +(14 1) routing sp12_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_h_r_16 lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 +(14 1) routing sp4_v_b_8 lc_trk_g0_0 +(14 10) routing bnl_op_4 lc_trk_g2_4 +(14 10) routing rgt_op_4 lc_trk_g2_4 +(14 10) routing sp12_v_t_3 lc_trk_g2_4 +(14 10) routing sp4_h_r_36 lc_trk_g2_4 +(14 10) routing sp4_h_r_44 lc_trk_g2_4 +(14 10) routing sp4_v_t_17 lc_trk_g2_4 +(14 10) routing sp4_v_t_25 lc_trk_g2_4 +(14 11) routing bnl_op_4 lc_trk_g2_4 +(14 11) routing sp12_v_t_19 lc_trk_g2_4 +(14 11) routing sp12_v_t_3 lc_trk_g2_4 +(14 11) routing sp4_h_l_17 lc_trk_g2_4 +(14 11) routing sp4_h_r_44 lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 +(14 11) routing sp4_v_t_25 lc_trk_g2_4 +(14 11) routing tnl_op_4 lc_trk_g2_4 +(14 12) routing bnl_op_0 lc_trk_g3_0 +(14 12) routing rgt_op_0 lc_trk_g3_0 +(14 12) routing sp12_v_b_0 lc_trk_g3_0 +(14 12) routing sp4_h_l_21 lc_trk_g3_0 +(14 12) routing sp4_h_r_40 lc_trk_g3_0 +(14 12) routing sp4_v_b_24 lc_trk_g3_0 +(14 12) routing sp4_v_t_21 lc_trk_g3_0 +(14 13) routing bnl_op_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_0 lc_trk_g3_0 +(14 13) routing sp12_v_t_15 lc_trk_g3_0 +(14 13) routing sp4_h_r_24 lc_trk_g3_0 +(14 13) routing sp4_h_r_40 lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 +(14 13) routing sp4_v_t_21 lc_trk_g3_0 +(14 13) routing tnl_op_0 lc_trk_g3_0 +(14 14) routing bnl_op_4 lc_trk_g3_4 +(14 14) routing rgt_op_4 lc_trk_g3_4 +(14 14) routing sp12_v_t_3 lc_trk_g3_4 +(14 14) routing sp4_h_r_36 lc_trk_g3_4 +(14 14) routing sp4_h_r_44 lc_trk_g3_4 +(14 14) routing sp4_v_t_17 lc_trk_g3_4 +(14 14) routing sp4_v_t_25 lc_trk_g3_4 +(14 15) routing bnl_op_4 lc_trk_g3_4 +(14 15) routing sp12_v_t_19 lc_trk_g3_4 +(14 15) routing sp12_v_t_3 lc_trk_g3_4 +(14 15) routing sp4_h_l_17 lc_trk_g3_4 +(14 15) routing sp4_h_r_44 lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 +(14 15) routing sp4_v_t_25 lc_trk_g3_4 +(14 15) routing tnl_op_4 lc_trk_g3_4 +(14 2) routing bnr_op_4 lc_trk_g0_4 +(14 2) routing lft_op_4 lc_trk_g0_4 +(14 2) routing sp12_h_l_3 lc_trk_g0_4 +(14 2) routing sp4_h_l_9 lc_trk_g0_4 +(14 2) routing sp4_h_r_12 lc_trk_g0_4 +(14 2) routing sp4_v_b_12 lc_trk_g0_4 +(14 2) routing sp4_v_b_4 lc_trk_g0_4 +(14 3) routing bnr_op_4 lc_trk_g0_4 +(14 3) routing sp12_h_l_19 lc_trk_g0_4 +(14 3) routing sp12_h_l_3 lc_trk_g0_4 +(14 3) routing sp4_h_l_9 lc_trk_g0_4 +(14 3) routing sp4_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 +(14 3) routing sp4_v_b_12 lc_trk_g0_4 +(14 4) routing bnr_op_0 lc_trk_g1_0 +(14 4) routing lft_op_0 lc_trk_g1_0 +(14 4) routing sp12_h_r_0 lc_trk_g1_0 +(14 4) routing sp4_h_r_16 lc_trk_g1_0 +(14 4) routing sp4_h_r_8 lc_trk_g1_0 +(14 4) routing sp4_v_b_0 lc_trk_g1_0 +(14 4) routing sp4_v_b_8 lc_trk_g1_0 +(14 5) routing bnr_op_0 lc_trk_g1_0 +(14 5) routing sp12_h_l_15 lc_trk_g1_0 +(14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_r_16 lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 +(14 5) routing sp4_v_b_8 lc_trk_g1_0 +(14 6) routing bnr_op_4 lc_trk_g1_4 +(14 6) routing lft_op_4 lc_trk_g1_4 +(14 6) routing sp12_h_l_3 lc_trk_g1_4 +(14 6) routing sp4_h_l_9 lc_trk_g1_4 +(14 6) routing sp4_h_r_12 lc_trk_g1_4 +(14 6) routing sp4_v_b_12 lc_trk_g1_4 +(14 6) routing sp4_v_b_4 lc_trk_g1_4 +(14 7) routing bnr_op_4 lc_trk_g1_4 +(14 7) routing sp12_h_l_19 lc_trk_g1_4 +(14 7) routing sp12_h_l_3 lc_trk_g1_4 +(14 7) routing sp4_h_l_9 lc_trk_g1_4 +(14 7) routing sp4_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 +(14 7) routing sp4_v_b_12 lc_trk_g1_4 +(14 8) routing bnl_op_0 lc_trk_g2_0 +(14 8) routing rgt_op_0 lc_trk_g2_0 +(14 8) routing sp12_v_b_0 lc_trk_g2_0 +(14 8) routing sp4_h_l_21 lc_trk_g2_0 +(14 8) routing sp4_h_r_40 lc_trk_g2_0 +(14 8) routing sp4_v_b_24 lc_trk_g2_0 +(14 8) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing bnl_op_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_0 lc_trk_g2_0 +(14 9) routing sp12_v_t_15 lc_trk_g2_0 +(14 9) routing sp4_h_r_24 lc_trk_g2_0 +(14 9) routing sp4_h_r_40 lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 +(14 9) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing tnl_op_0 lc_trk_g2_0 +(15 0) routing lft_op_1 lc_trk_g0_1 +(15 0) routing sp12_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_l_4 lc_trk_g0_1 +(15 0) routing sp4_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_9 lc_trk_g0_1 +(15 0) routing sp4_v_b_17 lc_trk_g0_1 +(15 1) routing lft_op_0 lc_trk_g0_0 +(15 1) routing sp12_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_16 lc_trk_g0_0 +(15 1) routing sp4_h_r_8 lc_trk_g0_0 +(15 1) routing sp4_v_b_16 lc_trk_g0_0 +(15 10) routing rgt_op_5 lc_trk_g2_5 +(15 10) routing sp12_v_b_5 lc_trk_g2_5 +(15 10) routing sp4_h_l_16 lc_trk_g2_5 +(15 10) routing sp4_h_l_32 lc_trk_g2_5 +(15 10) routing sp4_h_r_37 lc_trk_g2_5 +(15 10) routing sp4_v_b_45 lc_trk_g2_5 +(15 10) routing tnl_op_5 lc_trk_g2_5 +(15 10) routing tnr_op_5 lc_trk_g2_5 +(15 11) routing rgt_op_4 lc_trk_g2_4 +(15 11) routing sp12_v_t_3 lc_trk_g2_4 +(15 11) routing sp4_h_l_17 lc_trk_g2_4 +(15 11) routing sp4_h_r_36 lc_trk_g2_4 +(15 11) routing sp4_h_r_44 lc_trk_g2_4 +(15 11) routing sp4_v_t_33 lc_trk_g2_4 +(15 11) routing tnl_op_4 lc_trk_g2_4 +(15 12) routing rgt_op_1 lc_trk_g3_1 +(15 12) routing sp12_v_b_1 lc_trk_g3_1 +(15 12) routing sp4_h_l_28 lc_trk_g3_1 +(15 12) routing sp4_h_r_25 lc_trk_g3_1 +(15 12) routing sp4_h_r_33 lc_trk_g3_1 +(15 12) routing sp4_v_t_28 lc_trk_g3_1 +(15 12) routing tnl_op_1 lc_trk_g3_1 +(15 12) routing tnr_op_1 lc_trk_g3_1 +(15 13) routing rgt_op_0 lc_trk_g3_0 +(15 13) routing sp12_v_b_0 lc_trk_g3_0 +(15 13) routing sp4_h_l_21 lc_trk_g3_0 +(15 13) routing sp4_h_r_24 lc_trk_g3_0 +(15 13) routing sp4_h_r_40 lc_trk_g3_0 +(15 13) routing sp4_v_t_29 lc_trk_g3_0 +(15 13) routing tnl_op_0 lc_trk_g3_0 +(15 13) routing tnr_op_0 lc_trk_g3_0 +(15 14) routing rgt_op_5 lc_trk_g3_5 +(15 14) routing sp12_v_b_5 lc_trk_g3_5 +(15 14) routing sp4_h_l_16 lc_trk_g3_5 +(15 14) routing sp4_h_l_32 lc_trk_g3_5 +(15 14) routing sp4_h_r_37 lc_trk_g3_5 +(15 14) routing sp4_v_b_45 lc_trk_g3_5 +(15 14) routing tnl_op_5 lc_trk_g3_5 +(15 14) routing tnr_op_5 lc_trk_g3_5 +(15 15) routing rgt_op_4 lc_trk_g3_4 +(15 15) routing sp12_v_t_3 lc_trk_g3_4 +(15 15) routing sp4_h_l_17 lc_trk_g3_4 +(15 15) routing sp4_h_r_36 lc_trk_g3_4 +(15 15) routing sp4_h_r_44 lc_trk_g3_4 +(15 15) routing sp4_v_t_33 lc_trk_g3_4 +(15 15) routing tnl_op_4 lc_trk_g3_4 +(15 15) routing tnr_op_4 lc_trk_g3_4 +(15 2) routing lft_op_5 lc_trk_g0_5 +(15 2) routing sp12_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_h_l_0 lc_trk_g0_5 +(15 2) routing sp4_h_r_21 lc_trk_g0_5 +(15 2) routing sp4_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_v_b_21 lc_trk_g0_5 +(15 3) routing lft_op_4 lc_trk_g0_4 +(15 3) routing sp12_h_l_3 lc_trk_g0_4 +(15 3) routing sp4_h_l_9 lc_trk_g0_4 +(15 3) routing sp4_h_r_12 lc_trk_g0_4 +(15 3) routing sp4_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_v_t_9 lc_trk_g0_4 +(15 4) routing lft_op_1 lc_trk_g1_1 +(15 4) routing sp12_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_l_4 lc_trk_g1_1 +(15 4) routing sp4_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_9 lc_trk_g1_1 +(15 4) routing sp4_v_b_17 lc_trk_g1_1 +(15 5) routing lft_op_0 lc_trk_g1_0 +(15 5) routing sp12_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_16 lc_trk_g1_0 +(15 5) routing sp4_h_r_8 lc_trk_g1_0 +(15 5) routing sp4_v_b_16 lc_trk_g1_0 +(15 6) routing lft_op_5 lc_trk_g1_5 +(15 6) routing sp12_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_h_l_0 lc_trk_g1_5 +(15 6) routing sp4_h_r_21 lc_trk_g1_5 +(15 6) routing sp4_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_v_b_21 lc_trk_g1_5 +(15 7) routing lft_op_4 lc_trk_g1_4 +(15 7) routing sp12_h_l_3 lc_trk_g1_4 +(15 7) routing sp4_h_l_9 lc_trk_g1_4 +(15 7) routing sp4_h_r_12 lc_trk_g1_4 +(15 7) routing sp4_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_v_t_9 lc_trk_g1_4 +(15 8) routing rgt_op_1 lc_trk_g2_1 +(15 8) routing sp12_v_b_1 lc_trk_g2_1 +(15 8) routing sp4_h_l_28 lc_trk_g2_1 +(15 8) routing sp4_h_r_25 lc_trk_g2_1 +(15 8) routing sp4_h_r_33 lc_trk_g2_1 +(15 8) routing sp4_v_t_28 lc_trk_g2_1 +(15 8) routing tnl_op_1 lc_trk_g2_1 +(15 8) routing tnr_op_1 lc_trk_g2_1 +(15 9) routing rgt_op_0 lc_trk_g2_0 +(15 9) routing sp12_v_b_0 lc_trk_g2_0 +(15 9) routing sp4_h_l_21 lc_trk_g2_0 +(15 9) routing sp4_h_r_24 lc_trk_g2_0 +(15 9) routing sp4_h_r_40 lc_trk_g2_0 +(15 9) routing sp4_v_t_29 lc_trk_g2_0 +(15 9) routing tnl_op_0 lc_trk_g2_0 +(15 9) routing tnr_op_0 lc_trk_g2_0 +(16 0) routing sp12_h_r_17 lc_trk_g0_1 +(16 0) routing sp12_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_h_l_4 lc_trk_g0_1 +(16 0) routing sp4_h_r_1 lc_trk_g0_1 +(16 0) routing sp4_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_v_b_1 lc_trk_g0_1 +(16 0) routing sp4_v_b_17 lc_trk_g0_1 +(16 0) routing sp4_v_b_9 lc_trk_g0_1 +(16 1) routing sp12_h_l_15 lc_trk_g0_0 +(16 1) routing sp12_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_h_r_0 lc_trk_g0_0 +(16 1) routing sp4_h_r_16 lc_trk_g0_0 +(16 1) routing sp4_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_v_b_0 lc_trk_g0_0 +(16 1) routing sp4_v_b_16 lc_trk_g0_0 +(16 1) routing sp4_v_b_8 lc_trk_g0_0 +(16 10) routing sp12_v_b_21 lc_trk_g2_5 +(16 10) routing sp12_v_t_10 lc_trk_g2_5 +(16 10) routing sp4_h_l_16 lc_trk_g2_5 +(16 10) routing sp4_h_l_32 lc_trk_g2_5 +(16 10) routing sp4_h_r_37 lc_trk_g2_5 +(16 10) routing sp4_v_b_29 lc_trk_g2_5 +(16 10) routing sp4_v_b_37 lc_trk_g2_5 +(16 10) routing sp4_v_b_45 lc_trk_g2_5 +(16 11) routing sp12_v_b_12 lc_trk_g2_4 +(16 11) routing sp12_v_t_19 lc_trk_g2_4 +(16 11) routing sp4_h_l_17 lc_trk_g2_4 +(16 11) routing sp4_h_r_36 lc_trk_g2_4 +(16 11) routing sp4_h_r_44 lc_trk_g2_4 +(16 11) routing sp4_v_t_17 lc_trk_g2_4 +(16 11) routing sp4_v_t_25 lc_trk_g2_4 +(16 11) routing sp4_v_t_33 lc_trk_g2_4 +(16 12) routing sp12_v_b_9 lc_trk_g3_1 +(16 12) routing sp12_v_t_14 lc_trk_g3_1 +(16 12) routing sp4_h_l_28 lc_trk_g3_1 +(16 12) routing sp4_h_r_25 lc_trk_g3_1 +(16 12) routing sp4_h_r_33 lc_trk_g3_1 +(16 12) routing sp4_v_t_12 lc_trk_g3_1 +(16 12) routing sp4_v_t_20 lc_trk_g3_1 +(16 12) routing sp4_v_t_28 lc_trk_g3_1 +(16 13) routing sp12_v_b_8 lc_trk_g3_0 +(16 13) routing sp12_v_t_15 lc_trk_g3_0 +(16 13) routing sp4_h_l_21 lc_trk_g3_0 +(16 13) routing sp4_h_r_24 lc_trk_g3_0 +(16 13) routing sp4_h_r_40 lc_trk_g3_0 +(16 13) routing sp4_v_b_24 lc_trk_g3_0 +(16 13) routing sp4_v_t_21 lc_trk_g3_0 +(16 13) routing sp4_v_t_29 lc_trk_g3_0 +(16 14) routing sp12_v_b_21 lc_trk_g3_5 +(16 14) routing sp12_v_t_10 lc_trk_g3_5 +(16 14) routing sp4_h_l_16 lc_trk_g3_5 +(16 14) routing sp4_h_l_32 lc_trk_g3_5 +(16 14) routing sp4_h_r_37 lc_trk_g3_5 +(16 14) routing sp4_v_b_29 lc_trk_g3_5 +(16 14) routing sp4_v_b_37 lc_trk_g3_5 +(16 14) routing sp4_v_b_45 lc_trk_g3_5 +(16 15) routing sp12_v_b_12 lc_trk_g3_4 +(16 15) routing sp12_v_t_19 lc_trk_g3_4 +(16 15) routing sp4_h_l_17 lc_trk_g3_4 +(16 15) routing sp4_h_r_36 lc_trk_g3_4 +(16 15) routing sp4_h_r_44 lc_trk_g3_4 +(16 15) routing sp4_v_t_17 lc_trk_g3_4 +(16 15) routing sp4_v_t_25 lc_trk_g3_4 +(16 15) routing sp4_v_t_33 lc_trk_g3_4 +(16 2) routing sp12_h_l_10 lc_trk_g0_5 +(16 2) routing sp12_h_l_18 lc_trk_g0_5 +(16 2) routing sp4_h_l_0 lc_trk_g0_5 +(16 2) routing sp4_h_r_21 lc_trk_g0_5 +(16 2) routing sp4_h_r_5 lc_trk_g0_5 +(16 2) routing sp4_v_b_13 lc_trk_g0_5 +(16 2) routing sp4_v_b_21 lc_trk_g0_5 +(16 2) routing sp4_v_b_5 lc_trk_g0_5 +(16 3) routing sp12_h_l_11 lc_trk_g0_4 +(16 3) routing sp12_h_l_19 lc_trk_g0_4 +(16 3) routing sp4_h_l_9 lc_trk_g0_4 +(16 3) routing sp4_h_r_12 lc_trk_g0_4 +(16 3) routing sp4_h_r_4 lc_trk_g0_4 +(16 3) routing sp4_v_b_12 lc_trk_g0_4 +(16 3) routing sp4_v_b_4 lc_trk_g0_4 +(16 3) routing sp4_v_t_9 lc_trk_g0_4 +(16 4) routing sp12_h_r_17 lc_trk_g1_1 +(16 4) routing sp12_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_h_l_4 lc_trk_g1_1 +(16 4) routing sp4_h_r_1 lc_trk_g1_1 +(16 4) routing sp4_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_v_b_1 lc_trk_g1_1 +(16 4) routing sp4_v_b_17 lc_trk_g1_1 +(16 4) routing sp4_v_b_9 lc_trk_g1_1 +(16 5) routing sp12_h_l_15 lc_trk_g1_0 +(16 5) routing sp12_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_h_r_0 lc_trk_g1_0 +(16 5) routing sp4_h_r_16 lc_trk_g1_0 +(16 5) routing sp4_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_v_b_0 lc_trk_g1_0 +(16 5) routing sp4_v_b_16 lc_trk_g1_0 +(16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 6) routing sp12_h_l_10 lc_trk_g1_5 +(16 6) routing sp12_h_l_18 lc_trk_g1_5 +(16 6) routing sp4_h_l_0 lc_trk_g1_5 +(16 6) routing sp4_h_r_21 lc_trk_g1_5 +(16 6) routing sp4_h_r_5 lc_trk_g1_5 +(16 6) routing sp4_v_b_13 lc_trk_g1_5 +(16 6) routing sp4_v_b_21 lc_trk_g1_5 +(16 6) routing sp4_v_b_5 lc_trk_g1_5 +(16 7) routing sp12_h_l_11 lc_trk_g1_4 +(16 7) routing sp12_h_l_19 lc_trk_g1_4 +(16 7) routing sp4_h_l_9 lc_trk_g1_4 +(16 7) routing sp4_h_r_12 lc_trk_g1_4 +(16 7) routing sp4_h_r_4 lc_trk_g1_4 +(16 7) routing sp4_v_b_12 lc_trk_g1_4 +(16 7) routing sp4_v_b_4 lc_trk_g1_4 +(16 7) routing sp4_v_t_9 lc_trk_g1_4 +(16 8) routing sp12_v_b_9 lc_trk_g2_1 +(16 8) routing sp12_v_t_14 lc_trk_g2_1 +(16 8) routing sp4_h_l_28 lc_trk_g2_1 +(16 8) routing sp4_h_r_25 lc_trk_g2_1 +(16 8) routing sp4_h_r_33 lc_trk_g2_1 +(16 8) routing sp4_v_t_12 lc_trk_g2_1 +(16 8) routing sp4_v_t_20 lc_trk_g2_1 +(16 8) routing sp4_v_t_28 lc_trk_g2_1 +(16 9) routing sp12_v_b_8 lc_trk_g2_0 +(16 9) routing sp12_v_t_15 lc_trk_g2_0 +(16 9) routing sp4_h_l_21 lc_trk_g2_0 +(16 9) routing sp4_h_r_24 lc_trk_g2_0 +(16 9) routing sp4_h_r_40 lc_trk_g2_0 +(16 9) routing sp4_v_b_24 lc_trk_g2_0 +(16 9) routing sp4_v_t_21 lc_trk_g2_0 +(16 9) routing sp4_v_t_29 lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_l_4 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_32 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_15 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_32 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_19 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_9 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_l_4 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_19 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_9 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_15 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 lc_trk_g0_1 +(18 0) routing lft_op_1 lc_trk_g0_1 +(18 0) routing sp12_h_r_1 lc_trk_g0_1 +(18 0) routing sp4_h_l_4 lc_trk_g0_1 +(18 0) routing sp4_h_r_9 lc_trk_g0_1 +(18 0) routing sp4_v_b_1 lc_trk_g0_1 +(18 0) routing sp4_v_b_9 lc_trk_g0_1 +(18 1) routing bnr_op_1 lc_trk_g0_1 +(18 1) routing sp12_h_r_1 lc_trk_g0_1 +(18 1) routing sp12_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_h_l_4 lc_trk_g0_1 +(18 1) routing sp4_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 +(18 1) routing sp4_v_b_9 lc_trk_g0_1 +(18 10) routing bnl_op_5 lc_trk_g2_5 +(18 10) routing rgt_op_5 lc_trk_g2_5 +(18 10) routing sp12_v_b_5 lc_trk_g2_5 +(18 10) routing sp4_h_l_32 lc_trk_g2_5 +(18 10) routing sp4_h_r_37 lc_trk_g2_5 +(18 10) routing sp4_v_b_29 lc_trk_g2_5 +(18 10) routing sp4_v_b_37 lc_trk_g2_5 +(18 11) routing bnl_op_5 lc_trk_g2_5 +(18 11) routing sp12_v_b_21 lc_trk_g2_5 +(18 11) routing sp12_v_b_5 lc_trk_g2_5 +(18 11) routing sp4_h_l_16 lc_trk_g2_5 +(18 11) routing sp4_h_l_32 lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 +(18 11) routing sp4_v_b_37 lc_trk_g2_5 +(18 11) routing tnl_op_5 lc_trk_g2_5 +(18 12) routing bnl_op_1 lc_trk_g3_1 +(18 12) routing rgt_op_1 lc_trk_g3_1 +(18 12) routing sp12_v_b_1 lc_trk_g3_1 +(18 12) routing sp4_h_l_28 lc_trk_g3_1 +(18 12) routing sp4_h_r_33 lc_trk_g3_1 +(18 12) routing sp4_v_t_12 lc_trk_g3_1 +(18 12) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing bnl_op_1 lc_trk_g3_1 +(18 13) routing sp12_v_b_1 lc_trk_g3_1 +(18 13) routing sp12_v_t_14 lc_trk_g3_1 +(18 13) routing sp4_h_l_28 lc_trk_g3_1 +(18 13) routing sp4_h_r_25 lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 +(18 13) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing tnl_op_1 lc_trk_g3_1 +(18 14) routing bnl_op_5 lc_trk_g3_5 +(18 14) routing rgt_op_5 lc_trk_g3_5 +(18 14) routing sp12_v_b_5 lc_trk_g3_5 +(18 14) routing sp4_h_l_32 lc_trk_g3_5 +(18 14) routing sp4_h_r_37 lc_trk_g3_5 +(18 14) routing sp4_v_b_29 lc_trk_g3_5 +(18 14) routing sp4_v_b_37 lc_trk_g3_5 +(18 15) routing bnl_op_5 lc_trk_g3_5 +(18 15) routing sp12_v_b_21 lc_trk_g3_5 +(18 15) routing sp12_v_b_5 lc_trk_g3_5 +(18 15) routing sp4_h_l_16 lc_trk_g3_5 +(18 15) routing sp4_h_l_32 lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 +(18 15) routing sp4_v_b_37 lc_trk_g3_5 +(18 15) routing tnl_op_5 lc_trk_g3_5 +(18 2) routing bnr_op_5 lc_trk_g0_5 +(18 2) routing lft_op_5 lc_trk_g0_5 +(18 2) routing sp12_h_r_5 lc_trk_g0_5 +(18 2) routing sp4_h_l_0 lc_trk_g0_5 +(18 2) routing sp4_h_r_21 lc_trk_g0_5 +(18 2) routing sp4_v_b_13 lc_trk_g0_5 +(18 2) routing sp4_v_b_5 lc_trk_g0_5 +(18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_l_18 lc_trk_g0_5 +(18 3) routing sp12_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_h_r_21 lc_trk_g0_5 +(18 3) routing sp4_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 +(18 3) routing sp4_v_b_13 lc_trk_g0_5 +(18 4) routing bnr_op_1 lc_trk_g1_1 +(18 4) routing lft_op_1 lc_trk_g1_1 +(18 4) routing sp12_h_r_1 lc_trk_g1_1 +(18 4) routing sp4_h_l_4 lc_trk_g1_1 +(18 4) routing sp4_h_r_9 lc_trk_g1_1 +(18 4) routing sp4_v_b_1 lc_trk_g1_1 +(18 4) routing sp4_v_b_9 lc_trk_g1_1 +(18 5) routing bnr_op_1 lc_trk_g1_1 +(18 5) routing sp12_h_r_1 lc_trk_g1_1 +(18 5) routing sp12_h_r_17 lc_trk_g1_1 +(18 5) routing sp4_h_l_4 lc_trk_g1_1 +(18 5) routing sp4_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 +(18 5) routing sp4_v_b_9 lc_trk_g1_1 +(18 6) routing bnr_op_5 lc_trk_g1_5 +(18 6) routing lft_op_5 lc_trk_g1_5 +(18 6) routing sp12_h_r_5 lc_trk_g1_5 +(18 6) routing sp4_h_l_0 lc_trk_g1_5 +(18 6) routing sp4_h_r_21 lc_trk_g1_5 +(18 6) routing sp4_v_b_13 lc_trk_g1_5 +(18 6) routing sp4_v_b_5 lc_trk_g1_5 +(18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_l_18 lc_trk_g1_5 +(18 7) routing sp12_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_h_r_21 lc_trk_g1_5 +(18 7) routing sp4_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 +(18 7) routing sp4_v_b_13 lc_trk_g1_5 +(18 8) routing bnl_op_1 lc_trk_g2_1 +(18 8) routing rgt_op_1 lc_trk_g2_1 +(18 8) routing sp12_v_b_1 lc_trk_g2_1 +(18 8) routing sp4_h_l_28 lc_trk_g2_1 +(18 8) routing sp4_h_r_33 lc_trk_g2_1 +(18 8) routing sp4_v_t_12 lc_trk_g2_1 +(18 8) routing sp4_v_t_20 lc_trk_g2_1 +(18 9) routing bnl_op_1 lc_trk_g2_1 +(18 9) routing sp12_v_b_1 lc_trk_g2_1 +(18 9) routing sp12_v_t_14 lc_trk_g2_1 +(18 9) routing sp4_h_l_28 lc_trk_g2_1 +(18 9) routing sp4_h_r_25 lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 +(18 9) routing sp4_v_t_20 lc_trk_g2_1 +(18 9) routing tnl_op_1 lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_t_3 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_b_15 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_b_21 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_t_9 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_r_21 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_l_19 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_l_10 +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9 +(21 0) routing bnr_op_3 lc_trk_g0_3 +(21 0) routing lft_op_3 lc_trk_g0_3 +(21 0) routing sp12_h_l_0 lc_trk_g0_3 +(21 0) routing sp4_h_r_11 lc_trk_g0_3 +(21 0) routing sp4_h_r_19 lc_trk_g0_3 +(21 0) routing sp4_v_b_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_3 lc_trk_g0_3 +(21 1) routing bnr_op_3 lc_trk_g0_3 +(21 1) routing sp12_h_l_0 lc_trk_g0_3 +(21 1) routing sp12_h_l_16 lc_trk_g0_3 +(21 1) routing sp4_h_r_19 lc_trk_g0_3 +(21 1) routing sp4_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 +(21 1) routing sp4_v_b_11 lc_trk_g0_3 +(21 10) routing bnl_op_7 lc_trk_g2_7 +(21 10) routing rgt_op_7 lc_trk_g2_7 +(21 10) routing sp12_v_t_4 lc_trk_g2_7 +(21 10) routing sp4_h_l_34 lc_trk_g2_7 +(21 10) routing sp4_h_r_39 lc_trk_g2_7 +(21 10) routing sp4_v_b_31 lc_trk_g2_7 +(21 10) routing sp4_v_t_26 lc_trk_g2_7 +(21 11) routing bnl_op_7 lc_trk_g2_7 +(21 11) routing sp12_v_b_23 lc_trk_g2_7 +(21 11) routing sp12_v_t_4 lc_trk_g2_7 +(21 11) routing sp4_h_l_34 lc_trk_g2_7 +(21 11) routing sp4_h_r_31 lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 +(21 11) routing sp4_v_t_26 lc_trk_g2_7 +(21 11) routing tnl_op_7 lc_trk_g2_7 +(21 12) routing bnl_op_3 lc_trk_g3_3 +(21 12) routing rgt_op_3 lc_trk_g3_3 +(21 12) routing sp12_v_b_3 lc_trk_g3_3 +(21 12) routing sp4_h_l_22 lc_trk_g3_3 +(21 12) routing sp4_h_r_43 lc_trk_g3_3 +(21 12) routing sp4_v_b_35 lc_trk_g3_3 +(21 12) routing sp4_v_t_14 lc_trk_g3_3 +(21 13) routing bnl_op_3 lc_trk_g3_3 +(21 13) routing sp12_v_b_19 lc_trk_g3_3 +(21 13) routing sp12_v_b_3 lc_trk_g3_3 +(21 13) routing sp4_h_r_27 lc_trk_g3_3 +(21 13) routing sp4_h_r_43 lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 +(21 13) routing sp4_v_b_35 lc_trk_g3_3 +(21 13) routing tnl_op_3 lc_trk_g3_3 +(21 14) routing bnl_op_7 lc_trk_g3_7 +(21 14) routing rgt_op_7 lc_trk_g3_7 +(21 14) routing sp12_v_t_4 lc_trk_g3_7 +(21 14) routing sp4_h_l_34 lc_trk_g3_7 +(21 14) routing sp4_h_r_39 lc_trk_g3_7 +(21 14) routing sp4_v_b_31 lc_trk_g3_7 +(21 14) routing sp4_v_t_26 lc_trk_g3_7 +(21 15) routing bnl_op_7 lc_trk_g3_7 +(21 15) routing sp12_v_b_23 lc_trk_g3_7 +(21 15) routing sp12_v_t_4 lc_trk_g3_7 +(21 15) routing sp4_h_l_34 lc_trk_g3_7 +(21 15) routing sp4_h_r_31 lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 +(21 15) routing sp4_v_t_26 lc_trk_g3_7 +(21 15) routing tnl_op_7 lc_trk_g3_7 +(21 2) routing bnr_op_7 lc_trk_g0_7 +(21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_l_4 lc_trk_g0_7 +(21 2) routing sp4_h_l_10 lc_trk_g0_7 +(21 2) routing sp4_h_l_2 lc_trk_g0_7 +(21 2) routing sp4_v_b_7 lc_trk_g0_7 +(21 2) routing sp4_v_t_2 lc_trk_g0_7 +(21 3) routing bnr_op_7 lc_trk_g0_7 +(21 3) routing sp12_h_l_20 lc_trk_g0_7 +(21 3) routing sp12_h_l_4 lc_trk_g0_7 +(21 3) routing sp4_h_l_10 lc_trk_g0_7 +(21 3) routing sp4_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 +(21 3) routing sp4_v_t_2 lc_trk_g0_7 +(21 4) routing bnr_op_3 lc_trk_g1_3 +(21 4) routing lft_op_3 lc_trk_g1_3 +(21 4) routing sp12_h_l_0 lc_trk_g1_3 +(21 4) routing sp4_h_r_11 lc_trk_g1_3 +(21 4) routing sp4_h_r_19 lc_trk_g1_3 +(21 4) routing sp4_v_b_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_3 lc_trk_g1_3 +(21 5) routing bnr_op_3 lc_trk_g1_3 +(21 5) routing sp12_h_l_0 lc_trk_g1_3 +(21 5) routing sp12_h_l_16 lc_trk_g1_3 +(21 5) routing sp4_h_r_19 lc_trk_g1_3 +(21 5) routing sp4_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 +(21 5) routing sp4_v_b_11 lc_trk_g1_3 +(21 6) routing bnr_op_7 lc_trk_g1_7 +(21 6) routing lft_op_7 lc_trk_g1_7 +(21 6) routing sp12_h_l_4 lc_trk_g1_7 +(21 6) routing sp4_h_l_10 lc_trk_g1_7 +(21 6) routing sp4_h_l_2 lc_trk_g1_7 +(21 6) routing sp4_v_b_7 lc_trk_g1_7 +(21 6) routing sp4_v_t_2 lc_trk_g1_7 +(21 7) routing bnr_op_7 lc_trk_g1_7 +(21 7) routing sp12_h_l_20 lc_trk_g1_7 +(21 7) routing sp12_h_l_4 lc_trk_g1_7 +(21 7) routing sp4_h_l_10 lc_trk_g1_7 +(21 7) routing sp4_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 +(21 7) routing sp4_v_t_2 lc_trk_g1_7 +(21 8) routing bnl_op_3 lc_trk_g2_3 +(21 8) routing rgt_op_3 lc_trk_g2_3 +(21 8) routing sp12_v_b_3 lc_trk_g2_3 +(21 8) routing sp4_h_l_22 lc_trk_g2_3 +(21 8) routing sp4_h_r_43 lc_trk_g2_3 +(21 8) routing sp4_v_b_35 lc_trk_g2_3 +(21 8) routing sp4_v_t_14 lc_trk_g2_3 +(21 9) routing bnl_op_3 lc_trk_g2_3 +(21 9) routing sp12_v_b_19 lc_trk_g2_3 +(21 9) routing sp12_v_b_3 lc_trk_g2_3 +(21 9) routing sp4_h_r_27 lc_trk_g2_3 +(21 9) routing sp4_h_r_43 lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 +(21 9) routing sp4_v_b_35 lc_trk_g2_3 +(21 9) routing tnl_op_3 lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_13 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_15 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_13 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_3 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_3 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 lc_trk_g0_3 +(23 0) routing sp12_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_19 lc_trk_g0_3 +(23 0) routing sp4_h_r_3 lc_trk_g0_3 +(23 0) routing sp4_v_b_11 lc_trk_g0_3 +(23 0) routing sp4_v_b_19 lc_trk_g0_3 +(23 0) routing sp4_v_b_3 lc_trk_g0_3 +(23 1) routing sp12_h_l_9 lc_trk_g0_2 +(23 1) routing sp12_h_r_18 lc_trk_g0_2 +(23 1) routing sp4_h_l_7 lc_trk_g0_2 +(23 1) routing sp4_h_r_10 lc_trk_g0_2 +(23 1) routing sp4_h_r_2 lc_trk_g0_2 +(23 1) routing sp4_v_b_10 lc_trk_g0_2 +(23 1) routing sp4_v_b_2 lc_trk_g0_2 +(23 1) routing sp4_v_t_7 lc_trk_g0_2 +(23 10) routing sp12_v_b_15 lc_trk_g2_7 +(23 10) routing sp12_v_b_23 lc_trk_g2_7 +(23 10) routing sp4_h_l_34 lc_trk_g2_7 +(23 10) routing sp4_h_r_31 lc_trk_g2_7 +(23 10) routing sp4_h_r_39 lc_trk_g2_7 +(23 10) routing sp4_v_b_31 lc_trk_g2_7 +(23 10) routing sp4_v_t_26 lc_trk_g2_7 +(23 10) routing sp4_v_t_34 lc_trk_g2_7 +(23 11) routing sp12_v_t_13 lc_trk_g2_6 +(23 11) routing sp12_v_t_21 lc_trk_g2_6 +(23 11) routing sp4_h_l_27 lc_trk_g2_6 +(23 11) routing sp4_h_r_30 lc_trk_g2_6 +(23 11) routing sp4_h_r_46 lc_trk_g2_6 +(23 11) routing sp4_v_b_30 lc_trk_g2_6 +(23 11) routing sp4_v_b_38 lc_trk_g2_6 +(23 11) routing sp4_v_t_35 lc_trk_g2_6 +(23 12) routing sp12_v_b_11 lc_trk_g3_3 +(23 12) routing sp12_v_b_19 lc_trk_g3_3 +(23 12) routing sp4_h_l_22 lc_trk_g3_3 +(23 12) routing sp4_h_r_27 lc_trk_g3_3 +(23 12) routing sp4_h_r_43 lc_trk_g3_3 +(23 12) routing sp4_v_b_35 lc_trk_g3_3 +(23 12) routing sp4_v_t_14 lc_trk_g3_3 +(23 12) routing sp4_v_t_30 lc_trk_g3_3 +(23 13) routing sp12_v_t_17 lc_trk_g3_2 +(23 13) routing sp12_v_t_9 lc_trk_g3_2 +(23 13) routing sp4_h_l_31 lc_trk_g3_2 +(23 13) routing sp4_h_r_26 lc_trk_g3_2 +(23 13) routing sp4_h_r_34 lc_trk_g3_2 +(23 13) routing sp4_v_b_26 lc_trk_g3_2 +(23 13) routing sp4_v_b_42 lc_trk_g3_2 +(23 13) routing sp4_v_t_23 lc_trk_g3_2 +(23 14) routing sp12_v_b_15 lc_trk_g3_7 +(23 14) routing sp12_v_b_23 lc_trk_g3_7 +(23 14) routing sp4_h_l_34 lc_trk_g3_7 +(23 14) routing sp4_h_r_31 lc_trk_g3_7 +(23 14) routing sp4_h_r_39 lc_trk_g3_7 +(23 14) routing sp4_v_b_31 lc_trk_g3_7 +(23 14) routing sp4_v_t_26 lc_trk_g3_7 +(23 14) routing sp4_v_t_34 lc_trk_g3_7 +(23 15) routing sp12_v_t_13 lc_trk_g3_6 +(23 15) routing sp12_v_t_21 lc_trk_g3_6 +(23 15) routing sp4_h_l_27 lc_trk_g3_6 +(23 15) routing sp4_h_r_30 lc_trk_g3_6 +(23 15) routing sp4_h_r_46 lc_trk_g3_6 +(23 15) routing sp4_v_b_30 lc_trk_g3_6 +(23 15) routing sp4_v_b_38 lc_trk_g3_6 +(23 15) routing sp4_v_t_35 lc_trk_g3_6 +(23 2) routing sp12_h_l_12 lc_trk_g0_7 +(23 2) routing sp12_h_l_20 lc_trk_g0_7 +(23 2) routing sp4_h_l_10 lc_trk_g0_7 +(23 2) routing sp4_h_l_2 lc_trk_g0_7 +(23 2) routing sp4_h_r_7 lc_trk_g0_7 +(23 2) routing sp4_v_b_7 lc_trk_g0_7 +(23 2) routing sp4_v_t_10 lc_trk_g0_7 +(23 2) routing sp4_v_t_2 lc_trk_g0_7 +(23 3) routing sp12_h_l_13 lc_trk_g0_6 +(23 3) routing sp12_h_r_22 lc_trk_g0_6 +(23 3) routing sp4_h_l_11 lc_trk_g0_6 +(23 3) routing sp4_h_l_3 lc_trk_g0_6 +(23 3) routing sp4_h_r_6 lc_trk_g0_6 +(23 3) routing sp4_v_b_6 lc_trk_g0_6 +(23 3) routing sp4_v_t_11 lc_trk_g0_6 +(23 3) routing sp4_v_t_3 lc_trk_g0_6 +(23 4) routing sp12_h_l_16 lc_trk_g1_3 +(23 4) routing sp12_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_19 lc_trk_g1_3 +(23 4) routing sp4_h_r_3 lc_trk_g1_3 +(23 4) routing sp4_v_b_11 lc_trk_g1_3 +(23 4) routing sp4_v_b_19 lc_trk_g1_3 +(23 4) routing sp4_v_b_3 lc_trk_g1_3 +(23 5) routing sp12_h_l_9 lc_trk_g1_2 +(23 5) routing sp12_h_r_18 lc_trk_g1_2 +(23 5) routing sp4_h_l_7 lc_trk_g1_2 +(23 5) routing sp4_h_r_10 lc_trk_g1_2 +(23 5) routing sp4_h_r_2 lc_trk_g1_2 +(23 5) routing sp4_v_b_10 lc_trk_g1_2 +(23 5) routing sp4_v_b_2 lc_trk_g1_2 +(23 5) routing sp4_v_t_7 lc_trk_g1_2 +(23 6) routing sp12_h_l_12 lc_trk_g1_7 +(23 6) routing sp12_h_l_20 lc_trk_g1_7 +(23 6) routing sp4_h_l_10 lc_trk_g1_7 +(23 6) routing sp4_h_l_2 lc_trk_g1_7 +(23 6) routing sp4_h_r_7 lc_trk_g1_7 +(23 6) routing sp4_v_b_7 lc_trk_g1_7 +(23 6) routing sp4_v_t_10 lc_trk_g1_7 +(23 6) routing sp4_v_t_2 lc_trk_g1_7 +(23 7) routing sp12_h_l_13 lc_trk_g1_6 +(23 7) routing sp12_h_r_22 lc_trk_g1_6 +(23 7) routing sp4_h_l_11 lc_trk_g1_6 +(23 7) routing sp4_h_l_3 lc_trk_g1_6 +(23 7) routing sp4_h_r_6 lc_trk_g1_6 +(23 7) routing sp4_v_b_6 lc_trk_g1_6 +(23 7) routing sp4_v_t_11 lc_trk_g1_6 +(23 7) routing sp4_v_t_3 lc_trk_g1_6 +(23 8) routing sp12_v_b_11 lc_trk_g2_3 +(23 8) routing sp12_v_b_19 lc_trk_g2_3 +(23 8) routing sp4_h_l_22 lc_trk_g2_3 +(23 8) routing sp4_h_r_27 lc_trk_g2_3 +(23 8) routing sp4_h_r_43 lc_trk_g2_3 +(23 8) routing sp4_v_b_35 lc_trk_g2_3 +(23 8) routing sp4_v_t_14 lc_trk_g2_3 +(23 8) routing sp4_v_t_30 lc_trk_g2_3 +(23 9) routing sp12_v_t_17 lc_trk_g2_2 +(23 9) routing sp12_v_t_9 lc_trk_g2_2 +(23 9) routing sp4_h_l_31 lc_trk_g2_2 +(23 9) routing sp4_h_r_26 lc_trk_g2_2 +(23 9) routing sp4_h_r_34 lc_trk_g2_2 +(23 9) routing sp4_v_b_26 lc_trk_g2_2 +(23 9) routing sp4_v_b_42 lc_trk_g2_2 +(23 9) routing sp4_v_t_23 lc_trk_g2_2 +(24 0) routing lft_op_3 lc_trk_g0_3 +(24 0) routing sp12_h_l_0 lc_trk_g0_3 +(24 0) routing sp4_h_r_11 lc_trk_g0_3 +(24 0) routing sp4_h_r_19 lc_trk_g0_3 +(24 0) routing sp4_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_v_b_19 lc_trk_g0_3 +(24 1) routing sp12_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_h_l_7 lc_trk_g0_2 +(24 1) routing sp4_h_r_10 lc_trk_g0_2 +(24 1) routing sp4_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_v_t_7 lc_trk_g0_2 +(24 10) routing rgt_op_7 lc_trk_g2_7 +(24 10) routing sp12_v_t_4 lc_trk_g2_7 +(24 10) routing sp4_h_l_34 lc_trk_g2_7 +(24 10) routing sp4_h_r_31 lc_trk_g2_7 +(24 10) routing sp4_h_r_39 lc_trk_g2_7 +(24 10) routing sp4_v_t_34 lc_trk_g2_7 +(24 10) routing tnl_op_7 lc_trk_g2_7 +(24 10) routing tnr_op_7 lc_trk_g2_7 +(24 11) routing rgt_op_6 lc_trk_g2_6 +(24 11) routing sp12_v_b_6 lc_trk_g2_6 +(24 11) routing sp4_h_l_27 lc_trk_g2_6 +(24 11) routing sp4_h_r_30 lc_trk_g2_6 +(24 11) routing sp4_h_r_46 lc_trk_g2_6 +(24 11) routing sp4_v_t_35 lc_trk_g2_6 +(24 11) routing tnl_op_6 lc_trk_g2_6 +(24 11) routing tnr_op_6 lc_trk_g2_6 +(24 12) routing rgt_op_3 lc_trk_g3_3 +(24 12) routing sp12_v_b_3 lc_trk_g3_3 +(24 12) routing sp4_h_l_22 lc_trk_g3_3 +(24 12) routing sp4_h_r_27 lc_trk_g3_3 +(24 12) routing sp4_h_r_43 lc_trk_g3_3 +(24 12) routing sp4_v_t_30 lc_trk_g3_3 +(24 12) routing tnl_op_3 lc_trk_g3_3 +(24 12) routing tnr_op_3 lc_trk_g3_3 +(24 13) routing rgt_op_2 lc_trk_g3_2 +(24 13) routing sp12_v_b_2 lc_trk_g3_2 +(24 13) routing sp4_h_l_31 lc_trk_g3_2 +(24 13) routing sp4_h_r_26 lc_trk_g3_2 +(24 13) routing sp4_h_r_34 lc_trk_g3_2 +(24 13) routing sp4_v_b_42 lc_trk_g3_2 +(24 13) routing tnl_op_2 lc_trk_g3_2 +(24 13) routing tnr_op_2 lc_trk_g3_2 +(24 14) routing rgt_op_7 lc_trk_g3_7 +(24 14) routing sp12_v_t_4 lc_trk_g3_7 +(24 14) routing sp4_h_l_34 lc_trk_g3_7 +(24 14) routing sp4_h_r_31 lc_trk_g3_7 +(24 14) routing sp4_h_r_39 lc_trk_g3_7 +(24 14) routing sp4_v_t_34 lc_trk_g3_7 +(24 14) routing tnl_op_7 lc_trk_g3_7 +(24 14) routing tnr_op_7 lc_trk_g3_7 +(24 15) routing rgt_op_6 lc_trk_g3_6 +(24 15) routing sp12_v_b_6 lc_trk_g3_6 +(24 15) routing sp4_h_l_27 lc_trk_g3_6 +(24 15) routing sp4_h_r_30 lc_trk_g3_6 +(24 15) routing sp4_h_r_46 lc_trk_g3_6 +(24 15) routing sp4_v_t_35 lc_trk_g3_6 +(24 15) routing tnl_op_6 lc_trk_g3_6 +(24 15) routing tnr_op_6 lc_trk_g3_6 +(24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_l_4 lc_trk_g0_7 +(24 2) routing sp4_h_l_10 lc_trk_g0_7 +(24 2) routing sp4_h_l_2 lc_trk_g0_7 +(24 2) routing sp4_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_v_t_10 lc_trk_g0_7 +(24 3) routing lft_op_6 lc_trk_g0_6 +(24 3) routing sp12_h_l_5 lc_trk_g0_6 +(24 3) routing sp4_h_l_11 lc_trk_g0_6 +(24 3) routing sp4_h_l_3 lc_trk_g0_6 +(24 3) routing sp4_h_r_6 lc_trk_g0_6 +(24 3) routing sp4_v_t_11 lc_trk_g0_6 +(24 4) routing lft_op_3 lc_trk_g1_3 +(24 4) routing sp12_h_l_0 lc_trk_g1_3 +(24 4) routing sp4_h_r_11 lc_trk_g1_3 +(24 4) routing sp4_h_r_19 lc_trk_g1_3 +(24 4) routing sp4_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_v_b_19 lc_trk_g1_3 +(24 5) routing lft_op_2 lc_trk_g1_2 +(24 5) routing sp12_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_h_l_7 lc_trk_g1_2 +(24 5) routing sp4_h_r_10 lc_trk_g1_2 +(24 5) routing sp4_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_v_t_7 lc_trk_g1_2 +(24 6) routing lft_op_7 lc_trk_g1_7 +(24 6) routing sp12_h_l_4 lc_trk_g1_7 +(24 6) routing sp4_h_l_10 lc_trk_g1_7 +(24 6) routing sp4_h_l_2 lc_trk_g1_7 +(24 6) routing sp4_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_v_t_10 lc_trk_g1_7 +(24 7) routing lft_op_6 lc_trk_g1_6 +(24 7) routing sp12_h_l_5 lc_trk_g1_6 +(24 7) routing sp4_h_l_11 lc_trk_g1_6 +(24 7) routing sp4_h_l_3 lc_trk_g1_6 +(24 7) routing sp4_h_r_6 lc_trk_g1_6 +(24 7) routing sp4_v_t_11 lc_trk_g1_6 +(24 8) routing rgt_op_3 lc_trk_g2_3 +(24 8) routing sp12_v_b_3 lc_trk_g2_3 +(24 8) routing sp4_h_l_22 lc_trk_g2_3 +(24 8) routing sp4_h_r_27 lc_trk_g2_3 +(24 8) routing sp4_h_r_43 lc_trk_g2_3 +(24 8) routing sp4_v_t_30 lc_trk_g2_3 +(24 8) routing tnl_op_3 lc_trk_g2_3 +(24 8) routing tnr_op_3 lc_trk_g2_3 +(24 9) routing rgt_op_2 lc_trk_g2_2 +(24 9) routing sp12_v_b_2 lc_trk_g2_2 +(24 9) routing sp4_h_l_31 lc_trk_g2_2 +(24 9) routing sp4_h_r_26 lc_trk_g2_2 +(24 9) routing sp4_h_r_34 lc_trk_g2_2 +(24 9) routing sp4_v_b_42 lc_trk_g2_2 +(24 9) routing tnl_op_2 lc_trk_g2_2 +(24 9) routing tnr_op_2 lc_trk_g2_2 +(25 0) routing bnr_op_2 lc_trk_g0_2 +(25 0) routing sp12_h_r_2 lc_trk_g0_2 +(25 0) routing sp4_h_l_7 lc_trk_g0_2 +(25 0) routing sp4_h_r_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_2 lc_trk_g0_2 +(25 1) routing bnr_op_2 lc_trk_g0_2 +(25 1) routing sp12_h_r_18 lc_trk_g0_2 +(25 1) routing sp12_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_h_l_7 lc_trk_g0_2 +(25 1) routing sp4_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 +(25 1) routing sp4_v_b_10 lc_trk_g0_2 +(25 10) routing bnl_op_6 lc_trk_g2_6 +(25 10) routing rgt_op_6 lc_trk_g2_6 +(25 10) routing sp12_v_b_6 lc_trk_g2_6 +(25 10) routing sp4_h_l_27 lc_trk_g2_6 +(25 10) routing sp4_h_r_46 lc_trk_g2_6 +(25 10) routing sp4_v_b_30 lc_trk_g2_6 +(25 10) routing sp4_v_b_38 lc_trk_g2_6 +(25 11) routing bnl_op_6 lc_trk_g2_6 +(25 11) routing sp12_v_b_6 lc_trk_g2_6 +(25 11) routing sp12_v_t_21 lc_trk_g2_6 +(25 11) routing sp4_h_r_30 lc_trk_g2_6 +(25 11) routing sp4_h_r_46 lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 +(25 11) routing sp4_v_b_38 lc_trk_g2_6 +(25 11) routing tnl_op_6 lc_trk_g2_6 +(25 12) routing bnl_op_2 lc_trk_g3_2 +(25 12) routing rgt_op_2 lc_trk_g3_2 +(25 12) routing sp12_v_b_2 lc_trk_g3_2 +(25 12) routing sp4_h_l_31 lc_trk_g3_2 +(25 12) routing sp4_h_r_34 lc_trk_g3_2 +(25 12) routing sp4_v_b_26 lc_trk_g3_2 +(25 12) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing bnl_op_2 lc_trk_g3_2 +(25 13) routing sp12_v_b_2 lc_trk_g3_2 +(25 13) routing sp12_v_t_17 lc_trk_g3_2 +(25 13) routing sp4_h_l_31 lc_trk_g3_2 +(25 13) routing sp4_h_r_26 lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 +(25 13) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing tnl_op_2 lc_trk_g3_2 +(25 14) routing bnl_op_6 lc_trk_g3_6 +(25 14) routing rgt_op_6 lc_trk_g3_6 +(25 14) routing sp12_v_b_6 lc_trk_g3_6 +(25 14) routing sp4_h_l_27 lc_trk_g3_6 +(25 14) routing sp4_h_r_46 lc_trk_g3_6 +(25 14) routing sp4_v_b_30 lc_trk_g3_6 +(25 14) routing sp4_v_b_38 lc_trk_g3_6 +(25 15) routing bnl_op_6 lc_trk_g3_6 +(25 15) routing sp12_v_b_6 lc_trk_g3_6 +(25 15) routing sp12_v_t_21 lc_trk_g3_6 +(25 15) routing sp4_h_r_30 lc_trk_g3_6 +(25 15) routing sp4_h_r_46 lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 +(25 15) routing sp4_v_b_38 lc_trk_g3_6 +(25 15) routing tnl_op_6 lc_trk_g3_6 +(25 2) routing bnr_op_6 lc_trk_g0_6 +(25 2) routing lft_op_6 lc_trk_g0_6 +(25 2) routing sp12_h_l_5 lc_trk_g0_6 +(25 2) routing sp4_h_l_11 lc_trk_g0_6 +(25 2) routing sp4_h_l_3 lc_trk_g0_6 +(25 2) routing sp4_v_b_6 lc_trk_g0_6 +(25 2) routing sp4_v_t_3 lc_trk_g0_6 +(25 3) routing bnr_op_6 lc_trk_g0_6 +(25 3) routing sp12_h_l_5 lc_trk_g0_6 +(25 3) routing sp12_h_r_22 lc_trk_g0_6 +(25 3) routing sp4_h_l_11 lc_trk_g0_6 +(25 3) routing sp4_h_r_6 lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 +(25 3) routing sp4_v_t_3 lc_trk_g0_6 +(25 4) routing bnr_op_2 lc_trk_g1_2 +(25 4) routing lft_op_2 lc_trk_g1_2 +(25 4) routing sp12_h_r_2 lc_trk_g1_2 +(25 4) routing sp4_h_l_7 lc_trk_g1_2 +(25 4) routing sp4_h_r_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_2 lc_trk_g1_2 +(25 5) routing bnr_op_2 lc_trk_g1_2 +(25 5) routing sp12_h_r_18 lc_trk_g1_2 +(25 5) routing sp12_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_h_l_7 lc_trk_g1_2 +(25 5) routing sp4_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 +(25 5) routing sp4_v_b_10 lc_trk_g1_2 +(25 6) routing bnr_op_6 lc_trk_g1_6 +(25 6) routing lft_op_6 lc_trk_g1_6 +(25 6) routing sp12_h_l_5 lc_trk_g1_6 +(25 6) routing sp4_h_l_11 lc_trk_g1_6 +(25 6) routing sp4_h_l_3 lc_trk_g1_6 +(25 6) routing sp4_v_b_6 lc_trk_g1_6 +(25 6) routing sp4_v_t_3 lc_trk_g1_6 +(25 7) routing bnr_op_6 lc_trk_g1_6 +(25 7) routing sp12_h_l_5 lc_trk_g1_6 +(25 7) routing sp12_h_r_22 lc_trk_g1_6 +(25 7) routing sp4_h_l_11 lc_trk_g1_6 +(25 7) routing sp4_h_r_6 lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 +(25 7) routing sp4_v_t_3 lc_trk_g1_6 +(25 8) routing bnl_op_2 lc_trk_g2_2 +(25 8) routing rgt_op_2 lc_trk_g2_2 +(25 8) routing sp12_v_b_2 lc_trk_g2_2 +(25 8) routing sp4_h_l_31 lc_trk_g2_2 +(25 8) routing sp4_h_r_34 lc_trk_g2_2 +(25 8) routing sp4_v_b_26 lc_trk_g2_2 +(25 8) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing bnl_op_2 lc_trk_g2_2 +(25 9) routing sp12_v_b_2 lc_trk_g2_2 +(25 9) routing sp12_v_t_17 lc_trk_g2_2 +(25 9) routing sp4_h_l_31 lc_trk_g2_2 +(25 9) routing sp4_h_r_26 lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 +(25 9) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing tnl_op_2 lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(27 0) routing lc_trk_g1_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(27 4) routing lc_trk_g1_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(27 6) routing lc_trk_g1_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(27 8) routing lc_trk_g1_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(28 0) routing lc_trk_g2_1 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(28 4) routing lc_trk_g2_1 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(28 6) routing lc_trk_g2_0 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(28 8) routing lc_trk_g2_1 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(3 0) routing sp12_h_r_0 sp12_v_b_0 +(3 0) routing sp12_v_t_23 sp12_v_b_0 +(3 1) routing sp12_h_l_23 sp12_v_b_0 +(3 1) routing sp12_h_r_0 sp12_v_b_0 +(3 10) routing sp12_v_t_22 sp12_h_l_22 +(3 11) routing sp12_v_b_1 sp12_h_l_22 +(3 12) routing sp12_v_b_1 sp12_h_r_1 +(3 12) routing sp12_v_t_22 sp12_h_r_1 +(3 13) routing sp12_v_b_1 sp12_h_r_1 +(3 14) routing sp12_h_r_1 sp12_v_t_22 +(3 14) routing sp12_v_b_1 sp12_v_t_22 +(3 15) routing sp12_h_l_22 sp12_v_t_22 +(3 15) routing sp12_h_r_1 sp12_v_t_22 +(3 2) routing sp12_h_r_0 sp12_h_l_23 +(3 2) routing sp12_v_t_23 sp12_h_l_23 +(3 3) routing sp12_h_r_0 sp12_h_l_23 +(3 3) routing sp12_v_b_0 sp12_h_l_23 +(3 4) routing sp12_v_b_0 sp12_h_r_0 +(3 4) routing sp12_v_t_23 sp12_h_r_0 +(3 5) routing sp12_h_l_23 sp12_h_r_0 +(3 5) routing sp12_v_b_0 sp12_h_r_0 +(3 6) routing sp12_h_r_0 sp12_v_t_23 +(3 6) routing sp12_v_b_0 sp12_v_t_23 +(3 7) routing sp12_h_l_23 sp12_v_t_23 +(3 7) routing sp12_h_r_0 sp12_v_t_23 +(3 8) routing sp12_h_r_1 sp12_v_b_1 +(3 8) routing sp12_v_t_22 sp12_v_b_1 +(3 9) routing sp12_h_l_22 sp12_v_b_1 +(3 9) routing sp12_h_r_1 sp12_v_b_1 +(30 0) routing lc_trk_g0_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 sp4_v_b_0 +(4 0) routing sp4_h_l_43 sp4_v_b_0 +(4 0) routing sp4_v_t_37 sp4_v_b_0 +(4 0) routing sp4_v_t_41 sp4_v_b_0 +(4 1) routing sp4_h_l_41 sp4_h_r_0 +(4 1) routing sp4_h_l_44 sp4_h_r_0 +(4 1) routing sp4_v_b_6 sp4_h_r_0 +(4 1) routing sp4_v_t_42 sp4_h_r_0 +(4 10) routing sp4_h_r_0 sp4_v_t_43 +(4 10) routing sp4_h_r_6 sp4_v_t_43 +(4 10) routing sp4_v_b_10 sp4_v_t_43 +(4 10) routing sp4_v_b_6 sp4_v_t_43 +(4 11) routing sp4_h_r_10 sp4_h_l_43 +(4 11) routing sp4_v_b_1 sp4_h_l_43 +(4 11) routing sp4_v_t_37 sp4_h_l_43 +(4 12) routing sp4_h_l_38 sp4_v_b_9 +(4 12) routing sp4_h_l_44 sp4_v_b_9 +(4 12) routing sp4_v_t_36 sp4_v_b_9 +(4 12) routing sp4_v_t_44 sp4_v_b_9 +(4 13) routing sp4_h_l_36 sp4_h_r_9 +(4 13) routing sp4_v_b_3 sp4_h_r_9 +(4 13) routing sp4_v_t_41 sp4_h_r_9 +(4 14) routing sp4_h_r_3 sp4_v_t_44 +(4 14) routing sp4_h_r_9 sp4_v_t_44 +(4 14) routing sp4_v_b_1 sp4_v_t_44 +(4 14) routing sp4_v_b_9 sp4_v_t_44 +(4 15) routing sp4_h_r_6 sp4_h_l_44 +(4 15) routing sp4_v_b_4 sp4_h_l_44 +(4 15) routing sp4_v_t_38 sp4_h_l_44 +(4 2) routing sp4_h_r_0 sp4_v_t_37 +(4 2) routing sp4_h_r_6 sp4_v_t_37 +(4 2) routing sp4_v_b_0 sp4_v_t_37 +(4 2) routing sp4_v_b_4 sp4_v_t_37 +(4 3) routing sp4_h_r_4 sp4_h_l_37 +(4 3) routing sp4_h_r_9 sp4_h_l_37 +(4 3) routing sp4_v_b_7 sp4_h_l_37 +(4 3) routing sp4_v_t_43 sp4_h_l_37 +(4 4) routing sp4_h_l_38 sp4_v_b_3 +(4 4) routing sp4_h_l_44 sp4_v_b_3 +(4 4) routing sp4_v_t_38 sp4_v_b_3 +(4 4) routing sp4_v_t_42 sp4_v_b_3 +(4 5) routing sp4_v_b_9 sp4_h_r_3 +(4 5) routing sp4_v_t_47 sp4_h_r_3 +(4 6) routing sp4_h_r_3 sp4_v_t_38 +(4 6) routing sp4_h_r_9 sp4_v_t_38 +(4 6) routing sp4_v_b_3 sp4_v_t_38 +(4 6) routing sp4_v_b_7 sp4_v_t_38 +(4 7) routing sp4_h_r_0 sp4_h_l_38 +(4 7) routing sp4_v_b_10 sp4_h_l_38 +(4 7) routing sp4_v_t_44 sp4_h_l_38 +(4 8) routing sp4_h_l_37 sp4_v_b_6 +(4 8) routing sp4_h_l_43 sp4_v_b_6 +(4 8) routing sp4_v_t_43 sp4_v_b_6 +(4 8) routing sp4_v_t_47 sp4_v_b_6 +(4 9) routing sp4_h_l_47 sp4_h_r_6 +(4 9) routing sp4_v_b_0 sp4_h_r_6 +(4 9) routing sp4_v_t_36 sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_8 sp4_h_r_16 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_8 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_13 sp4_h_r_26 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_13 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_14 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_14 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_15 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_15 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_9 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_9 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_10 sp4_h_l_9 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_10 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_11 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_11 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_12 sp4_h_r_24 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_12 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_8 sp12_h_r_8 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_8 sp4_h_l_21 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_13 sp12_h_r_2 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_13 sp4_h_l_31 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_14 sp12_h_l_3 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_14 sp4_h_r_44 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_15 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_15 sp4_h_r_46 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_9 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_9 sp4_h_r_34 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_10 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_10 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_11 sp12_h_l_13 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_11 sp4_h_l_27 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_12 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_12 sp4_h_r_40 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_8 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_8 sp4_v_b_16 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_13 sp12_h_r_18 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_13 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_14 sp12_h_l_19 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_14 sp4_v_b_12 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_15 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_15 sp4_v_t_3 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_9 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_9 sp4_v_t_7 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_10 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_10 sp4_v_t_9 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_11 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_11 sp4_v_t_11 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_12 sp12_h_l_15 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_12 sp4_v_b_8 +(5 0) routing sp4_h_l_44 sp4_h_r_0 +(5 0) routing sp4_v_b_0 sp4_h_r_0 +(5 0) routing sp4_v_b_6 sp4_h_r_0 +(5 0) routing sp4_v_t_37 sp4_h_r_0 +(5 1) routing sp4_h_l_37 sp4_v_b_0 +(5 1) routing sp4_h_l_43 sp4_v_b_0 +(5 1) routing sp4_h_r_0 sp4_v_b_0 +(5 1) routing sp4_v_t_44 sp4_v_b_0 +(5 10) routing sp4_v_b_6 sp4_h_l_43 +(5 10) routing sp4_v_t_37 sp4_h_l_43 +(5 10) routing sp4_v_t_43 sp4_h_l_43 +(5 11) routing sp4_h_l_43 sp4_v_t_43 +(5 11) routing sp4_h_r_0 sp4_v_t_43 +(5 11) routing sp4_h_r_6 sp4_v_t_43 +(5 11) routing sp4_v_b_3 sp4_v_t_43 +(5 12) routing sp4_v_b_3 sp4_h_r_9 +(5 12) routing sp4_v_b_9 sp4_h_r_9 +(5 12) routing sp4_v_t_44 sp4_h_r_9 +(5 13) routing sp4_h_l_38 sp4_v_b_9 +(5 13) routing sp4_h_l_44 sp4_v_b_9 +(5 13) routing sp4_h_r_9 sp4_v_b_9 +(5 13) routing sp4_v_t_43 sp4_v_b_9 +(5 14) routing sp4_h_r_6 sp4_h_l_44 +(5 14) routing sp4_v_b_9 sp4_h_l_44 +(5 14) routing sp4_v_t_38 sp4_h_l_44 +(5 14) routing sp4_v_t_44 sp4_h_l_44 +(5 15) routing sp4_h_l_44 sp4_v_t_44 +(5 15) routing sp4_h_r_3 sp4_v_t_44 +(5 15) routing sp4_h_r_9 sp4_v_t_44 +(5 15) routing sp4_v_b_6 sp4_v_t_44 +(5 2) routing sp4_h_r_9 sp4_h_l_37 +(5 2) routing sp4_v_b_0 sp4_h_l_37 +(5 2) routing sp4_v_t_37 sp4_h_l_37 +(5 2) routing sp4_v_t_43 sp4_h_l_37 +(5 3) routing sp4_h_l_37 sp4_v_t_37 +(5 3) routing sp4_h_r_0 sp4_v_t_37 +(5 3) routing sp4_h_r_6 sp4_v_t_37 +(5 3) routing sp4_v_b_9 sp4_v_t_37 +(5 4) routing sp4_v_b_3 sp4_h_r_3 +(5 4) routing sp4_v_b_9 sp4_h_r_3 +(5 4) routing sp4_v_t_38 sp4_h_r_3 +(5 5) routing sp4_h_l_38 sp4_v_b_3 +(5 5) routing sp4_h_l_44 sp4_v_b_3 +(5 5) routing sp4_h_r_3 sp4_v_b_3 +(5 5) routing sp4_v_t_37 sp4_v_b_3 +(5 6) routing sp4_h_r_0 sp4_h_l_38 +(5 6) routing sp4_v_b_3 sp4_h_l_38 +(5 6) routing sp4_v_t_38 sp4_h_l_38 +(5 6) routing sp4_v_t_44 sp4_h_l_38 +(5 7) routing sp4_h_l_38 sp4_v_t_38 +(5 7) routing sp4_h_r_3 sp4_v_t_38 +(5 7) routing sp4_h_r_9 sp4_v_t_38 +(5 7) routing sp4_v_b_0 sp4_v_t_38 +(5 8) routing sp4_v_b_0 sp4_h_r_6 +(5 8) routing sp4_v_b_6 sp4_h_r_6 +(5 8) routing sp4_v_t_43 sp4_h_r_6 +(5 9) routing sp4_h_l_37 sp4_v_b_6 +(5 9) routing sp4_h_l_43 sp4_v_b_6 +(5 9) routing sp4_h_r_6 sp4_v_b_6 +(5 9) routing sp4_v_t_38 sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT1_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT1_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT1_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT1_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT1_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT1_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT1_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT1_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_8 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_8 sp4_v_t_21 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_13 sp4_v_b_42 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_13 sp4_v_b_26 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_14 sp4_v_t_33 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_14 sp4_v_t_17 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_15 sp4_v_t_35 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_15 sp4_v_b_30 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_9 sp12_v_b_2 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_9 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_10 sp12_v_t_3 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_10 sp4_v_t_25 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_11 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_11 sp4_v_b_38 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_12 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_12 sp4_v_b_24 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_8 sp12_v_t_15 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_8 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_13 sp12_v_t_9 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_13 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_14 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_14 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_15 sp12_v_t_13 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_15 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_9 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_9 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_10 sp12_v_t_19 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_10 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_11 sp12_v_t_21 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_11 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_12 sp12_v_b_8 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_12 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_8 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_8 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_13 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_13 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_14 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_14 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_15 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_15 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_9 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_9 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_10 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_10 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_11 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_11 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_12 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_12 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 sp4_v_b_0 +(6 0) routing sp4_h_r_7 sp4_v_b_0 +(6 0) routing sp4_v_t_41 sp4_v_b_0 +(6 0) routing sp4_v_t_44 sp4_v_b_0 +(6 1) routing sp4_h_l_37 sp4_h_r_0 +(6 1) routing sp4_h_l_41 sp4_h_r_0 +(6 1) routing sp4_v_b_0 sp4_h_r_0 +(6 1) routing sp4_v_b_6 sp4_h_r_0 +(6 10) routing sp4_h_l_36 sp4_v_t_43 +(6 10) routing sp4_h_r_0 sp4_v_t_43 +(6 10) routing sp4_v_b_10 sp4_v_t_43 +(6 10) routing sp4_v_b_3 sp4_v_t_43 +(6 11) routing sp4_h_r_10 sp4_h_l_43 +(6 11) routing sp4_h_r_6 sp4_h_l_43 +(6 11) routing sp4_v_t_37 sp4_h_l_43 +(6 11) routing sp4_v_t_43 sp4_h_l_43 +(6 12) routing sp4_h_l_38 sp4_v_b_9 +(6 12) routing sp4_h_r_4 sp4_v_b_9 +(6 12) routing sp4_v_t_36 sp4_v_b_9 +(6 12) routing sp4_v_t_43 sp4_v_b_9 +(6 13) routing sp4_h_l_36 sp4_h_r_9 +(6 13) routing sp4_v_b_3 sp4_h_r_9 +(6 13) routing sp4_v_b_9 sp4_h_r_9 +(6 14) routing sp4_h_l_41 sp4_v_t_44 +(6 14) routing sp4_h_r_3 sp4_v_t_44 +(6 14) routing sp4_v_b_1 sp4_v_t_44 +(6 14) routing sp4_v_b_6 sp4_v_t_44 +(6 15) routing sp4_h_r_9 sp4_h_l_44 +(6 15) routing sp4_v_t_38 sp4_h_l_44 +(6 15) routing sp4_v_t_44 sp4_h_l_44 +(6 2) routing sp4_h_l_42 sp4_v_t_37 +(6 2) routing sp4_h_r_6 sp4_v_t_37 +(6 2) routing sp4_v_b_4 sp4_v_t_37 +(6 2) routing sp4_v_b_9 sp4_v_t_37 +(6 3) routing sp4_h_r_0 sp4_h_l_37 +(6 3) routing sp4_h_r_4 sp4_h_l_37 +(6 3) routing sp4_v_t_37 sp4_h_l_37 +(6 3) routing sp4_v_t_43 sp4_h_l_37 +(6 4) routing sp4_h_l_44 sp4_v_b_3 +(6 4) routing sp4_h_r_10 sp4_v_b_3 +(6 4) routing sp4_v_t_37 sp4_v_b_3 +(6 4) routing sp4_v_t_42 sp4_v_b_3 +(6 5) routing sp4_v_b_3 sp4_h_r_3 +(6 5) routing sp4_v_b_9 sp4_h_r_3 +(6 6) routing sp4_h_l_47 sp4_v_t_38 +(6 6) routing sp4_h_r_9 sp4_v_t_38 +(6 6) routing sp4_v_b_0 sp4_v_t_38 +(6 6) routing sp4_v_b_7 sp4_v_t_38 +(6 7) routing sp4_v_t_38 sp4_h_l_38 +(6 7) routing sp4_v_t_44 sp4_h_l_38 +(6 8) routing sp4_h_l_37 sp4_v_b_6 +(6 8) routing sp4_h_r_1 sp4_v_b_6 +(6 8) routing sp4_v_t_38 sp4_v_b_6 +(6 8) routing sp4_v_t_47 sp4_v_b_6 +(6 9) routing sp4_h_l_43 sp4_h_r_6 +(6 9) routing sp4_h_l_47 sp4_h_r_6 +(6 9) routing sp4_v_b_0 sp4_h_r_6 +(6 9) routing sp4_v_b_6 sp4_h_r_6 +(7 0) MAC16 functional bit: MULT1_bram_cbit_1 +(7 1) MAC16 functional bit: MULT1_bram_cbit_0 +(7 2) Hard IP config bit: MULT1_bram_cbit_3 +(7 2) MAC16 functional bit: MULT1_bram_cbit_3 +(7 3) MAC16 functional bit: MULT1_bram_cbit_2 +(7 5) Hard IP config bit: MULT1_bram_cbit_4 +(7 5) MAC16 functional bit: MULT1_bram_cbit_4 +(7 6) MAC16 functional bit: MULT1_bram_cbit_7 +(7 7) MAC16 functional bit: MULT1_bram_cbit_6 +(8 0) routing sp4_h_l_40 sp4_h_r_1 +(8 0) routing sp4_v_b_1 sp4_h_r_1 +(8 0) routing sp4_v_b_7 sp4_h_r_1 +(8 1) routing sp4_h_l_36 sp4_v_b_1 +(8 1) routing sp4_h_l_42 sp4_v_b_1 +(8 1) routing sp4_h_r_1 sp4_v_b_1 +(8 1) routing sp4_v_t_47 sp4_v_b_1 +(8 10) routing sp4_v_t_36 sp4_h_l_42 +(8 10) routing sp4_v_t_42 sp4_h_l_42 +(8 11) routing sp4_h_l_42 sp4_v_t_42 +(8 11) routing sp4_h_r_1 sp4_v_t_42 +(8 11) routing sp4_h_r_7 sp4_v_t_42 +(8 11) routing sp4_v_b_4 sp4_v_t_42 +(8 12) routing sp4_v_b_10 sp4_h_r_10 +(8 12) routing sp4_v_b_4 sp4_h_r_10 +(8 13) routing sp4_h_l_41 sp4_v_b_10 +(8 13) routing sp4_h_l_47 sp4_v_b_10 +(8 13) routing sp4_h_r_10 sp4_v_b_10 +(8 13) routing sp4_v_t_42 sp4_v_b_10 +(8 14) routing sp4_h_r_10 sp4_h_l_47 +(8 14) routing sp4_h_r_2 sp4_h_l_47 +(8 14) routing sp4_v_t_41 sp4_h_l_47 +(8 15) routing sp4_h_l_47 sp4_v_t_47 +(8 15) routing sp4_h_r_10 sp4_v_t_47 +(8 15) routing sp4_h_r_4 sp4_v_t_47 +(8 15) routing sp4_v_b_7 sp4_v_t_47 +(8 2) routing sp4_v_t_36 sp4_h_l_36 +(8 2) routing sp4_v_t_42 sp4_h_l_36 +(8 3) routing sp4_h_l_36 sp4_v_t_36 +(8 3) routing sp4_h_r_1 sp4_v_t_36 +(8 3) routing sp4_h_r_7 sp4_v_t_36 +(8 3) routing sp4_v_b_10 sp4_v_t_36 +(8 4) routing sp4_h_l_45 sp4_h_r_4 +(8 4) routing sp4_v_b_10 sp4_h_r_4 +(8 4) routing sp4_v_b_4 sp4_h_r_4 +(8 5) routing sp4_h_l_41 sp4_v_b_4 +(8 5) routing sp4_h_l_47 sp4_v_b_4 +(8 5) routing sp4_h_r_4 sp4_v_b_4 +(8 5) routing sp4_v_t_36 sp4_v_b_4 +(8 6) routing sp4_h_r_4 sp4_h_l_41 +(8 6) routing sp4_h_r_8 sp4_h_l_41 +(8 6) routing sp4_v_t_41 sp4_h_l_41 +(8 6) routing sp4_v_t_47 sp4_h_l_41 +(8 7) routing sp4_h_l_41 sp4_v_t_41 +(8 7) routing sp4_h_r_10 sp4_v_t_41 +(8 7) routing sp4_h_r_4 sp4_v_t_41 +(8 7) routing sp4_v_b_1 sp4_v_t_41 +(8 8) routing sp4_h_l_42 sp4_h_r_7 +(8 8) routing sp4_v_b_1 sp4_h_r_7 +(8 8) routing sp4_v_b_7 sp4_h_r_7 +(8 9) routing sp4_h_l_36 sp4_v_b_7 +(8 9) routing sp4_h_l_42 sp4_v_b_7 +(8 9) routing sp4_h_r_7 sp4_v_b_7 +(8 9) routing sp4_v_t_41 sp4_v_b_7 +(9 0) routing sp4_v_b_1 sp4_h_r_1 +(9 0) routing sp4_v_b_7 sp4_h_r_1 +(9 0) routing sp4_v_t_36 sp4_h_r_1 +(9 1) routing sp4_h_l_36 sp4_v_b_1 +(9 1) routing sp4_h_l_42 sp4_v_b_1 +(9 1) routing sp4_v_t_36 sp4_v_b_1 +(9 1) routing sp4_v_t_40 sp4_v_b_1 +(9 10) routing sp4_h_r_4 sp4_h_l_42 +(9 10) routing sp4_v_b_7 sp4_h_l_42 +(9 10) routing sp4_v_t_36 sp4_h_l_42 +(9 10) routing sp4_v_t_42 sp4_h_l_42 +(9 11) routing sp4_h_r_1 sp4_v_t_42 +(9 11) routing sp4_h_r_7 sp4_v_t_42 +(9 11) routing sp4_v_b_11 sp4_v_t_42 +(9 11) routing sp4_v_b_7 sp4_v_t_42 +(9 12) routing sp4_v_b_10 sp4_h_r_10 +(9 12) routing sp4_v_b_4 sp4_h_r_10 +(9 12) routing sp4_v_t_47 sp4_h_r_10 +(9 13) routing sp4_h_l_41 sp4_v_b_10 +(9 13) routing sp4_h_l_47 sp4_v_b_10 +(9 13) routing sp4_v_t_39 sp4_v_b_10 +(9 13) routing sp4_v_t_47 sp4_v_b_10 +(9 14) routing sp4_v_b_10 sp4_h_l_47 +(9 14) routing sp4_v_t_41 sp4_h_l_47 +(9 15) routing sp4_h_r_10 sp4_v_t_47 +(9 15) routing sp4_h_r_4 sp4_v_t_47 +(9 15) routing sp4_v_b_10 sp4_v_t_47 +(9 15) routing sp4_v_b_2 sp4_v_t_47 +(9 2) routing sp4_h_r_10 sp4_h_l_36 +(9 2) routing sp4_v_b_1 sp4_h_l_36 +(9 2) routing sp4_v_t_36 sp4_h_l_36 +(9 2) routing sp4_v_t_42 sp4_h_l_36 +(9 3) routing sp4_h_r_1 sp4_v_t_36 +(9 3) routing sp4_h_r_7 sp4_v_t_36 +(9 3) routing sp4_v_b_1 sp4_v_t_36 +(9 3) routing sp4_v_b_5 sp4_v_t_36 +(9 4) routing sp4_v_b_10 sp4_h_r_4 +(9 4) routing sp4_v_b_4 sp4_h_r_4 +(9 4) routing sp4_v_t_41 sp4_h_r_4 +(9 5) routing sp4_h_l_41 sp4_v_b_4 +(9 5) routing sp4_h_l_47 sp4_v_b_4 +(9 5) routing sp4_v_t_41 sp4_v_b_4 +(9 5) routing sp4_v_t_45 sp4_v_b_4 +(9 6) routing sp4_v_b_4 sp4_h_l_41 +(9 6) routing sp4_v_t_41 sp4_h_l_41 +(9 6) routing sp4_v_t_47 sp4_h_l_41 +(9 7) routing sp4_h_r_10 sp4_v_t_41 +(9 7) routing sp4_h_r_4 sp4_v_t_41 +(9 7) routing sp4_v_b_4 sp4_v_t_41 +(9 7) routing sp4_v_b_8 sp4_v_t_41 +(9 8) routing sp4_h_l_41 sp4_h_r_7 +(9 8) routing sp4_v_b_1 sp4_h_r_7 +(9 8) routing sp4_v_b_7 sp4_h_r_7 +(9 8) routing sp4_v_t_42 sp4_h_r_7 +(9 9) routing sp4_h_l_36 sp4_v_b_7 +(9 9) routing sp4_h_l_42 sp4_v_b_7 +(9 9) routing sp4_v_t_42 sp4_v_b_7 +(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/cached_dsp2_5k.txt b/icefuzz/cached_dsp2_5k.txt index e69de29..1904fae 100644 --- a/icefuzz/cached_dsp2_5k.txt +++ b/icefuzz/cached_dsp2_5k.txt @@ -0,0 +1,3057 @@ +(0 0) Negative Clock bit +(0 10) routing glb_netwk_2 glb2local_2 +(0 10) routing glb_netwk_3 glb2local_2 +(0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 +(0 11) routing glb_netwk_3 glb2local_2 +(0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_2 glb2local_3 +(0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 +(0 13) routing glb_netwk_1 glb2local_3 +(0 13) routing glb_netwk_3 glb2local_3 +(0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 +(0 14) routing glb_netwk_4 wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 2) routing glb_netwk_2 wire_mult/lc_7/clk +(0 2) routing glb_netwk_3 wire_mult/lc_7/clk +(0 2) routing glb_netwk_6 wire_mult/lc_7/clk +(0 2) routing glb_netwk_7 wire_mult/lc_7/clk +(0 2) routing lc_trk_g2_0 wire_mult/lc_7/clk +(0 2) routing lc_trk_g3_1 wire_mult/lc_7/clk +(0 3) routing glb_netwk_1 wire_mult/lc_7/clk +(0 3) routing glb_netwk_3 wire_mult/lc_7/clk +(0 3) routing glb_netwk_5 wire_mult/lc_7/clk +(0 3) routing glb_netwk_7 wire_mult/lc_7/clk +(0 3) routing lc_trk_g1_1 wire_mult/lc_7/clk +(0 3) routing lc_trk_g3_1 wire_mult/lc_7/clk +(0 4) routing lc_trk_g2_2 wire_mult/lc_7/cen +(0 4) routing lc_trk_g3_3 wire_mult/lc_7/cen +(0 5) routing lc_trk_g1_3 wire_mult/lc_7/cen +(0 5) routing lc_trk_g3_3 wire_mult/lc_7/cen +(0 6) routing glb_netwk_2 glb2local_0 +(0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 +(0 7) routing glb_netwk_1 glb2local_0 +(0 7) routing glb_netwk_3 glb2local_0 +(0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_2 glb2local_1 +(0 8) routing glb_netwk_3 glb2local_1 +(0 8) routing glb_netwk_6 glb2local_1 +(0 8) routing glb_netwk_7 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 +(0 9) routing glb_netwk_5 glb2local_1 +(0 9) routing glb_netwk_7 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 glb2local_2 +(1 11) routing glb_netwk_5 glb2local_2 +(1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 +(1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(1 2) routing glb_netwk_4 wire_mult/lc_7/clk +(1 2) routing glb_netwk_5 wire_mult/lc_7/clk +(1 2) routing glb_netwk_6 wire_mult/lc_7/clk +(1 2) routing glb_netwk_7 wire_mult/lc_7/clk +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_mult/lc_7/cen +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_mult/lc_7/cen +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_mult/lc_7/cen +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_mult/lc_7/cen +(1 5) routing lc_trk_g0_2 wire_mult/lc_7/cen +(1 5) routing lc_trk_g1_3 wire_mult/lc_7/cen +(1 5) routing lc_trk_g2_2 wire_mult/lc_7/cen +(1 5) routing lc_trk_g3_3 wire_mult/lc_7/cen +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 +(1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 +(1 9) routing glb_netwk_5 glb2local_1 +(1 9) routing glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_7 glb2local_1 +(10 0) routing sp4_h_l_40 sp4_h_r_1 +(10 0) routing sp4_v_b_7 sp4_h_r_1 +(10 0) routing sp4_v_t_45 sp4_h_r_1 +(10 1) routing sp4_h_l_42 sp4_v_b_1 +(10 1) routing sp4_h_r_8 sp4_v_b_1 +(10 1) routing sp4_v_t_40 sp4_v_b_1 +(10 1) routing sp4_v_t_47 sp4_v_b_1 +(10 10) routing sp4_h_r_4 sp4_h_l_42 +(10 10) routing sp4_v_b_2 sp4_h_l_42 +(10 10) routing sp4_v_t_36 sp4_h_l_42 +(10 11) routing sp4_h_l_39 sp4_v_t_42 +(10 11) routing sp4_h_r_1 sp4_v_t_42 +(10 11) routing sp4_v_b_11 sp4_v_t_42 +(10 11) routing sp4_v_b_4 sp4_v_t_42 +(10 12) routing sp4_h_l_39 sp4_h_r_10 +(10 12) routing sp4_v_b_4 sp4_h_r_10 +(10 12) routing sp4_v_t_40 sp4_h_r_10 +(10 13) routing sp4_h_l_41 sp4_v_b_10 +(10 13) routing sp4_h_r_5 sp4_v_b_10 +(10 13) routing sp4_v_t_39 sp4_v_b_10 +(10 13) routing sp4_v_t_42 sp4_v_b_10 +(10 14) routing sp4_h_r_2 sp4_h_l_47 +(10 14) routing sp4_v_b_5 sp4_h_l_47 +(10 14) routing sp4_v_t_41 sp4_h_l_47 +(10 15) routing sp4_h_l_40 sp4_v_t_47 +(10 15) routing sp4_h_r_4 sp4_v_t_47 +(10 15) routing sp4_v_b_2 sp4_v_t_47 +(10 15) routing sp4_v_b_7 sp4_v_t_47 +(10 2) routing sp4_h_r_10 sp4_h_l_36 +(10 2) routing sp4_v_b_8 sp4_h_l_36 +(10 2) routing sp4_v_t_42 sp4_h_l_36 +(10 3) routing sp4_h_l_45 sp4_v_t_36 +(10 3) routing sp4_h_r_7 sp4_v_t_36 +(10 3) routing sp4_v_b_10 sp4_v_t_36 +(10 3) routing sp4_v_b_5 sp4_v_t_36 +(10 4) routing sp4_h_l_45 sp4_h_r_4 +(10 4) routing sp4_v_b_10 sp4_h_r_4 +(10 4) routing sp4_v_t_46 sp4_h_r_4 +(10 5) routing sp4_h_l_47 sp4_v_b_4 +(10 5) routing sp4_h_r_11 sp4_v_b_4 +(10 5) routing sp4_v_t_36 sp4_v_b_4 +(10 5) routing sp4_v_t_45 sp4_v_b_4 +(10 6) routing sp4_h_r_8 sp4_h_l_41 +(10 6) routing sp4_v_b_11 sp4_h_l_41 +(10 6) routing sp4_v_t_47 sp4_h_l_41 +(10 7) routing sp4_h_l_46 sp4_v_t_41 +(10 7) routing sp4_h_r_10 sp4_v_t_41 +(10 7) routing sp4_v_b_1 sp4_v_t_41 +(10 7) routing sp4_v_b_8 sp4_v_t_41 +(10 8) routing sp4_v_b_1 sp4_h_r_7 +(10 8) routing sp4_v_t_39 sp4_h_r_7 +(10 9) routing sp4_h_l_36 sp4_v_b_7 +(10 9) routing sp4_h_r_2 sp4_v_b_7 +(10 9) routing sp4_v_t_41 sp4_v_b_7 +(10 9) routing sp4_v_t_46 sp4_v_b_7 +(11 0) routing sp4_h_l_45 sp4_v_b_2 +(11 0) routing sp4_h_r_9 sp4_v_b_2 +(11 0) routing sp4_v_t_43 sp4_v_b_2 +(11 0) routing sp4_v_t_46 sp4_v_b_2 +(11 1) routing sp4_h_l_39 sp4_h_r_2 +(11 1) routing sp4_h_l_43 sp4_h_r_2 +(11 1) routing sp4_v_b_2 sp4_h_r_2 +(11 1) routing sp4_v_b_8 sp4_h_r_2 +(11 10) routing sp4_h_l_38 sp4_v_t_45 +(11 10) routing sp4_h_r_2 sp4_v_t_45 +(11 10) routing sp4_v_b_0 sp4_v_t_45 +(11 10) routing sp4_v_b_5 sp4_v_t_45 +(11 11) routing sp4_h_r_0 sp4_h_l_45 +(11 11) routing sp4_h_r_8 sp4_h_l_45 +(11 11) routing sp4_v_t_39 sp4_h_l_45 +(11 11) routing sp4_v_t_45 sp4_h_l_45 +(11 12) routing sp4_h_l_40 sp4_v_b_11 +(11 12) routing sp4_h_r_6 sp4_v_b_11 +(11 12) routing sp4_v_t_38 sp4_v_b_11 +(11 12) routing sp4_v_t_45 sp4_v_b_11 +(11 13) routing sp4_h_l_46 sp4_h_r_11 +(11 13) routing sp4_v_b_11 sp4_h_r_11 +(11 13) routing sp4_v_b_5 sp4_h_r_11 +(11 14) routing sp4_h_l_43 sp4_v_t_46 +(11 14) routing sp4_h_r_5 sp4_v_t_46 +(11 14) routing sp4_v_b_3 sp4_v_t_46 +(11 14) routing sp4_v_b_8 sp4_v_t_46 +(11 15) routing sp4_v_t_40 sp4_h_l_46 +(11 15) routing sp4_v_t_46 sp4_h_l_46 +(11 2) routing sp4_h_l_44 sp4_v_t_39 +(11 2) routing sp4_h_r_8 sp4_v_t_39 +(11 2) routing sp4_v_b_11 sp4_v_t_39 +(11 2) routing sp4_v_b_6 sp4_v_t_39 +(11 3) routing sp4_h_r_2 sp4_h_l_39 +(11 3) routing sp4_h_r_6 sp4_h_l_39 +(11 3) routing sp4_v_t_39 sp4_h_l_39 +(11 3) routing sp4_v_t_45 sp4_h_l_39 +(11 4) routing sp4_h_l_46 sp4_v_b_5 +(11 4) routing sp4_h_r_0 sp4_v_b_5 +(11 4) routing sp4_v_t_39 sp4_v_b_5 +(11 4) routing sp4_v_t_44 sp4_v_b_5 +(11 5) routing sp4_h_l_40 sp4_h_r_5 +(11 5) routing sp4_h_l_44 sp4_h_r_5 +(11 5) routing sp4_v_b_11 sp4_h_r_5 +(11 5) routing sp4_v_b_5 sp4_h_r_5 +(11 6) routing sp4_h_l_37 sp4_v_t_40 +(11 6) routing sp4_h_r_11 sp4_v_t_40 +(11 6) routing sp4_v_b_2 sp4_v_t_40 +(11 6) routing sp4_v_b_9 sp4_v_t_40 +(11 7) routing sp4_h_r_9 sp4_h_l_40 +(11 7) routing sp4_v_t_40 sp4_h_l_40 +(11 7) routing sp4_v_t_46 sp4_h_l_40 +(11 8) routing sp4_h_l_39 sp4_v_b_8 +(11 8) routing sp4_h_r_3 sp4_v_b_8 +(11 8) routing sp4_v_t_37 sp4_v_b_8 +(11 8) routing sp4_v_t_40 sp4_v_b_8 +(11 9) routing sp4_h_l_37 sp4_h_r_8 +(11 9) routing sp4_v_b_2 sp4_h_r_8 +(11 9) routing sp4_v_b_8 sp4_h_r_8 +(12 0) routing sp4_h_l_46 sp4_h_r_2 +(12 0) routing sp4_v_b_2 sp4_h_r_2 +(12 0) routing sp4_v_b_8 sp4_h_r_2 +(12 0) routing sp4_v_t_39 sp4_h_r_2 +(12 1) routing sp4_h_l_39 sp4_v_b_2 +(12 1) routing sp4_h_l_45 sp4_v_b_2 +(12 1) routing sp4_h_r_2 sp4_v_b_2 +(12 1) routing sp4_v_t_46 sp4_v_b_2 +(12 10) routing sp4_v_b_8 sp4_h_l_45 +(12 10) routing sp4_v_t_39 sp4_h_l_45 +(12 10) routing sp4_v_t_45 sp4_h_l_45 +(12 11) routing sp4_h_l_45 sp4_v_t_45 +(12 11) routing sp4_h_r_2 sp4_v_t_45 +(12 11) routing sp4_h_r_8 sp4_v_t_45 +(12 11) routing sp4_v_b_5 sp4_v_t_45 +(12 12) routing sp4_h_l_45 sp4_h_r_11 +(12 12) routing sp4_v_b_11 sp4_h_r_11 +(12 12) routing sp4_v_b_5 sp4_h_r_11 +(12 12) routing sp4_v_t_46 sp4_h_r_11 +(12 13) routing sp4_h_l_40 sp4_v_b_11 +(12 13) routing sp4_h_l_46 sp4_v_b_11 +(12 13) routing sp4_h_r_11 sp4_v_b_11 +(12 13) routing sp4_v_t_45 sp4_v_b_11 +(12 14) routing sp4_h_r_8 sp4_h_l_46 +(12 14) routing sp4_v_b_11 sp4_h_l_46 +(12 14) routing sp4_v_t_40 sp4_h_l_46 +(12 14) routing sp4_v_t_46 sp4_h_l_46 +(12 15) routing sp4_h_l_46 sp4_v_t_46 +(12 15) routing sp4_h_r_11 sp4_v_t_46 +(12 15) routing sp4_h_r_5 sp4_v_t_46 +(12 15) routing sp4_v_b_8 sp4_v_t_46 +(12 2) routing sp4_v_b_2 sp4_h_l_39 +(12 2) routing sp4_v_t_39 sp4_h_l_39 +(12 2) routing sp4_v_t_45 sp4_h_l_39 +(12 3) routing sp4_h_l_39 sp4_v_t_39 +(12 3) routing sp4_h_r_2 sp4_v_t_39 +(12 3) routing sp4_h_r_8 sp4_v_t_39 +(12 3) routing sp4_v_b_11 sp4_v_t_39 +(12 4) routing sp4_v_b_11 sp4_h_r_5 +(12 4) routing sp4_v_b_5 sp4_h_r_5 +(12 4) routing sp4_v_t_40 sp4_h_r_5 +(12 5) routing sp4_h_l_40 sp4_v_b_5 +(12 5) routing sp4_h_l_46 sp4_v_b_5 +(12 5) routing sp4_h_r_5 sp4_v_b_5 +(12 5) routing sp4_v_t_39 sp4_v_b_5 +(12 6) routing sp4_h_r_2 sp4_h_l_40 +(12 6) routing sp4_v_b_5 sp4_h_l_40 +(12 6) routing sp4_v_t_40 sp4_h_l_40 +(12 6) routing sp4_v_t_46 sp4_h_l_40 +(12 7) routing sp4_h_l_40 sp4_v_t_40 +(12 7) routing sp4_h_r_11 sp4_v_t_40 +(12 7) routing sp4_h_r_5 sp4_v_t_40 +(12 7) routing sp4_v_b_2 sp4_v_t_40 +(12 8) routing sp4_h_l_40 sp4_h_r_8 +(12 8) routing sp4_v_b_2 sp4_h_r_8 +(12 8) routing sp4_v_b_8 sp4_h_r_8 +(12 8) routing sp4_v_t_45 sp4_h_r_8 +(12 9) routing sp4_h_l_39 sp4_v_b_8 +(12 9) routing sp4_h_l_45 sp4_v_b_8 +(12 9) routing sp4_h_r_8 sp4_v_b_8 +(12 9) routing sp4_v_t_40 sp4_v_b_8 +(13 0) routing sp4_h_l_39 sp4_v_b_2 +(13 0) routing sp4_h_l_45 sp4_v_b_2 +(13 0) routing sp4_v_t_39 sp4_v_b_2 +(13 0) routing sp4_v_t_43 sp4_v_b_2 +(13 1) routing sp4_h_l_43 sp4_h_r_2 +(13 1) routing sp4_h_l_46 sp4_h_r_2 +(13 1) routing sp4_v_b_8 sp4_h_r_2 +(13 1) routing sp4_v_t_44 sp4_h_r_2 +(13 10) routing sp4_h_r_2 sp4_v_t_45 +(13 10) routing sp4_h_r_8 sp4_v_t_45 +(13 10) routing sp4_v_b_0 sp4_v_t_45 +(13 10) routing sp4_v_b_8 sp4_v_t_45 +(13 11) routing sp4_h_r_0 sp4_h_l_45 +(13 11) routing sp4_v_b_3 sp4_h_l_45 +(13 11) routing sp4_v_t_39 sp4_h_l_45 +(13 12) routing sp4_h_l_40 sp4_v_b_11 +(13 12) routing sp4_h_l_46 sp4_v_b_11 +(13 12) routing sp4_v_t_38 sp4_v_b_11 +(13 12) routing sp4_v_t_46 sp4_v_b_11 +(13 13) routing sp4_h_l_45 sp4_h_r_11 +(13 13) routing sp4_v_b_5 sp4_h_r_11 +(13 13) routing sp4_v_t_43 sp4_h_r_11 +(13 14) routing sp4_h_r_11 sp4_v_t_46 +(13 14) routing sp4_h_r_5 sp4_v_t_46 +(13 14) routing sp4_v_b_11 sp4_v_t_46 +(13 14) routing sp4_v_b_3 sp4_v_t_46 +(13 15) routing sp4_h_r_8 sp4_h_l_46 +(13 15) routing sp4_v_b_6 sp4_h_l_46 +(13 15) routing sp4_v_t_40 sp4_h_l_46 +(13 2) routing sp4_h_r_2 sp4_v_t_39 +(13 2) routing sp4_h_r_8 sp4_v_t_39 +(13 2) routing sp4_v_b_2 sp4_v_t_39 +(13 2) routing sp4_v_b_6 sp4_v_t_39 +(13 3) routing sp4_h_r_6 sp4_h_l_39 +(13 3) routing sp4_v_b_9 sp4_h_l_39 +(13 3) routing sp4_v_t_45 sp4_h_l_39 +(13 4) routing sp4_h_l_40 sp4_v_b_5 +(13 4) routing sp4_h_l_46 sp4_v_b_5 +(13 4) routing sp4_v_t_40 sp4_v_b_5 +(13 4) routing sp4_v_t_44 sp4_v_b_5 +(13 5) routing sp4_h_l_44 sp4_h_r_5 +(13 5) routing sp4_v_b_11 sp4_h_r_5 +(13 5) routing sp4_v_t_37 sp4_h_r_5 +(13 6) routing sp4_h_r_11 sp4_v_t_40 +(13 6) routing sp4_h_r_5 sp4_v_t_40 +(13 6) routing sp4_v_b_5 sp4_v_t_40 +(13 6) routing sp4_v_b_9 sp4_v_t_40 +(13 7) routing sp4_h_r_2 sp4_h_l_40 +(13 7) routing sp4_h_r_9 sp4_h_l_40 +(13 7) routing sp4_v_b_0 sp4_h_l_40 +(13 7) routing sp4_v_t_46 sp4_h_l_40 +(13 8) routing sp4_h_l_39 sp4_v_b_8 +(13 8) routing sp4_h_l_45 sp4_v_b_8 +(13 8) routing sp4_v_t_37 sp4_v_b_8 +(13 8) routing sp4_v_t_45 sp4_v_b_8 +(13 9) routing sp4_h_l_37 sp4_h_r_8 +(13 9) routing sp4_h_l_40 sp4_h_r_8 +(13 9) routing sp4_v_b_2 sp4_h_r_8 +(13 9) routing sp4_v_t_38 sp4_h_r_8 +(14 0) routing bnr_op_0 lc_trk_g0_0 +(14 0) routing lft_op_0 lc_trk_g0_0 +(14 0) routing sp12_h_r_0 lc_trk_g0_0 +(14 0) routing sp4_h_r_16 lc_trk_g0_0 +(14 0) routing sp4_h_r_8 lc_trk_g0_0 +(14 0) routing sp4_v_b_0 lc_trk_g0_0 +(14 0) routing sp4_v_b_8 lc_trk_g0_0 +(14 1) routing bnr_op_0 lc_trk_g0_0 +(14 1) routing sp12_h_r_0 lc_trk_g0_0 +(14 1) routing sp12_h_r_16 lc_trk_g0_0 +(14 1) routing sp4_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_h_r_16 lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 +(14 1) routing sp4_v_b_8 lc_trk_g0_0 +(14 10) routing bnl_op_4 lc_trk_g2_4 +(14 10) routing rgt_op_4 lc_trk_g2_4 +(14 10) routing sp12_v_t_3 lc_trk_g2_4 +(14 10) routing sp4_h_l_33 lc_trk_g2_4 +(14 10) routing sp4_h_r_36 lc_trk_g2_4 +(14 10) routing sp4_v_b_36 lc_trk_g2_4 +(14 10) routing sp4_v_t_17 lc_trk_g2_4 +(14 11) routing bnl_op_4 lc_trk_g2_4 +(14 11) routing sp12_v_t_19 lc_trk_g2_4 +(14 11) routing sp12_v_t_3 lc_trk_g2_4 +(14 11) routing sp4_h_l_17 lc_trk_g2_4 +(14 11) routing sp4_h_l_33 lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 +(14 11) routing sp4_v_b_36 lc_trk_g2_4 +(14 11) routing tnl_op_4 lc_trk_g2_4 +(14 12) routing bnl_op_0 lc_trk_g3_0 +(14 12) routing rgt_op_0 lc_trk_g3_0 +(14 12) routing sp12_v_b_0 lc_trk_g3_0 +(14 12) routing sp4_h_r_32 lc_trk_g3_0 +(14 12) routing sp4_h_r_40 lc_trk_g3_0 +(14 12) routing sp4_v_b_32 lc_trk_g3_0 +(14 12) routing sp4_v_t_13 lc_trk_g3_0 +(14 13) routing bnl_op_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_16 lc_trk_g3_0 +(14 13) routing sp4_h_l_13 lc_trk_g3_0 +(14 13) routing sp4_h_r_40 lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 +(14 13) routing sp4_v_b_32 lc_trk_g3_0 +(14 13) routing tnl_op_0 lc_trk_g3_0 +(14 14) routing bnl_op_4 lc_trk_g3_4 +(14 14) routing sp12_v_t_3 lc_trk_g3_4 +(14 14) routing sp4_h_l_33 lc_trk_g3_4 +(14 14) routing sp4_h_r_36 lc_trk_g3_4 +(14 14) routing sp4_v_b_36 lc_trk_g3_4 +(14 14) routing sp4_v_t_17 lc_trk_g3_4 +(14 15) routing bnl_op_4 lc_trk_g3_4 +(14 15) routing sp12_v_t_19 lc_trk_g3_4 +(14 15) routing sp12_v_t_3 lc_trk_g3_4 +(14 15) routing sp4_h_l_17 lc_trk_g3_4 +(14 15) routing sp4_h_l_33 lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 +(14 15) routing sp4_v_b_36 lc_trk_g3_4 +(14 15) routing tnl_op_4 lc_trk_g3_4 +(14 2) routing lft_op_4 lc_trk_g0_4 +(14 2) routing sp12_h_r_4 lc_trk_g0_4 +(14 2) routing sp4_h_l_9 lc_trk_g0_4 +(14 2) routing sp4_h_r_12 lc_trk_g0_4 +(14 2) routing sp4_v_b_4 lc_trk_g0_4 +(14 2) routing sp4_v_t_1 lc_trk_g0_4 +(14 3) routing sp12_h_r_20 lc_trk_g0_4 +(14 3) routing sp12_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_h_l_9 lc_trk_g0_4 +(14 3) routing sp4_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 +(14 3) routing sp4_v_t_1 lc_trk_g0_4 +(14 4) routing lft_op_0 lc_trk_g1_0 +(14 4) routing sp12_h_r_0 lc_trk_g1_0 +(14 4) routing sp4_h_r_16 lc_trk_g1_0 +(14 4) routing sp4_h_r_8 lc_trk_g1_0 +(14 4) routing sp4_v_b_0 lc_trk_g1_0 +(14 4) routing sp4_v_b_8 lc_trk_g1_0 +(14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp12_h_r_16 lc_trk_g1_0 +(14 5) routing sp4_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_r_16 lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 +(14 5) routing sp4_v_b_8 lc_trk_g1_0 +(14 6) routing bnr_op_4 lc_trk_g1_4 +(14 6) routing lft_op_4 lc_trk_g1_4 +(14 6) routing sp12_h_r_4 lc_trk_g1_4 +(14 6) routing sp4_h_l_9 lc_trk_g1_4 +(14 6) routing sp4_h_r_12 lc_trk_g1_4 +(14 6) routing sp4_v_b_4 lc_trk_g1_4 +(14 6) routing sp4_v_t_1 lc_trk_g1_4 +(14 7) routing bnr_op_4 lc_trk_g1_4 +(14 7) routing sp12_h_r_20 lc_trk_g1_4 +(14 7) routing sp12_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_h_l_9 lc_trk_g1_4 +(14 7) routing sp4_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 +(14 7) routing sp4_v_t_1 lc_trk_g1_4 +(14 8) routing bnl_op_0 lc_trk_g2_0 +(14 8) routing rgt_op_0 lc_trk_g2_0 +(14 8) routing sp12_v_b_0 lc_trk_g2_0 +(14 8) routing sp4_h_r_32 lc_trk_g2_0 +(14 8) routing sp4_h_r_40 lc_trk_g2_0 +(14 8) routing sp4_v_b_32 lc_trk_g2_0 +(14 8) routing sp4_v_t_13 lc_trk_g2_0 +(14 9) routing bnl_op_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_16 lc_trk_g2_0 +(14 9) routing sp4_h_l_13 lc_trk_g2_0 +(14 9) routing sp4_h_r_40 lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 +(14 9) routing sp4_v_b_32 lc_trk_g2_0 +(14 9) routing tnl_op_0 lc_trk_g2_0 +(15 0) routing lft_op_1 lc_trk_g0_1 +(15 0) routing sp12_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_17 lc_trk_g0_1 +(15 0) routing sp4_h_r_9 lc_trk_g0_1 +(15 0) routing sp4_v_t_4 lc_trk_g0_1 +(15 1) routing lft_op_0 lc_trk_g0_0 +(15 1) routing sp12_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_16 lc_trk_g0_0 +(15 1) routing sp4_h_r_8 lc_trk_g0_0 +(15 1) routing sp4_v_b_16 lc_trk_g0_0 +(15 10) routing sp12_v_b_5 lc_trk_g2_5 +(15 10) routing sp4_h_l_24 lc_trk_g2_5 +(15 10) routing sp4_h_r_29 lc_trk_g2_5 +(15 10) routing sp4_h_r_45 lc_trk_g2_5 +(15 10) routing sp4_v_b_45 lc_trk_g2_5 +(15 10) routing tnl_op_5 lc_trk_g2_5 +(15 10) routing tnr_op_5 lc_trk_g2_5 +(15 11) routing rgt_op_4 lc_trk_g2_4 +(15 11) routing sp12_v_t_3 lc_trk_g2_4 +(15 11) routing sp4_h_l_17 lc_trk_g2_4 +(15 11) routing sp4_h_l_33 lc_trk_g2_4 +(15 11) routing sp4_h_r_36 lc_trk_g2_4 +(15 11) routing sp4_v_t_33 lc_trk_g2_4 +(15 11) routing tnl_op_4 lc_trk_g2_4 +(15 11) routing tnr_op_4 lc_trk_g2_4 +(15 12) routing rgt_op_1 lc_trk_g3_1 +(15 12) routing sp12_v_b_1 lc_trk_g3_1 +(15 12) routing sp4_h_l_12 lc_trk_g3_1 +(15 12) routing sp4_h_l_20 lc_trk_g3_1 +(15 12) routing sp4_h_l_28 lc_trk_g3_1 +(15 12) routing sp4_v_b_41 lc_trk_g3_1 +(15 12) routing tnl_op_1 lc_trk_g3_1 +(15 13) routing rgt_op_0 lc_trk_g3_0 +(15 13) routing sp12_v_b_0 lc_trk_g3_0 +(15 13) routing sp4_h_l_13 lc_trk_g3_0 +(15 13) routing sp4_h_r_32 lc_trk_g3_0 +(15 13) routing sp4_h_r_40 lc_trk_g3_0 +(15 13) routing sp4_v_t_29 lc_trk_g3_0 +(15 13) routing tnl_op_0 lc_trk_g3_0 +(15 13) routing tnr_op_0 lc_trk_g3_0 +(15 14) routing rgt_op_5 lc_trk_g3_5 +(15 14) routing sp12_v_b_5 lc_trk_g3_5 +(15 14) routing sp4_h_l_24 lc_trk_g3_5 +(15 14) routing sp4_h_r_29 lc_trk_g3_5 +(15 14) routing sp4_h_r_45 lc_trk_g3_5 +(15 14) routing sp4_v_b_45 lc_trk_g3_5 +(15 14) routing tnr_op_5 lc_trk_g3_5 +(15 15) routing sp12_v_t_3 lc_trk_g3_4 +(15 15) routing sp4_h_l_17 lc_trk_g3_4 +(15 15) routing sp4_h_l_33 lc_trk_g3_4 +(15 15) routing sp4_h_r_36 lc_trk_g3_4 +(15 15) routing sp4_v_t_33 lc_trk_g3_4 +(15 15) routing tnl_op_4 lc_trk_g3_4 +(15 15) routing tnr_op_4 lc_trk_g3_4 +(15 2) routing lft_op_5 lc_trk_g0_5 +(15 2) routing sp12_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_h_l_0 lc_trk_g0_5 +(15 2) routing sp4_h_r_21 lc_trk_g0_5 +(15 2) routing sp4_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_v_t_8 lc_trk_g0_5 +(15 3) routing lft_op_4 lc_trk_g0_4 +(15 3) routing sp12_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_h_l_9 lc_trk_g0_4 +(15 3) routing sp4_h_r_12 lc_trk_g0_4 +(15 3) routing sp4_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_v_b_20 lc_trk_g0_4 +(15 4) routing sp12_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_17 lc_trk_g1_1 +(15 4) routing sp4_h_r_9 lc_trk_g1_1 +(15 4) routing sp4_v_t_4 lc_trk_g1_1 +(15 5) routing lft_op_0 lc_trk_g1_0 +(15 5) routing sp12_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_16 lc_trk_g1_0 +(15 5) routing sp4_h_r_8 lc_trk_g1_0 +(15 5) routing sp4_v_b_16 lc_trk_g1_0 +(15 6) routing lft_op_5 lc_trk_g1_5 +(15 6) routing sp12_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_h_l_0 lc_trk_g1_5 +(15 6) routing sp4_h_r_21 lc_trk_g1_5 +(15 6) routing sp4_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_v_t_8 lc_trk_g1_5 +(15 7) routing lft_op_4 lc_trk_g1_4 +(15 7) routing sp12_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_h_l_9 lc_trk_g1_4 +(15 7) routing sp4_h_r_12 lc_trk_g1_4 +(15 7) routing sp4_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_v_b_20 lc_trk_g1_4 +(15 8) routing rgt_op_1 lc_trk_g2_1 +(15 8) routing sp12_v_b_1 lc_trk_g2_1 +(15 8) routing sp4_h_l_12 lc_trk_g2_1 +(15 8) routing sp4_h_l_20 lc_trk_g2_1 +(15 8) routing sp4_h_l_28 lc_trk_g2_1 +(15 8) routing sp4_v_b_41 lc_trk_g2_1 +(15 8) routing tnl_op_1 lc_trk_g2_1 +(15 9) routing rgt_op_0 lc_trk_g2_0 +(15 9) routing sp12_v_b_0 lc_trk_g2_0 +(15 9) routing sp4_h_l_13 lc_trk_g2_0 +(15 9) routing sp4_h_r_32 lc_trk_g2_0 +(15 9) routing sp4_h_r_40 lc_trk_g2_0 +(15 9) routing sp4_v_t_29 lc_trk_g2_0 +(15 9) routing tnl_op_0 lc_trk_g2_0 +(15 9) routing tnr_op_0 lc_trk_g2_0 +(16 0) routing sp12_h_l_14 lc_trk_g0_1 +(16 0) routing sp12_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_h_r_1 lc_trk_g0_1 +(16 0) routing sp4_h_r_17 lc_trk_g0_1 +(16 0) routing sp4_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_v_b_1 lc_trk_g0_1 +(16 0) routing sp4_v_b_9 lc_trk_g0_1 +(16 0) routing sp4_v_t_4 lc_trk_g0_1 +(16 1) routing sp12_h_r_16 lc_trk_g0_0 +(16 1) routing sp12_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_h_r_0 lc_trk_g0_0 +(16 1) routing sp4_h_r_16 lc_trk_g0_0 +(16 1) routing sp4_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_v_b_0 lc_trk_g0_0 +(16 1) routing sp4_v_b_16 lc_trk_g0_0 +(16 1) routing sp4_v_b_8 lc_trk_g0_0 +(16 10) routing sp12_v_b_13 lc_trk_g2_5 +(16 10) routing sp12_v_t_18 lc_trk_g2_5 +(16 10) routing sp4_h_l_24 lc_trk_g2_5 +(16 10) routing sp4_h_r_29 lc_trk_g2_5 +(16 10) routing sp4_h_r_45 lc_trk_g2_5 +(16 10) routing sp4_v_b_37 lc_trk_g2_5 +(16 10) routing sp4_v_b_45 lc_trk_g2_5 +(16 10) routing sp4_v_t_16 lc_trk_g2_5 +(16 11) routing sp12_v_b_12 lc_trk_g2_4 +(16 11) routing sp12_v_t_19 lc_trk_g2_4 +(16 11) routing sp4_h_l_17 lc_trk_g2_4 +(16 11) routing sp4_h_l_33 lc_trk_g2_4 +(16 11) routing sp4_h_r_36 lc_trk_g2_4 +(16 11) routing sp4_v_b_36 lc_trk_g2_4 +(16 11) routing sp4_v_t_17 lc_trk_g2_4 +(16 11) routing sp4_v_t_33 lc_trk_g2_4 +(16 12) routing sp12_v_b_9 lc_trk_g3_1 +(16 12) routing sp12_v_t_14 lc_trk_g3_1 +(16 12) routing sp4_h_l_12 lc_trk_g3_1 +(16 12) routing sp4_h_l_20 lc_trk_g3_1 +(16 12) routing sp4_h_l_28 lc_trk_g3_1 +(16 12) routing sp4_v_b_25 lc_trk_g3_1 +(16 12) routing sp4_v_b_41 lc_trk_g3_1 +(16 12) routing sp4_v_t_20 lc_trk_g3_1 +(16 13) routing sp12_v_b_16 lc_trk_g3_0 +(16 13) routing sp12_v_b_8 lc_trk_g3_0 +(16 13) routing sp4_h_l_13 lc_trk_g3_0 +(16 13) routing sp4_h_r_32 lc_trk_g3_0 +(16 13) routing sp4_h_r_40 lc_trk_g3_0 +(16 13) routing sp4_v_b_32 lc_trk_g3_0 +(16 13) routing sp4_v_t_13 lc_trk_g3_0 +(16 13) routing sp4_v_t_29 lc_trk_g3_0 +(16 14) routing sp12_v_b_13 lc_trk_g3_5 +(16 14) routing sp12_v_t_18 lc_trk_g3_5 +(16 14) routing sp4_h_l_24 lc_trk_g3_5 +(16 14) routing sp4_h_r_29 lc_trk_g3_5 +(16 14) routing sp4_h_r_45 lc_trk_g3_5 +(16 14) routing sp4_v_b_37 lc_trk_g3_5 +(16 14) routing sp4_v_b_45 lc_trk_g3_5 +(16 14) routing sp4_v_t_16 lc_trk_g3_5 +(16 15) routing sp12_v_b_12 lc_trk_g3_4 +(16 15) routing sp12_v_t_19 lc_trk_g3_4 +(16 15) routing sp4_h_l_17 lc_trk_g3_4 +(16 15) routing sp4_h_l_33 lc_trk_g3_4 +(16 15) routing sp4_h_r_36 lc_trk_g3_4 +(16 15) routing sp4_v_b_36 lc_trk_g3_4 +(16 15) routing sp4_v_t_17 lc_trk_g3_4 +(16 15) routing sp4_v_t_33 lc_trk_g3_4 +(16 2) routing sp12_h_l_18 lc_trk_g0_5 +(16 2) routing sp12_h_r_13 lc_trk_g0_5 +(16 2) routing sp4_h_l_0 lc_trk_g0_5 +(16 2) routing sp4_h_r_21 lc_trk_g0_5 +(16 2) routing sp4_h_r_5 lc_trk_g0_5 +(16 2) routing sp4_v_b_5 lc_trk_g0_5 +(16 2) routing sp4_v_t_0 lc_trk_g0_5 +(16 2) routing sp4_v_t_8 lc_trk_g0_5 +(16 3) routing sp12_h_l_11 lc_trk_g0_4 +(16 3) routing sp12_h_r_20 lc_trk_g0_4 +(16 3) routing sp4_h_l_9 lc_trk_g0_4 +(16 3) routing sp4_h_r_12 lc_trk_g0_4 +(16 3) routing sp4_h_r_4 lc_trk_g0_4 +(16 3) routing sp4_v_b_20 lc_trk_g0_4 +(16 3) routing sp4_v_b_4 lc_trk_g0_4 +(16 3) routing sp4_v_t_1 lc_trk_g0_4 +(16 4) routing sp12_h_l_14 lc_trk_g1_1 +(16 4) routing sp12_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_h_r_1 lc_trk_g1_1 +(16 4) routing sp4_h_r_17 lc_trk_g1_1 +(16 4) routing sp4_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_v_b_1 lc_trk_g1_1 +(16 4) routing sp4_v_b_9 lc_trk_g1_1 +(16 4) routing sp4_v_t_4 lc_trk_g1_1 +(16 5) routing sp12_h_r_16 lc_trk_g1_0 +(16 5) routing sp12_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_h_r_0 lc_trk_g1_0 +(16 5) routing sp4_h_r_16 lc_trk_g1_0 +(16 5) routing sp4_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_v_b_0 lc_trk_g1_0 +(16 5) routing sp4_v_b_16 lc_trk_g1_0 +(16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 6) routing sp12_h_l_18 lc_trk_g1_5 +(16 6) routing sp12_h_r_13 lc_trk_g1_5 +(16 6) routing sp4_h_l_0 lc_trk_g1_5 +(16 6) routing sp4_h_r_21 lc_trk_g1_5 +(16 6) routing sp4_h_r_5 lc_trk_g1_5 +(16 6) routing sp4_v_b_5 lc_trk_g1_5 +(16 6) routing sp4_v_t_0 lc_trk_g1_5 +(16 6) routing sp4_v_t_8 lc_trk_g1_5 +(16 7) routing sp12_h_l_11 lc_trk_g1_4 +(16 7) routing sp12_h_r_20 lc_trk_g1_4 +(16 7) routing sp4_h_l_9 lc_trk_g1_4 +(16 7) routing sp4_h_r_12 lc_trk_g1_4 +(16 7) routing sp4_h_r_4 lc_trk_g1_4 +(16 7) routing sp4_v_b_20 lc_trk_g1_4 +(16 7) routing sp4_v_b_4 lc_trk_g1_4 +(16 7) routing sp4_v_t_1 lc_trk_g1_4 +(16 8) routing sp12_v_b_9 lc_trk_g2_1 +(16 8) routing sp12_v_t_14 lc_trk_g2_1 +(16 8) routing sp4_h_l_12 lc_trk_g2_1 +(16 8) routing sp4_h_l_20 lc_trk_g2_1 +(16 8) routing sp4_h_l_28 lc_trk_g2_1 +(16 8) routing sp4_v_b_25 lc_trk_g2_1 +(16 8) routing sp4_v_b_41 lc_trk_g2_1 +(16 8) routing sp4_v_t_20 lc_trk_g2_1 +(16 9) routing sp12_v_b_16 lc_trk_g2_0 +(16 9) routing sp12_v_b_8 lc_trk_g2_0 +(16 9) routing sp4_h_l_13 lc_trk_g2_0 +(16 9) routing sp4_h_r_32 lc_trk_g2_0 +(16 9) routing sp4_h_r_40 lc_trk_g2_0 +(16 9) routing sp4_v_b_32 lc_trk_g2_0 +(16 9) routing sp4_v_t_13 lc_trk_g2_0 +(16 9) routing sp4_v_t_29 lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_12 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 lc_trk_g0_1 +(18 0) routing lft_op_1 lc_trk_g0_1 +(18 0) routing sp12_h_r_1 lc_trk_g0_1 +(18 0) routing sp4_h_r_17 lc_trk_g0_1 +(18 0) routing sp4_h_r_9 lc_trk_g0_1 +(18 0) routing sp4_v_b_1 lc_trk_g0_1 +(18 0) routing sp4_v_b_9 lc_trk_g0_1 +(18 1) routing bnr_op_1 lc_trk_g0_1 +(18 1) routing sp12_h_l_14 lc_trk_g0_1 +(18 1) routing sp12_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 +(18 1) routing sp4_v_b_9 lc_trk_g0_1 +(18 10) routing bnl_op_5 lc_trk_g2_5 +(18 10) routing sp12_v_b_5 lc_trk_g2_5 +(18 10) routing sp4_h_l_24 lc_trk_g2_5 +(18 10) routing sp4_h_r_45 lc_trk_g2_5 +(18 10) routing sp4_v_b_37 lc_trk_g2_5 +(18 10) routing sp4_v_t_16 lc_trk_g2_5 +(18 11) routing bnl_op_5 lc_trk_g2_5 +(18 11) routing sp12_v_b_5 lc_trk_g2_5 +(18 11) routing sp12_v_t_18 lc_trk_g2_5 +(18 11) routing sp4_h_r_29 lc_trk_g2_5 +(18 11) routing sp4_h_r_45 lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 +(18 11) routing sp4_v_b_37 lc_trk_g2_5 +(18 11) routing tnl_op_5 lc_trk_g2_5 +(18 12) routing bnl_op_1 lc_trk_g3_1 +(18 12) routing rgt_op_1 lc_trk_g3_1 +(18 12) routing sp12_v_b_1 lc_trk_g3_1 +(18 12) routing sp4_h_l_20 lc_trk_g3_1 +(18 12) routing sp4_h_l_28 lc_trk_g3_1 +(18 12) routing sp4_v_b_25 lc_trk_g3_1 +(18 12) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing bnl_op_1 lc_trk_g3_1 +(18 13) routing sp12_v_b_1 lc_trk_g3_1 +(18 13) routing sp12_v_t_14 lc_trk_g3_1 +(18 13) routing sp4_h_l_12 lc_trk_g3_1 +(18 13) routing sp4_h_l_28 lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 +(18 13) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing tnl_op_1 lc_trk_g3_1 +(18 14) routing bnl_op_5 lc_trk_g3_5 +(18 14) routing rgt_op_5 lc_trk_g3_5 +(18 14) routing sp12_v_b_5 lc_trk_g3_5 +(18 14) routing sp4_h_l_24 lc_trk_g3_5 +(18 14) routing sp4_h_r_45 lc_trk_g3_5 +(18 14) routing sp4_v_b_37 lc_trk_g3_5 +(18 14) routing sp4_v_t_16 lc_trk_g3_5 +(18 15) routing bnl_op_5 lc_trk_g3_5 +(18 15) routing sp12_v_b_5 lc_trk_g3_5 +(18 15) routing sp12_v_t_18 lc_trk_g3_5 +(18 15) routing sp4_h_r_29 lc_trk_g3_5 +(18 15) routing sp4_h_r_45 lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 +(18 15) routing sp4_v_b_37 lc_trk_g3_5 +(18 2) routing bnr_op_5 lc_trk_g0_5 +(18 2) routing lft_op_5 lc_trk_g0_5 +(18 2) routing sp12_h_r_5 lc_trk_g0_5 +(18 2) routing sp4_h_l_0 lc_trk_g0_5 +(18 2) routing sp4_h_r_21 lc_trk_g0_5 +(18 2) routing sp4_v_b_5 lc_trk_g0_5 +(18 2) routing sp4_v_t_0 lc_trk_g0_5 +(18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_l_18 lc_trk_g0_5 +(18 3) routing sp12_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_h_r_21 lc_trk_g0_5 +(18 3) routing sp4_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 +(18 3) routing sp4_v_t_0 lc_trk_g0_5 +(18 4) routing bnr_op_1 lc_trk_g1_1 +(18 4) routing sp12_h_r_1 lc_trk_g1_1 +(18 4) routing sp4_h_r_17 lc_trk_g1_1 +(18 4) routing sp4_h_r_9 lc_trk_g1_1 +(18 4) routing sp4_v_b_1 lc_trk_g1_1 +(18 4) routing sp4_v_b_9 lc_trk_g1_1 +(18 5) routing bnr_op_1 lc_trk_g1_1 +(18 5) routing sp12_h_l_14 lc_trk_g1_1 +(18 5) routing sp12_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_17 lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 +(18 5) routing sp4_v_b_9 lc_trk_g1_1 +(18 6) routing bnr_op_5 lc_trk_g1_5 +(18 6) routing lft_op_5 lc_trk_g1_5 +(18 6) routing sp12_h_r_5 lc_trk_g1_5 +(18 6) routing sp4_h_l_0 lc_trk_g1_5 +(18 6) routing sp4_h_r_21 lc_trk_g1_5 +(18 6) routing sp4_v_b_5 lc_trk_g1_5 +(18 6) routing sp4_v_t_0 lc_trk_g1_5 +(18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_l_18 lc_trk_g1_5 +(18 7) routing sp12_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_h_r_21 lc_trk_g1_5 +(18 7) routing sp4_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 +(18 7) routing sp4_v_t_0 lc_trk_g1_5 +(18 8) routing bnl_op_1 lc_trk_g2_1 +(18 8) routing rgt_op_1 lc_trk_g2_1 +(18 8) routing sp12_v_b_1 lc_trk_g2_1 +(18 8) routing sp4_h_l_20 lc_trk_g2_1 +(18 8) routing sp4_h_l_28 lc_trk_g2_1 +(18 8) routing sp4_v_b_25 lc_trk_g2_1 +(18 8) routing sp4_v_t_20 lc_trk_g2_1 +(18 9) routing bnl_op_1 lc_trk_g2_1 +(18 9) routing sp12_v_b_1 lc_trk_g2_1 +(18 9) routing sp12_v_t_14 lc_trk_g2_1 +(18 9) routing sp4_h_l_12 lc_trk_g2_1 +(18 9) routing sp4_h_l_28 lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 +(18 9) routing sp4_v_t_20 lc_trk_g2_1 +(18 9) routing tnl_op_1 lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_t_0 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_b_23 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_r_6 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_r_4 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_r_21 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_r_23 +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_mult/lc_7/clk +(2 3) routing lc_trk_g0_0 wire_mult/lc_7/clk +(2 3) routing lc_trk_g1_1 wire_mult/lc_7/clk +(2 3) routing lc_trk_g2_0 wire_mult/lc_7/clk +(2 3) routing lc_trk_g3_1 wire_mult/lc_7/clk +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_r_18 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_l_6 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_l_9 +(21 0) routing bnr_op_3 lc_trk_g0_3 +(21 0) routing lft_op_3 lc_trk_g0_3 +(21 0) routing sp12_h_l_0 lc_trk_g0_3 +(21 0) routing sp4_h_l_6 lc_trk_g0_3 +(21 0) routing sp4_h_r_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_3 lc_trk_g0_3 +(21 1) routing bnr_op_3 lc_trk_g0_3 +(21 1) routing sp12_h_l_0 lc_trk_g0_3 +(21 1) routing sp12_h_r_19 lc_trk_g0_3 +(21 1) routing sp4_h_l_6 lc_trk_g0_3 +(21 1) routing sp4_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 +(21 1) routing sp4_v_b_11 lc_trk_g0_3 +(21 10) routing bnl_op_7 lc_trk_g2_7 +(21 10) routing rgt_op_7 lc_trk_g2_7 +(21 10) routing sp12_v_t_4 lc_trk_g2_7 +(21 10) routing sp4_h_l_34 lc_trk_g2_7 +(21 10) routing sp4_h_r_39 lc_trk_g2_7 +(21 10) routing sp4_v_t_18 lc_trk_g2_7 +(21 10) routing sp4_v_t_26 lc_trk_g2_7 +(21 11) routing bnl_op_7 lc_trk_g2_7 +(21 11) routing sp12_v_b_23 lc_trk_g2_7 +(21 11) routing sp12_v_t_4 lc_trk_g2_7 +(21 11) routing sp4_h_l_18 lc_trk_g2_7 +(21 11) routing sp4_h_l_34 lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 +(21 11) routing sp4_v_t_26 lc_trk_g2_7 +(21 11) routing tnl_op_7 lc_trk_g2_7 +(21 12) routing bnl_op_3 lc_trk_g3_3 +(21 12) routing rgt_op_3 lc_trk_g3_3 +(21 12) routing sp12_v_b_3 lc_trk_g3_3 +(21 12) routing sp4_h_l_22 lc_trk_g3_3 +(21 12) routing sp4_h_r_43 lc_trk_g3_3 +(21 12) routing sp4_v_b_27 lc_trk_g3_3 +(21 12) routing sp4_v_b_35 lc_trk_g3_3 +(21 13) routing bnl_op_3 lc_trk_g3_3 +(21 13) routing sp12_v_b_3 lc_trk_g3_3 +(21 13) routing sp12_v_t_16 lc_trk_g3_3 +(21 13) routing sp4_h_r_27 lc_trk_g3_3 +(21 13) routing sp4_h_r_43 lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 +(21 13) routing sp4_v_b_35 lc_trk_g3_3 +(21 13) routing tnl_op_3 lc_trk_g3_3 +(21 14) routing bnl_op_7 lc_trk_g3_7 +(21 14) routing rgt_op_7 lc_trk_g3_7 +(21 14) routing sp12_v_t_4 lc_trk_g3_7 +(21 14) routing sp4_h_l_34 lc_trk_g3_7 +(21 14) routing sp4_h_r_39 lc_trk_g3_7 +(21 14) routing sp4_v_t_18 lc_trk_g3_7 +(21 14) routing sp4_v_t_26 lc_trk_g3_7 +(21 15) routing bnl_op_7 lc_trk_g3_7 +(21 15) routing sp12_v_b_23 lc_trk_g3_7 +(21 15) routing sp12_v_t_4 lc_trk_g3_7 +(21 15) routing sp4_h_l_18 lc_trk_g3_7 +(21 15) routing sp4_h_l_34 lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 +(21 15) routing sp4_v_t_26 lc_trk_g3_7 +(21 2) routing bnr_op_7 lc_trk_g0_7 +(21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_l_4 lc_trk_g0_7 +(21 2) routing sp4_h_r_15 lc_trk_g0_7 +(21 2) routing sp4_h_r_23 lc_trk_g0_7 +(21 2) routing sp4_v_b_7 lc_trk_g0_7 +(21 2) routing sp4_v_t_2 lc_trk_g0_7 +(21 3) routing bnr_op_7 lc_trk_g0_7 +(21 3) routing sp12_h_l_4 lc_trk_g0_7 +(21 3) routing sp12_h_r_23 lc_trk_g0_7 +(21 3) routing sp4_h_r_23 lc_trk_g0_7 +(21 3) routing sp4_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 +(21 3) routing sp4_v_t_2 lc_trk_g0_7 +(21 4) routing bnr_op_3 lc_trk_g1_3 +(21 4) routing lft_op_3 lc_trk_g1_3 +(21 4) routing sp12_h_l_0 lc_trk_g1_3 +(21 4) routing sp4_h_l_6 lc_trk_g1_3 +(21 4) routing sp4_h_r_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_3 lc_trk_g1_3 +(21 5) routing bnr_op_3 lc_trk_g1_3 +(21 5) routing sp12_h_l_0 lc_trk_g1_3 +(21 5) routing sp12_h_r_19 lc_trk_g1_3 +(21 5) routing sp4_h_l_6 lc_trk_g1_3 +(21 5) routing sp4_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 +(21 5) routing sp4_v_b_11 lc_trk_g1_3 +(21 6) routing bnr_op_7 lc_trk_g1_7 +(21 6) routing sp12_h_l_4 lc_trk_g1_7 +(21 6) routing sp4_h_r_15 lc_trk_g1_7 +(21 6) routing sp4_h_r_23 lc_trk_g1_7 +(21 6) routing sp4_v_b_7 lc_trk_g1_7 +(21 6) routing sp4_v_t_2 lc_trk_g1_7 +(21 7) routing bnr_op_7 lc_trk_g1_7 +(21 7) routing sp12_h_l_4 lc_trk_g1_7 +(21 7) routing sp12_h_r_23 lc_trk_g1_7 +(21 7) routing sp4_h_r_23 lc_trk_g1_7 +(21 7) routing sp4_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 +(21 7) routing sp4_v_t_2 lc_trk_g1_7 +(21 8) routing bnl_op_3 lc_trk_g2_3 +(21 8) routing rgt_op_3 lc_trk_g2_3 +(21 8) routing sp12_v_b_3 lc_trk_g2_3 +(21 8) routing sp4_h_l_22 lc_trk_g2_3 +(21 8) routing sp4_h_r_43 lc_trk_g2_3 +(21 8) routing sp4_v_b_27 lc_trk_g2_3 +(21 8) routing sp4_v_b_35 lc_trk_g2_3 +(21 9) routing bnl_op_3 lc_trk_g2_3 +(21 9) routing sp12_v_b_3 lc_trk_g2_3 +(21 9) routing sp12_v_t_16 lc_trk_g2_3 +(21 9) routing sp4_h_r_27 lc_trk_g2_3 +(21 9) routing sp4_h_r_43 lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 +(21 9) routing sp4_v_b_35 lc_trk_g2_3 +(21 9) routing tnl_op_3 lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_8 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_8 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_8 lc_trk_g0_3 +(23 0) routing sp12_h_r_19 lc_trk_g0_3 +(23 0) routing sp4_h_l_6 lc_trk_g0_3 +(23 0) routing sp4_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_3 lc_trk_g0_3 +(23 0) routing sp4_v_b_11 lc_trk_g0_3 +(23 0) routing sp4_v_b_19 lc_trk_g0_3 +(23 0) routing sp4_v_b_3 lc_trk_g0_3 +(23 1) routing sp12_h_l_9 lc_trk_g0_2 +(23 1) routing sp12_h_r_18 lc_trk_g0_2 +(23 1) routing sp4_h_r_10 lc_trk_g0_2 +(23 1) routing sp4_h_r_18 lc_trk_g0_2 +(23 1) routing sp4_h_r_2 lc_trk_g0_2 +(23 1) routing sp4_v_b_10 lc_trk_g0_2 +(23 1) routing sp4_v_b_18 lc_trk_g0_2 +(23 1) routing sp4_v_b_2 lc_trk_g0_2 +(23 10) routing sp12_v_b_23 lc_trk_g2_7 +(23 10) routing sp12_v_t_12 lc_trk_g2_7 +(23 10) routing sp4_h_l_18 lc_trk_g2_7 +(23 10) routing sp4_h_l_34 lc_trk_g2_7 +(23 10) routing sp4_h_r_39 lc_trk_g2_7 +(23 10) routing sp4_v_b_47 lc_trk_g2_7 +(23 10) routing sp4_v_t_18 lc_trk_g2_7 +(23 10) routing sp4_v_t_26 lc_trk_g2_7 +(23 11) routing sp12_v_b_14 lc_trk_g2_6 +(23 11) routing sp12_v_b_22 lc_trk_g2_6 +(23 11) routing sp4_h_l_27 lc_trk_g2_6 +(23 11) routing sp4_h_r_30 lc_trk_g2_6 +(23 11) routing sp4_h_r_46 lc_trk_g2_6 +(23 11) routing sp4_v_b_38 lc_trk_g2_6 +(23 11) routing sp4_v_t_19 lc_trk_g2_6 +(23 11) routing sp4_v_t_35 lc_trk_g2_6 +(23 12) routing sp12_v_t_16 lc_trk_g3_3 +(23 12) routing sp12_v_t_8 lc_trk_g3_3 +(23 12) routing sp4_h_l_22 lc_trk_g3_3 +(23 12) routing sp4_h_r_27 lc_trk_g3_3 +(23 12) routing sp4_h_r_43 lc_trk_g3_3 +(23 12) routing sp4_v_b_27 lc_trk_g3_3 +(23 12) routing sp4_v_b_35 lc_trk_g3_3 +(23 12) routing sp4_v_t_30 lc_trk_g3_3 +(23 13) routing sp12_v_b_18 lc_trk_g3_2 +(23 13) routing sp12_v_t_9 lc_trk_g3_2 +(23 13) routing sp4_h_l_15 lc_trk_g3_2 +(23 13) routing sp4_h_l_23 lc_trk_g3_2 +(23 13) routing sp4_h_r_42 lc_trk_g3_2 +(23 13) routing sp4_v_t_15 lc_trk_g3_2 +(23 13) routing sp4_v_t_23 lc_trk_g3_2 +(23 13) routing sp4_v_t_31 lc_trk_g3_2 +(23 14) routing sp12_v_b_23 lc_trk_g3_7 +(23 14) routing sp12_v_t_12 lc_trk_g3_7 +(23 14) routing sp4_h_l_18 lc_trk_g3_7 +(23 14) routing sp4_h_l_34 lc_trk_g3_7 +(23 14) routing sp4_h_r_39 lc_trk_g3_7 +(23 14) routing sp4_v_b_47 lc_trk_g3_7 +(23 14) routing sp4_v_t_18 lc_trk_g3_7 +(23 14) routing sp4_v_t_26 lc_trk_g3_7 +(23 15) routing sp12_v_b_14 lc_trk_g3_6 +(23 15) routing sp12_v_b_22 lc_trk_g3_6 +(23 15) routing sp4_h_l_27 lc_trk_g3_6 +(23 15) routing sp4_h_r_30 lc_trk_g3_6 +(23 15) routing sp4_h_r_46 lc_trk_g3_6 +(23 15) routing sp4_v_b_38 lc_trk_g3_6 +(23 15) routing sp4_v_t_19 lc_trk_g3_6 +(23 15) routing sp4_v_t_35 lc_trk_g3_6 +(23 2) routing sp12_h_r_15 lc_trk_g0_7 +(23 2) routing sp12_h_r_23 lc_trk_g0_7 +(23 2) routing sp4_h_r_15 lc_trk_g0_7 +(23 2) routing sp4_h_r_23 lc_trk_g0_7 +(23 2) routing sp4_h_r_7 lc_trk_g0_7 +(23 2) routing sp4_v_b_23 lc_trk_g0_7 +(23 2) routing sp4_v_b_7 lc_trk_g0_7 +(23 2) routing sp4_v_t_2 lc_trk_g0_7 +(23 3) routing sp12_h_l_13 lc_trk_g0_6 +(23 3) routing sp12_h_l_21 lc_trk_g0_6 +(23 3) routing sp4_h_l_3 lc_trk_g0_6 +(23 3) routing sp4_h_r_22 lc_trk_g0_6 +(23 3) routing sp4_h_r_6 lc_trk_g0_6 +(23 3) routing sp4_v_b_14 lc_trk_g0_6 +(23 3) routing sp4_v_b_6 lc_trk_g0_6 +(23 3) routing sp4_v_t_11 lc_trk_g0_6 +(23 4) routing sp12_h_l_8 lc_trk_g1_3 +(23 4) routing sp12_h_r_19 lc_trk_g1_3 +(23 4) routing sp4_h_l_6 lc_trk_g1_3 +(23 4) routing sp4_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_3 lc_trk_g1_3 +(23 4) routing sp4_v_b_11 lc_trk_g1_3 +(23 4) routing sp4_v_b_19 lc_trk_g1_3 +(23 4) routing sp4_v_b_3 lc_trk_g1_3 +(23 5) routing sp12_h_l_9 lc_trk_g1_2 +(23 5) routing sp12_h_r_18 lc_trk_g1_2 +(23 5) routing sp4_h_r_10 lc_trk_g1_2 +(23 5) routing sp4_h_r_18 lc_trk_g1_2 +(23 5) routing sp4_h_r_2 lc_trk_g1_2 +(23 5) routing sp4_v_b_10 lc_trk_g1_2 +(23 5) routing sp4_v_b_18 lc_trk_g1_2 +(23 5) routing sp4_v_b_2 lc_trk_g1_2 +(23 6) routing sp12_h_r_15 lc_trk_g1_7 +(23 6) routing sp12_h_r_23 lc_trk_g1_7 +(23 6) routing sp4_h_r_15 lc_trk_g1_7 +(23 6) routing sp4_h_r_23 lc_trk_g1_7 +(23 6) routing sp4_h_r_7 lc_trk_g1_7 +(23 6) routing sp4_v_b_23 lc_trk_g1_7 +(23 6) routing sp4_v_b_7 lc_trk_g1_7 +(23 6) routing sp4_v_t_2 lc_trk_g1_7 +(23 7) routing sp12_h_l_13 lc_trk_g1_6 +(23 7) routing sp12_h_l_21 lc_trk_g1_6 +(23 7) routing sp4_h_l_3 lc_trk_g1_6 +(23 7) routing sp4_h_r_22 lc_trk_g1_6 +(23 7) routing sp4_h_r_6 lc_trk_g1_6 +(23 7) routing sp4_v_b_14 lc_trk_g1_6 +(23 7) routing sp4_v_b_6 lc_trk_g1_6 +(23 7) routing sp4_v_t_11 lc_trk_g1_6 +(23 8) routing sp12_v_t_16 lc_trk_g2_3 +(23 8) routing sp12_v_t_8 lc_trk_g2_3 +(23 8) routing sp4_h_l_22 lc_trk_g2_3 +(23 8) routing sp4_h_r_27 lc_trk_g2_3 +(23 8) routing sp4_h_r_43 lc_trk_g2_3 +(23 8) routing sp4_v_b_27 lc_trk_g2_3 +(23 8) routing sp4_v_b_35 lc_trk_g2_3 +(23 8) routing sp4_v_t_30 lc_trk_g2_3 +(23 9) routing sp12_v_b_18 lc_trk_g2_2 +(23 9) routing sp12_v_t_9 lc_trk_g2_2 +(23 9) routing sp4_h_l_15 lc_trk_g2_2 +(23 9) routing sp4_h_l_23 lc_trk_g2_2 +(23 9) routing sp4_h_r_42 lc_trk_g2_2 +(23 9) routing sp4_v_t_15 lc_trk_g2_2 +(23 9) routing sp4_v_t_23 lc_trk_g2_2 +(23 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 0) routing lft_op_3 lc_trk_g0_3 +(24 0) routing sp12_h_l_0 lc_trk_g0_3 +(24 0) routing sp4_h_l_6 lc_trk_g0_3 +(24 0) routing sp4_h_r_11 lc_trk_g0_3 +(24 0) routing sp4_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_v_b_19 lc_trk_g0_3 +(24 1) routing lft_op_2 lc_trk_g0_2 +(24 1) routing sp12_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_h_r_10 lc_trk_g0_2 +(24 1) routing sp4_h_r_18 lc_trk_g0_2 +(24 1) routing sp4_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_v_b_18 lc_trk_g0_2 +(24 10) routing rgt_op_7 lc_trk_g2_7 +(24 10) routing sp12_v_t_4 lc_trk_g2_7 +(24 10) routing sp4_h_l_18 lc_trk_g2_7 +(24 10) routing sp4_h_l_34 lc_trk_g2_7 +(24 10) routing sp4_h_r_39 lc_trk_g2_7 +(24 10) routing sp4_v_b_47 lc_trk_g2_7 +(24 10) routing tnl_op_7 lc_trk_g2_7 +(24 10) routing tnr_op_7 lc_trk_g2_7 +(24 11) routing sp12_v_t_5 lc_trk_g2_6 +(24 11) routing sp4_h_l_27 lc_trk_g2_6 +(24 11) routing sp4_h_r_30 lc_trk_g2_6 +(24 11) routing sp4_h_r_46 lc_trk_g2_6 +(24 11) routing sp4_v_t_35 lc_trk_g2_6 +(24 11) routing tnr_op_6 lc_trk_g2_6 +(24 12) routing rgt_op_3 lc_trk_g3_3 +(24 12) routing sp12_v_b_3 lc_trk_g3_3 +(24 12) routing sp4_h_l_22 lc_trk_g3_3 +(24 12) routing sp4_h_r_27 lc_trk_g3_3 +(24 12) routing sp4_h_r_43 lc_trk_g3_3 +(24 12) routing sp4_v_t_30 lc_trk_g3_3 +(24 12) routing tnl_op_3 lc_trk_g3_3 +(24 12) routing tnr_op_3 lc_trk_g3_3 +(24 13) routing rgt_op_2 lc_trk_g3_2 +(24 13) routing sp12_v_b_2 lc_trk_g3_2 +(24 13) routing sp4_h_l_15 lc_trk_g3_2 +(24 13) routing sp4_h_l_23 lc_trk_g3_2 +(24 13) routing sp4_h_r_42 lc_trk_g3_2 +(24 13) routing sp4_v_t_31 lc_trk_g3_2 +(24 13) routing tnl_op_2 lc_trk_g3_2 +(24 13) routing tnr_op_2 lc_trk_g3_2 +(24 14) routing rgt_op_7 lc_trk_g3_7 +(24 14) routing sp12_v_t_4 lc_trk_g3_7 +(24 14) routing sp4_h_l_18 lc_trk_g3_7 +(24 14) routing sp4_h_l_34 lc_trk_g3_7 +(24 14) routing sp4_h_r_39 lc_trk_g3_7 +(24 14) routing sp4_v_b_47 lc_trk_g3_7 +(24 14) routing tnr_op_7 lc_trk_g3_7 +(24 15) routing rgt_op_6 lc_trk_g3_6 +(24 15) routing sp12_v_t_5 lc_trk_g3_6 +(24 15) routing sp4_h_l_27 lc_trk_g3_6 +(24 15) routing sp4_h_r_30 lc_trk_g3_6 +(24 15) routing sp4_h_r_46 lc_trk_g3_6 +(24 15) routing sp4_v_t_35 lc_trk_g3_6 +(24 15) routing tnl_op_6 lc_trk_g3_6 +(24 15) routing tnr_op_6 lc_trk_g3_6 +(24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_l_4 lc_trk_g0_7 +(24 2) routing sp4_h_r_15 lc_trk_g0_7 +(24 2) routing sp4_h_r_23 lc_trk_g0_7 +(24 2) routing sp4_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_v_b_23 lc_trk_g0_7 +(24 3) routing lft_op_6 lc_trk_g0_6 +(24 3) routing sp12_h_r_6 lc_trk_g0_6 +(24 3) routing sp4_h_l_3 lc_trk_g0_6 +(24 3) routing sp4_h_r_22 lc_trk_g0_6 +(24 3) routing sp4_h_r_6 lc_trk_g0_6 +(24 3) routing sp4_v_t_11 lc_trk_g0_6 +(24 4) routing lft_op_3 lc_trk_g1_3 +(24 4) routing sp12_h_l_0 lc_trk_g1_3 +(24 4) routing sp4_h_l_6 lc_trk_g1_3 +(24 4) routing sp4_h_r_11 lc_trk_g1_3 +(24 4) routing sp4_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_v_b_19 lc_trk_g1_3 +(24 5) routing lft_op_2 lc_trk_g1_2 +(24 5) routing sp12_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_h_r_10 lc_trk_g1_2 +(24 5) routing sp4_h_r_18 lc_trk_g1_2 +(24 5) routing sp4_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_v_b_18 lc_trk_g1_2 +(24 6) routing sp12_h_l_4 lc_trk_g1_7 +(24 6) routing sp4_h_r_15 lc_trk_g1_7 +(24 6) routing sp4_h_r_23 lc_trk_g1_7 +(24 6) routing sp4_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_v_b_23 lc_trk_g1_7 +(24 7) routing lft_op_6 lc_trk_g1_6 +(24 7) routing sp12_h_r_6 lc_trk_g1_6 +(24 7) routing sp4_h_l_3 lc_trk_g1_6 +(24 7) routing sp4_h_r_22 lc_trk_g1_6 +(24 7) routing sp4_h_r_6 lc_trk_g1_6 +(24 7) routing sp4_v_t_11 lc_trk_g1_6 +(24 8) routing rgt_op_3 lc_trk_g2_3 +(24 8) routing sp12_v_b_3 lc_trk_g2_3 +(24 8) routing sp4_h_l_22 lc_trk_g2_3 +(24 8) routing sp4_h_r_27 lc_trk_g2_3 +(24 8) routing sp4_h_r_43 lc_trk_g2_3 +(24 8) routing sp4_v_t_30 lc_trk_g2_3 +(24 8) routing tnl_op_3 lc_trk_g2_3 +(24 8) routing tnr_op_3 lc_trk_g2_3 +(24 9) routing rgt_op_2 lc_trk_g2_2 +(24 9) routing sp12_v_b_2 lc_trk_g2_2 +(24 9) routing sp4_h_l_15 lc_trk_g2_2 +(24 9) routing sp4_h_l_23 lc_trk_g2_2 +(24 9) routing sp4_h_r_42 lc_trk_g2_2 +(24 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 9) routing tnl_op_2 lc_trk_g2_2 +(24 9) routing tnr_op_2 lc_trk_g2_2 +(25 0) routing bnr_op_2 lc_trk_g0_2 +(25 0) routing lft_op_2 lc_trk_g0_2 +(25 0) routing sp12_h_r_2 lc_trk_g0_2 +(25 0) routing sp4_h_r_10 lc_trk_g0_2 +(25 0) routing sp4_h_r_18 lc_trk_g0_2 +(25 0) routing sp4_v_b_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_2 lc_trk_g0_2 +(25 1) routing bnr_op_2 lc_trk_g0_2 +(25 1) routing sp12_h_r_18 lc_trk_g0_2 +(25 1) routing sp12_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_h_r_18 lc_trk_g0_2 +(25 1) routing sp4_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 +(25 1) routing sp4_v_b_10 lc_trk_g0_2 +(25 10) routing bnl_op_6 lc_trk_g2_6 +(25 10) routing sp12_v_t_5 lc_trk_g2_6 +(25 10) routing sp4_h_l_27 lc_trk_g2_6 +(25 10) routing sp4_h_r_46 lc_trk_g2_6 +(25 10) routing sp4_v_b_38 lc_trk_g2_6 +(25 10) routing sp4_v_t_19 lc_trk_g2_6 +(25 11) routing bnl_op_6 lc_trk_g2_6 +(25 11) routing sp12_v_b_22 lc_trk_g2_6 +(25 11) routing sp12_v_t_5 lc_trk_g2_6 +(25 11) routing sp4_h_r_30 lc_trk_g2_6 +(25 11) routing sp4_h_r_46 lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 +(25 11) routing sp4_v_b_38 lc_trk_g2_6 +(25 12) routing bnl_op_2 lc_trk_g3_2 +(25 12) routing rgt_op_2 lc_trk_g3_2 +(25 12) routing sp12_v_b_2 lc_trk_g3_2 +(25 12) routing sp4_h_l_23 lc_trk_g3_2 +(25 12) routing sp4_h_r_42 lc_trk_g3_2 +(25 12) routing sp4_v_t_15 lc_trk_g3_2 +(25 12) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing bnl_op_2 lc_trk_g3_2 +(25 13) routing sp12_v_b_18 lc_trk_g3_2 +(25 13) routing sp12_v_b_2 lc_trk_g3_2 +(25 13) routing sp4_h_l_15 lc_trk_g3_2 +(25 13) routing sp4_h_r_42 lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 +(25 13) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing tnl_op_2 lc_trk_g3_2 +(25 14) routing bnl_op_6 lc_trk_g3_6 +(25 14) routing rgt_op_6 lc_trk_g3_6 +(25 14) routing sp12_v_t_5 lc_trk_g3_6 +(25 14) routing sp4_h_l_27 lc_trk_g3_6 +(25 14) routing sp4_h_r_46 lc_trk_g3_6 +(25 14) routing sp4_v_b_38 lc_trk_g3_6 +(25 14) routing sp4_v_t_19 lc_trk_g3_6 +(25 15) routing bnl_op_6 lc_trk_g3_6 +(25 15) routing sp12_v_b_22 lc_trk_g3_6 +(25 15) routing sp12_v_t_5 lc_trk_g3_6 +(25 15) routing sp4_h_r_30 lc_trk_g3_6 +(25 15) routing sp4_h_r_46 lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 +(25 15) routing sp4_v_b_38 lc_trk_g3_6 +(25 15) routing tnl_op_6 lc_trk_g3_6 +(25 2) routing bnr_op_6 lc_trk_g0_6 +(25 2) routing lft_op_6 lc_trk_g0_6 +(25 2) routing sp12_h_r_6 lc_trk_g0_6 +(25 2) routing sp4_h_l_3 lc_trk_g0_6 +(25 2) routing sp4_h_r_22 lc_trk_g0_6 +(25 2) routing sp4_v_b_14 lc_trk_g0_6 +(25 2) routing sp4_v_b_6 lc_trk_g0_6 +(25 3) routing bnr_op_6 lc_trk_g0_6 +(25 3) routing sp12_h_l_21 lc_trk_g0_6 +(25 3) routing sp12_h_r_6 lc_trk_g0_6 +(25 3) routing sp4_h_r_22 lc_trk_g0_6 +(25 3) routing sp4_h_r_6 lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 +(25 3) routing sp4_v_b_14 lc_trk_g0_6 +(25 4) routing bnr_op_2 lc_trk_g1_2 +(25 4) routing lft_op_2 lc_trk_g1_2 +(25 4) routing sp12_h_r_2 lc_trk_g1_2 +(25 4) routing sp4_h_r_10 lc_trk_g1_2 +(25 4) routing sp4_h_r_18 lc_trk_g1_2 +(25 4) routing sp4_v_b_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_2 lc_trk_g1_2 +(25 5) routing bnr_op_2 lc_trk_g1_2 +(25 5) routing sp12_h_r_18 lc_trk_g1_2 +(25 5) routing sp12_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_h_r_18 lc_trk_g1_2 +(25 5) routing sp4_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 +(25 5) routing sp4_v_b_10 lc_trk_g1_2 +(25 6) routing bnr_op_6 lc_trk_g1_6 +(25 6) routing lft_op_6 lc_trk_g1_6 +(25 6) routing sp12_h_r_6 lc_trk_g1_6 +(25 6) routing sp4_h_l_3 lc_trk_g1_6 +(25 6) routing sp4_h_r_22 lc_trk_g1_6 +(25 6) routing sp4_v_b_14 lc_trk_g1_6 +(25 6) routing sp4_v_b_6 lc_trk_g1_6 +(25 7) routing bnr_op_6 lc_trk_g1_6 +(25 7) routing sp12_h_l_21 lc_trk_g1_6 +(25 7) routing sp12_h_r_6 lc_trk_g1_6 +(25 7) routing sp4_h_r_22 lc_trk_g1_6 +(25 7) routing sp4_h_r_6 lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 +(25 7) routing sp4_v_b_14 lc_trk_g1_6 +(25 8) routing bnl_op_2 lc_trk_g2_2 +(25 8) routing rgt_op_2 lc_trk_g2_2 +(25 8) routing sp12_v_b_2 lc_trk_g2_2 +(25 8) routing sp4_h_l_23 lc_trk_g2_2 +(25 8) routing sp4_h_r_42 lc_trk_g2_2 +(25 8) routing sp4_v_t_15 lc_trk_g2_2 +(25 8) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing bnl_op_2 lc_trk_g2_2 +(25 9) routing sp12_v_b_18 lc_trk_g2_2 +(25 9) routing sp12_v_b_2 lc_trk_g2_2 +(25 9) routing sp4_h_l_15 lc_trk_g2_2 +(25 9) routing sp4_h_r_42 lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 +(25 9) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing tnl_op_2 lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(27 0) routing lc_trk_g1_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(27 4) routing lc_trk_g1_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(27 6) routing lc_trk_g1_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(27 8) routing lc_trk_g1_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(28 0) routing lc_trk_g2_1 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(28 4) routing lc_trk_g2_1 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(28 6) routing lc_trk_g2_0 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(28 8) routing lc_trk_g2_1 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(3 0) routing sp12_h_r_0 sp12_v_b_0 +(3 0) routing sp12_v_t_23 sp12_v_b_0 +(3 1) routing sp12_h_l_23 sp12_v_b_0 +(3 1) routing sp12_h_r_0 sp12_v_b_0 +(3 10) routing sp12_v_t_22 sp12_h_l_22 +(3 11) routing sp12_v_b_1 sp12_h_l_22 +(3 12) routing sp12_v_b_1 sp12_h_r_1 +(3 12) routing sp12_v_t_22 sp12_h_r_1 +(3 13) routing sp12_h_l_22 sp12_h_r_1 +(3 13) routing sp12_v_b_1 sp12_h_r_1 +(3 14) routing sp12_h_r_1 sp12_v_t_22 +(3 14) routing sp12_v_b_1 sp12_v_t_22 +(3 15) routing sp12_h_l_22 sp12_v_t_22 +(3 15) routing sp12_h_r_1 sp12_v_t_22 +(3 2) routing sp12_h_r_0 sp12_h_l_23 +(3 2) routing sp12_v_t_23 sp12_h_l_23 +(3 3) routing sp12_h_r_0 sp12_h_l_23 +(3 3) routing sp12_v_b_0 sp12_h_l_23 +(3 4) routing sp12_v_b_0 sp12_h_r_0 +(3 4) routing sp12_v_t_23 sp12_h_r_0 +(3 5) routing sp12_h_l_23 sp12_h_r_0 +(3 5) routing sp12_v_b_0 sp12_h_r_0 +(3 6) routing sp12_h_r_0 sp12_v_t_23 +(3 6) routing sp12_v_b_0 sp12_v_t_23 +(3 7) routing sp12_h_l_23 sp12_v_t_23 +(3 7) routing sp12_h_r_0 sp12_v_t_23 +(3 8) routing sp12_h_r_1 sp12_v_b_1 +(3 8) routing sp12_v_t_22 sp12_v_b_1 +(3 9) routing sp12_h_l_22 sp12_v_b_1 +(3 9) routing sp12_h_r_1 sp12_v_b_1 +(30 0) routing lc_trk_g0_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 sp4_v_b_0 +(4 0) routing sp4_h_l_43 sp4_v_b_0 +(4 0) routing sp4_v_t_37 sp4_v_b_0 +(4 0) routing sp4_v_t_41 sp4_v_b_0 +(4 1) routing sp4_v_b_6 sp4_h_r_0 +(4 1) routing sp4_v_t_42 sp4_h_r_0 +(4 10) routing sp4_h_r_0 sp4_v_t_43 +(4 10) routing sp4_h_r_6 sp4_v_t_43 +(4 10) routing sp4_v_b_10 sp4_v_t_43 +(4 10) routing sp4_v_b_6 sp4_v_t_43 +(4 11) routing sp4_h_r_10 sp4_h_l_43 +(4 11) routing sp4_h_r_3 sp4_h_l_43 +(4 11) routing sp4_v_b_1 sp4_h_l_43 +(4 11) routing sp4_v_t_37 sp4_h_l_43 +(4 12) routing sp4_h_l_38 sp4_v_b_9 +(4 12) routing sp4_h_l_44 sp4_v_b_9 +(4 12) routing sp4_v_t_36 sp4_v_b_9 +(4 12) routing sp4_v_t_44 sp4_v_b_9 +(4 13) routing sp4_v_b_3 sp4_h_r_9 +(4 13) routing sp4_v_t_41 sp4_h_r_9 +(4 14) routing sp4_h_r_3 sp4_v_t_44 +(4 14) routing sp4_h_r_9 sp4_v_t_44 +(4 14) routing sp4_v_b_1 sp4_v_t_44 +(4 14) routing sp4_v_b_9 sp4_v_t_44 +(4 15) routing sp4_h_r_6 sp4_h_l_44 +(4 15) routing sp4_v_b_4 sp4_h_l_44 +(4 15) routing sp4_v_t_38 sp4_h_l_44 +(4 2) routing sp4_h_r_0 sp4_v_t_37 +(4 2) routing sp4_h_r_6 sp4_v_t_37 +(4 2) routing sp4_v_b_0 sp4_v_t_37 +(4 2) routing sp4_v_b_4 sp4_v_t_37 +(4 3) routing sp4_h_r_4 sp4_h_l_37 +(4 3) routing sp4_v_b_7 sp4_h_l_37 +(4 3) routing sp4_v_t_43 sp4_h_l_37 +(4 4) routing sp4_h_l_38 sp4_v_b_3 +(4 4) routing sp4_h_l_44 sp4_v_b_3 +(4 4) routing sp4_v_t_38 sp4_v_b_3 +(4 4) routing sp4_v_t_42 sp4_v_b_3 +(4 5) routing sp4_h_l_37 sp4_h_r_3 +(4 5) routing sp4_v_b_9 sp4_h_r_3 +(4 5) routing sp4_v_t_47 sp4_h_r_3 +(4 6) routing sp4_h_r_3 sp4_v_t_38 +(4 6) routing sp4_h_r_9 sp4_v_t_38 +(4 6) routing sp4_v_b_3 sp4_v_t_38 +(4 6) routing sp4_v_b_7 sp4_v_t_38 +(4 7) routing sp4_h_r_0 sp4_h_l_38 +(4 7) routing sp4_v_b_10 sp4_h_l_38 +(4 7) routing sp4_v_t_44 sp4_h_l_38 +(4 8) routing sp4_h_l_37 sp4_v_b_6 +(4 8) routing sp4_h_l_43 sp4_v_b_6 +(4 8) routing sp4_v_t_43 sp4_v_b_6 +(4 8) routing sp4_v_t_47 sp4_v_b_6 +(4 9) routing sp4_h_l_38 sp4_h_r_6 +(4 9) routing sp4_v_b_0 sp4_h_r_6 +(4 9) routing sp4_v_t_36 sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_16 sp4_h_r_16 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_16 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_21 sp4_h_l_15 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_21 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_22 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_22 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_23 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_23 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_17 sp4_h_r_18 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_17 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_18 sp4_h_l_9 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_18 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_19 sp4_h_r_22 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_19 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_20 sp4_h_l_13 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_20 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_16 sp12_h_r_8 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_16 sp4_h_r_32 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_21 sp12_h_r_2 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_21 sp4_h_r_42 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_22 sp12_h_r_4 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_22 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_23 sp12_h_r_6 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_23 sp4_h_r_46 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_17 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_17 sp4_h_l_23 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_18 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_18 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_19 sp12_h_l_13 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_19 sp4_h_l_27 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_20 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_20 sp4_h_r_40 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_16 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_16 sp4_v_b_16 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_21 sp12_h_r_18 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_21 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_22 sp12_h_r_20 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_22 sp4_v_t_1 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_23 sp12_h_l_21 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_23 sp4_v_b_14 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_17 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_17 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_18 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_18 sp4_v_b_20 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_19 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_19 sp4_v_t_11 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_20 sp12_h_r_16 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_20 sp4_v_b_8 +(5 0) routing sp4_v_b_0 sp4_h_r_0 +(5 0) routing sp4_v_b_6 sp4_h_r_0 +(5 0) routing sp4_v_t_37 sp4_h_r_0 +(5 1) routing sp4_h_l_37 sp4_v_b_0 +(5 1) routing sp4_h_l_43 sp4_v_b_0 +(5 1) routing sp4_h_r_0 sp4_v_b_0 +(5 1) routing sp4_v_t_44 sp4_v_b_0 +(5 10) routing sp4_h_r_3 sp4_h_l_43 +(5 10) routing sp4_v_b_6 sp4_h_l_43 +(5 10) routing sp4_v_t_37 sp4_h_l_43 +(5 10) routing sp4_v_t_43 sp4_h_l_43 +(5 11) routing sp4_h_l_43 sp4_v_t_43 +(5 11) routing sp4_h_r_0 sp4_v_t_43 +(5 11) routing sp4_h_r_6 sp4_v_t_43 +(5 11) routing sp4_v_b_3 sp4_v_t_43 +(5 12) routing sp4_v_b_3 sp4_h_r_9 +(5 12) routing sp4_v_b_9 sp4_h_r_9 +(5 12) routing sp4_v_t_44 sp4_h_r_9 +(5 13) routing sp4_h_l_38 sp4_v_b_9 +(5 13) routing sp4_h_l_44 sp4_v_b_9 +(5 13) routing sp4_h_r_9 sp4_v_b_9 +(5 13) routing sp4_v_t_43 sp4_v_b_9 +(5 14) routing sp4_h_r_6 sp4_h_l_44 +(5 14) routing sp4_v_b_9 sp4_h_l_44 +(5 14) routing sp4_v_t_38 sp4_h_l_44 +(5 14) routing sp4_v_t_44 sp4_h_l_44 +(5 15) routing sp4_h_l_44 sp4_v_t_44 +(5 15) routing sp4_h_r_3 sp4_v_t_44 +(5 15) routing sp4_h_r_9 sp4_v_t_44 +(5 15) routing sp4_v_b_6 sp4_v_t_44 +(5 2) routing sp4_v_b_0 sp4_h_l_37 +(5 2) routing sp4_v_t_37 sp4_h_l_37 +(5 2) routing sp4_v_t_43 sp4_h_l_37 +(5 3) routing sp4_h_l_37 sp4_v_t_37 +(5 3) routing sp4_h_r_0 sp4_v_t_37 +(5 3) routing sp4_h_r_6 sp4_v_t_37 +(5 3) routing sp4_v_b_9 sp4_v_t_37 +(5 4) routing sp4_h_l_37 sp4_h_r_3 +(5 4) routing sp4_v_b_3 sp4_h_r_3 +(5 4) routing sp4_v_b_9 sp4_h_r_3 +(5 4) routing sp4_v_t_38 sp4_h_r_3 +(5 5) routing sp4_h_l_38 sp4_v_b_3 +(5 5) routing sp4_h_l_44 sp4_v_b_3 +(5 5) routing sp4_h_r_3 sp4_v_b_3 +(5 5) routing sp4_v_t_37 sp4_v_b_3 +(5 6) routing sp4_h_r_0 sp4_h_l_38 +(5 6) routing sp4_v_b_3 sp4_h_l_38 +(5 6) routing sp4_v_t_38 sp4_h_l_38 +(5 6) routing sp4_v_t_44 sp4_h_l_38 +(5 7) routing sp4_h_l_38 sp4_v_t_38 +(5 7) routing sp4_h_r_3 sp4_v_t_38 +(5 7) routing sp4_h_r_9 sp4_v_t_38 +(5 7) routing sp4_v_b_0 sp4_v_t_38 +(5 8) routing sp4_h_l_38 sp4_h_r_6 +(5 8) routing sp4_v_b_0 sp4_h_r_6 +(5 8) routing sp4_v_b_6 sp4_h_r_6 +(5 8) routing sp4_v_t_43 sp4_h_r_6 +(5 9) routing sp4_h_l_37 sp4_v_b_6 +(5 9) routing sp4_h_l_43 sp4_v_b_6 +(5 9) routing sp4_h_r_6 sp4_v_b_6 +(5 9) routing sp4_v_t_38 sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT2_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT2_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT2_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT2_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT2_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT2_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT2_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT2_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_16 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_16 sp4_v_b_32 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_21 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_21 sp4_v_t_15 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_22 sp4_v_t_33 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_22 sp4_v_t_17 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_23 sp4_v_t_35 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_23 sp4_v_t_19 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_17 sp12_v_b_2 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_17 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_18 sp12_v_t_3 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_18 sp4_v_b_36 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_19 sp12_v_t_5 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_19 sp4_v_b_38 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_20 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_20 sp4_v_t_13 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_16 sp12_v_b_16 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_16 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_21 sp12_v_t_9 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_21 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_22 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_22 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_23 sp12_v_b_14 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_23 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_17 sp12_v_b_18 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_17 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_18 sp12_v_t_19 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_18 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_19 sp12_v_b_22 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_19 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_20 sp12_v_b_8 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_20 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_16 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_16 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_21 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_21 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_22 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_22 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_23 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_23 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_17 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_17 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_18 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_18 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_19 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_19 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_20 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_20 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 sp4_v_b_0 +(6 0) routing sp4_h_r_7 sp4_v_b_0 +(6 0) routing sp4_v_t_41 sp4_v_b_0 +(6 0) routing sp4_v_t_44 sp4_v_b_0 +(6 1) routing sp4_v_b_0 sp4_h_r_0 +(6 1) routing sp4_v_b_6 sp4_h_r_0 +(6 10) routing sp4_h_l_36 sp4_v_t_43 +(6 10) routing sp4_h_r_0 sp4_v_t_43 +(6 10) routing sp4_v_b_10 sp4_v_t_43 +(6 10) routing sp4_v_b_3 sp4_v_t_43 +(6 11) routing sp4_h_r_10 sp4_h_l_43 +(6 11) routing sp4_h_r_6 sp4_h_l_43 +(6 11) routing sp4_v_t_37 sp4_h_l_43 +(6 11) routing sp4_v_t_43 sp4_h_l_43 +(6 12) routing sp4_h_l_38 sp4_v_b_9 +(6 12) routing sp4_h_r_4 sp4_v_b_9 +(6 12) routing sp4_v_t_36 sp4_v_b_9 +(6 12) routing sp4_v_t_43 sp4_v_b_9 +(6 13) routing sp4_h_l_44 sp4_h_r_9 +(6 13) routing sp4_v_b_3 sp4_h_r_9 +(6 13) routing sp4_v_b_9 sp4_h_r_9 +(6 14) routing sp4_h_l_41 sp4_v_t_44 +(6 14) routing sp4_h_r_3 sp4_v_t_44 +(6 14) routing sp4_v_b_1 sp4_v_t_44 +(6 14) routing sp4_v_b_6 sp4_v_t_44 +(6 15) routing sp4_v_t_38 sp4_h_l_44 +(6 15) routing sp4_v_t_44 sp4_h_l_44 +(6 2) routing sp4_h_l_42 sp4_v_t_37 +(6 2) routing sp4_h_r_6 sp4_v_t_37 +(6 2) routing sp4_v_b_4 sp4_v_t_37 +(6 2) routing sp4_v_b_9 sp4_v_t_37 +(6 3) routing sp4_h_r_0 sp4_h_l_37 +(6 3) routing sp4_h_r_4 sp4_h_l_37 +(6 3) routing sp4_v_t_37 sp4_h_l_37 +(6 3) routing sp4_v_t_43 sp4_h_l_37 +(6 4) routing sp4_h_l_44 sp4_v_b_3 +(6 4) routing sp4_h_r_10 sp4_v_b_3 +(6 4) routing sp4_v_t_37 sp4_v_b_3 +(6 4) routing sp4_v_t_42 sp4_v_b_3 +(6 5) routing sp4_h_l_38 sp4_h_r_3 +(6 5) routing sp4_v_b_3 sp4_h_r_3 +(6 5) routing sp4_v_b_9 sp4_h_r_3 +(6 6) routing sp4_h_l_47 sp4_v_t_38 +(6 6) routing sp4_h_r_9 sp4_v_t_38 +(6 6) routing sp4_v_b_0 sp4_v_t_38 +(6 6) routing sp4_v_b_7 sp4_v_t_38 +(6 7) routing sp4_v_t_38 sp4_h_l_38 +(6 7) routing sp4_v_t_44 sp4_h_l_38 +(6 8) routing sp4_h_l_37 sp4_v_b_6 +(6 8) routing sp4_h_r_1 sp4_v_b_6 +(6 8) routing sp4_v_t_38 sp4_v_b_6 +(6 8) routing sp4_v_t_47 sp4_v_b_6 +(6 9) routing sp4_v_b_0 sp4_h_r_6 +(6 9) routing sp4_v_b_6 sp4_h_r_6 +(7 0) MAC16 functional bit: MULT2_bram_cbit_1 +(7 1) MAC16 functional bit: MULT2_bram_cbit_0 +(7 2) MAC16 functional bit: MULT2_bram_cbit_3 +(7 3) MAC16 functional bit: MULT2_bram_cbit_2 +(7 4) MAC16 functional bit: MULT2_bram_cbit_5 +(7 5) MAC16 functional bit: MULT2_bram_cbit_4 +(7 6) MAC16 functional bit: MULT2_bram_cbit_7 +(7 7) MAC16 functional bit: MULT2_bram_cbit_6 +(8 0) routing sp4_h_l_40 sp4_h_r_1 +(8 0) routing sp4_v_b_1 sp4_h_r_1 +(8 0) routing sp4_v_b_7 sp4_h_r_1 +(8 1) routing sp4_h_l_36 sp4_v_b_1 +(8 1) routing sp4_h_l_42 sp4_v_b_1 +(8 1) routing sp4_h_r_1 sp4_v_b_1 +(8 1) routing sp4_v_t_47 sp4_v_b_1 +(8 10) routing sp4_v_t_36 sp4_h_l_42 +(8 10) routing sp4_v_t_42 sp4_h_l_42 +(8 11) routing sp4_h_l_42 sp4_v_t_42 +(8 11) routing sp4_h_r_1 sp4_v_t_42 +(8 11) routing sp4_h_r_7 sp4_v_t_42 +(8 11) routing sp4_v_b_4 sp4_v_t_42 +(8 12) routing sp4_h_l_39 sp4_h_r_10 +(8 12) routing sp4_h_l_47 sp4_h_r_10 +(8 12) routing sp4_v_b_10 sp4_h_r_10 +(8 12) routing sp4_v_b_4 sp4_h_r_10 +(8 13) routing sp4_h_l_41 sp4_v_b_10 +(8 13) routing sp4_h_l_47 sp4_v_b_10 +(8 13) routing sp4_h_r_10 sp4_v_b_10 +(8 13) routing sp4_v_t_42 sp4_v_b_10 +(8 14) routing sp4_h_r_10 sp4_h_l_47 +(8 14) routing sp4_h_r_2 sp4_h_l_47 +(8 14) routing sp4_v_t_41 sp4_h_l_47 +(8 14) routing sp4_v_t_47 sp4_h_l_47 +(8 15) routing sp4_h_l_47 sp4_v_t_47 +(8 15) routing sp4_h_r_10 sp4_v_t_47 +(8 15) routing sp4_h_r_4 sp4_v_t_47 +(8 15) routing sp4_v_b_7 sp4_v_t_47 +(8 2) routing sp4_v_t_36 sp4_h_l_36 +(8 2) routing sp4_v_t_42 sp4_h_l_36 +(8 3) routing sp4_h_l_36 sp4_v_t_36 +(8 3) routing sp4_h_r_1 sp4_v_t_36 +(8 3) routing sp4_h_r_7 sp4_v_t_36 +(8 3) routing sp4_v_b_10 sp4_v_t_36 +(8 4) routing sp4_h_l_45 sp4_h_r_4 +(8 4) routing sp4_v_b_10 sp4_h_r_4 +(8 4) routing sp4_v_b_4 sp4_h_r_4 +(8 5) routing sp4_h_l_41 sp4_v_b_4 +(8 5) routing sp4_h_l_47 sp4_v_b_4 +(8 5) routing sp4_h_r_4 sp4_v_b_4 +(8 5) routing sp4_v_t_36 sp4_v_b_4 +(8 6) routing sp4_h_r_4 sp4_h_l_41 +(8 6) routing sp4_h_r_8 sp4_h_l_41 +(8 6) routing sp4_v_t_41 sp4_h_l_41 +(8 6) routing sp4_v_t_47 sp4_h_l_41 +(8 7) routing sp4_h_l_41 sp4_v_t_41 +(8 7) routing sp4_h_r_10 sp4_v_t_41 +(8 7) routing sp4_h_r_4 sp4_v_t_41 +(8 7) routing sp4_v_b_1 sp4_v_t_41 +(8 8) routing sp4_v_b_1 sp4_h_r_7 +(8 8) routing sp4_v_b_7 sp4_h_r_7 +(8 9) routing sp4_h_l_36 sp4_v_b_7 +(8 9) routing sp4_h_l_42 sp4_v_b_7 +(8 9) routing sp4_h_r_7 sp4_v_b_7 +(8 9) routing sp4_v_t_41 sp4_v_b_7 +(9 0) routing sp4_v_b_1 sp4_h_r_1 +(9 0) routing sp4_v_b_7 sp4_h_r_1 +(9 0) routing sp4_v_t_36 sp4_h_r_1 +(9 1) routing sp4_h_l_36 sp4_v_b_1 +(9 1) routing sp4_h_l_42 sp4_v_b_1 +(9 1) routing sp4_v_t_36 sp4_v_b_1 +(9 1) routing sp4_v_t_40 sp4_v_b_1 +(9 10) routing sp4_h_r_4 sp4_h_l_42 +(9 10) routing sp4_v_b_7 sp4_h_l_42 +(9 10) routing sp4_v_t_36 sp4_h_l_42 +(9 10) routing sp4_v_t_42 sp4_h_l_42 +(9 11) routing sp4_h_r_1 sp4_v_t_42 +(9 11) routing sp4_h_r_7 sp4_v_t_42 +(9 11) routing sp4_v_b_11 sp4_v_t_42 +(9 11) routing sp4_v_b_7 sp4_v_t_42 +(9 12) routing sp4_v_b_10 sp4_h_r_10 +(9 12) routing sp4_v_b_4 sp4_h_r_10 +(9 12) routing sp4_v_t_47 sp4_h_r_10 +(9 13) routing sp4_h_l_41 sp4_v_b_10 +(9 13) routing sp4_h_l_47 sp4_v_b_10 +(9 13) routing sp4_v_t_39 sp4_v_b_10 +(9 13) routing sp4_v_t_47 sp4_v_b_10 +(9 14) routing sp4_v_b_10 sp4_h_l_47 +(9 14) routing sp4_v_t_41 sp4_h_l_47 +(9 14) routing sp4_v_t_47 sp4_h_l_47 +(9 15) routing sp4_h_r_10 sp4_v_t_47 +(9 15) routing sp4_h_r_4 sp4_v_t_47 +(9 15) routing sp4_v_b_10 sp4_v_t_47 +(9 15) routing sp4_v_b_2 sp4_v_t_47 +(9 2) routing sp4_h_r_10 sp4_h_l_36 +(9 2) routing sp4_v_b_1 sp4_h_l_36 +(9 2) routing sp4_v_t_36 sp4_h_l_36 +(9 2) routing sp4_v_t_42 sp4_h_l_36 +(9 3) routing sp4_h_r_1 sp4_v_t_36 +(9 3) routing sp4_h_r_7 sp4_v_t_36 +(9 3) routing sp4_v_b_1 sp4_v_t_36 +(9 3) routing sp4_v_b_5 sp4_v_t_36 +(9 4) routing sp4_v_b_10 sp4_h_r_4 +(9 4) routing sp4_v_b_4 sp4_h_r_4 +(9 4) routing sp4_v_t_41 sp4_h_r_4 +(9 5) routing sp4_h_l_41 sp4_v_b_4 +(9 5) routing sp4_h_l_47 sp4_v_b_4 +(9 5) routing sp4_v_t_41 sp4_v_b_4 +(9 5) routing sp4_v_t_45 sp4_v_b_4 +(9 6) routing sp4_v_b_4 sp4_h_l_41 +(9 6) routing sp4_v_t_41 sp4_h_l_41 +(9 6) routing sp4_v_t_47 sp4_h_l_41 +(9 7) routing sp4_h_r_10 sp4_v_t_41 +(9 7) routing sp4_h_r_4 sp4_v_t_41 +(9 7) routing sp4_v_b_4 sp4_v_t_41 +(9 7) routing sp4_v_b_8 sp4_v_t_41 +(9 8) routing sp4_v_b_1 sp4_h_r_7 +(9 8) routing sp4_v_b_7 sp4_h_r_7 +(9 8) routing sp4_v_t_42 sp4_h_r_7 +(9 9) routing sp4_h_l_36 sp4_v_b_7 +(9 9) routing sp4_h_l_42 sp4_v_b_7 +(9 9) routing sp4_v_t_42 sp4_v_b_7 +(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/cached_dsp3_5k.txt b/icefuzz/cached_dsp3_5k.txt index e69de29..f42a3f9 100644 --- a/icefuzz/cached_dsp3_5k.txt +++ b/icefuzz/cached_dsp3_5k.txt @@ -0,0 +1,3159 @@ +(0 10) routing glb_netwk_2 glb2local_2 +(0 10) routing glb_netwk_3 glb2local_2 +(0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 +(0 11) routing glb_netwk_3 glb2local_2 +(0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_2 glb2local_3 +(0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 +(0 13) routing glb_netwk_1 glb2local_3 +(0 13) routing glb_netwk_3 glb2local_3 +(0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 +(0 14) routing glb_netwk_4 wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 +(0 7) routing glb_netwk_1 glb2local_0 +(0 7) routing glb_netwk_3 glb2local_0 +(0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_2 glb2local_1 +(0 8) routing glb_netwk_3 glb2local_1 +(0 8) routing glb_netwk_6 glb2local_1 +(0 8) routing glb_netwk_7 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 +(0 9) routing glb_netwk_5 glb2local_1 +(0 9) routing glb_netwk_7 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 glb2local_2 +(1 11) routing glb_netwk_5 glb2local_2 +(1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 +(1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 +(1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 +(1 9) routing glb_netwk_5 glb2local_1 +(1 9) routing glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_7 glb2local_1 +(10 0) routing sp4_h_l_40 sp4_h_r_1 +(10 0) routing sp4_v_b_7 sp4_h_r_1 +(10 0) routing sp4_v_t_45 sp4_h_r_1 +(10 1) routing sp4_h_l_42 sp4_v_b_1 +(10 1) routing sp4_h_r_8 sp4_v_b_1 +(10 1) routing sp4_v_t_40 sp4_v_b_1 +(10 1) routing sp4_v_t_47 sp4_v_b_1 +(10 10) routing sp4_h_r_4 sp4_h_l_42 +(10 10) routing sp4_v_b_2 sp4_h_l_42 +(10 10) routing sp4_v_t_36 sp4_h_l_42 +(10 11) routing sp4_h_l_39 sp4_v_t_42 +(10 11) routing sp4_h_r_1 sp4_v_t_42 +(10 11) routing sp4_v_b_11 sp4_v_t_42 +(10 11) routing sp4_v_b_4 sp4_v_t_42 +(10 12) routing sp4_h_l_42 sp4_h_r_10 +(10 12) routing sp4_v_b_4 sp4_h_r_10 +(10 12) routing sp4_v_t_40 sp4_h_r_10 +(10 13) routing sp4_h_l_41 sp4_v_b_10 +(10 13) routing sp4_h_r_5 sp4_v_b_10 +(10 13) routing sp4_v_t_39 sp4_v_b_10 +(10 13) routing sp4_v_t_42 sp4_v_b_10 +(10 14) routing sp4_h_r_2 sp4_h_l_47 +(10 14) routing sp4_v_b_5 sp4_h_l_47 +(10 14) routing sp4_v_t_41 sp4_h_l_47 +(10 15) routing sp4_h_l_40 sp4_v_t_47 +(10 15) routing sp4_h_r_4 sp4_v_t_47 +(10 15) routing sp4_v_b_2 sp4_v_t_47 +(10 15) routing sp4_v_b_7 sp4_v_t_47 +(10 2) routing sp4_h_r_10 sp4_h_l_36 +(10 2) routing sp4_v_b_8 sp4_h_l_36 +(10 2) routing sp4_v_t_42 sp4_h_l_36 +(10 3) routing sp4_h_l_45 sp4_v_t_36 +(10 3) routing sp4_h_r_7 sp4_v_t_36 +(10 3) routing sp4_v_b_10 sp4_v_t_36 +(10 3) routing sp4_v_b_5 sp4_v_t_36 +(10 4) routing sp4_h_l_45 sp4_h_r_4 +(10 4) routing sp4_v_b_10 sp4_h_r_4 +(10 4) routing sp4_v_t_46 sp4_h_r_4 +(10 5) routing sp4_h_l_47 sp4_v_b_4 +(10 5) routing sp4_h_r_11 sp4_v_b_4 +(10 5) routing sp4_v_t_36 sp4_v_b_4 +(10 5) routing sp4_v_t_45 sp4_v_b_4 +(10 6) routing sp4_h_r_8 sp4_h_l_41 +(10 6) routing sp4_v_b_11 sp4_h_l_41 +(10 6) routing sp4_v_t_47 sp4_h_l_41 +(10 7) routing sp4_h_l_46 sp4_v_t_41 +(10 7) routing sp4_h_r_10 sp4_v_t_41 +(10 7) routing sp4_v_b_1 sp4_v_t_41 +(10 7) routing sp4_v_b_8 sp4_v_t_41 +(10 8) routing sp4_h_l_41 sp4_h_r_7 +(10 8) routing sp4_h_l_46 sp4_h_r_7 +(10 8) routing sp4_v_b_1 sp4_h_r_7 +(10 8) routing sp4_v_t_39 sp4_h_r_7 +(10 9) routing sp4_h_l_36 sp4_v_b_7 +(10 9) routing sp4_h_r_2 sp4_v_b_7 +(10 9) routing sp4_v_t_41 sp4_v_b_7 +(10 9) routing sp4_v_t_46 sp4_v_b_7 +(11 0) routing sp4_h_l_45 sp4_v_b_2 +(11 0) routing sp4_h_r_9 sp4_v_b_2 +(11 0) routing sp4_v_t_43 sp4_v_b_2 +(11 0) routing sp4_v_t_46 sp4_v_b_2 +(11 1) routing sp4_v_b_2 sp4_h_r_2 +(11 1) routing sp4_v_b_8 sp4_h_r_2 +(11 10) routing sp4_h_l_38 sp4_v_t_45 +(11 10) routing sp4_h_r_2 sp4_v_t_45 +(11 10) routing sp4_v_b_0 sp4_v_t_45 +(11 10) routing sp4_v_b_5 sp4_v_t_45 +(11 11) routing sp4_h_r_0 sp4_h_l_45 +(11 11) routing sp4_h_r_8 sp4_h_l_45 +(11 11) routing sp4_v_t_39 sp4_h_l_45 +(11 11) routing sp4_v_t_45 sp4_h_l_45 +(11 12) routing sp4_h_l_40 sp4_v_b_11 +(11 12) routing sp4_h_r_6 sp4_v_b_11 +(11 12) routing sp4_v_t_38 sp4_v_b_11 +(11 12) routing sp4_v_t_45 sp4_v_b_11 +(11 13) routing sp4_h_l_46 sp4_h_r_11 +(11 13) routing sp4_v_b_11 sp4_h_r_11 +(11 13) routing sp4_v_b_5 sp4_h_r_11 +(11 14) routing sp4_h_l_43 sp4_v_t_46 +(11 14) routing sp4_h_r_5 sp4_v_t_46 +(11 14) routing sp4_v_b_3 sp4_v_t_46 +(11 14) routing sp4_v_b_8 sp4_v_t_46 +(11 15) routing sp4_h_r_3 sp4_h_l_46 +(11 15) routing sp4_v_t_40 sp4_h_l_46 +(11 15) routing sp4_v_t_46 sp4_h_l_46 +(11 2) routing sp4_h_l_44 sp4_v_t_39 +(11 2) routing sp4_h_r_8 sp4_v_t_39 +(11 2) routing sp4_v_b_11 sp4_v_t_39 +(11 2) routing sp4_v_b_6 sp4_v_t_39 +(11 3) routing sp4_h_r_2 sp4_h_l_39 +(11 3) routing sp4_h_r_6 sp4_h_l_39 +(11 3) routing sp4_v_t_39 sp4_h_l_39 +(11 3) routing sp4_v_t_45 sp4_h_l_39 +(11 4) routing sp4_h_l_46 sp4_v_b_5 +(11 4) routing sp4_h_r_0 sp4_v_b_5 +(11 4) routing sp4_v_t_39 sp4_v_b_5 +(11 4) routing sp4_v_t_44 sp4_v_b_5 +(11 5) routing sp4_h_l_40 sp4_h_r_5 +(11 5) routing sp4_h_l_44 sp4_h_r_5 +(11 5) routing sp4_v_b_11 sp4_h_r_5 +(11 5) routing sp4_v_b_5 sp4_h_r_5 +(11 6) routing sp4_h_l_37 sp4_v_t_40 +(11 6) routing sp4_h_r_11 sp4_v_t_40 +(11 6) routing sp4_v_b_2 sp4_v_t_40 +(11 6) routing sp4_v_b_9 sp4_v_t_40 +(11 7) routing sp4_v_t_40 sp4_h_l_40 +(11 7) routing sp4_v_t_46 sp4_h_l_40 +(11 8) routing sp4_h_l_39 sp4_v_b_8 +(11 8) routing sp4_h_r_3 sp4_v_b_8 +(11 8) routing sp4_v_t_37 sp4_v_b_8 +(11 8) routing sp4_v_t_40 sp4_v_b_8 +(11 9) routing sp4_h_l_37 sp4_h_r_8 +(11 9) routing sp4_v_b_2 sp4_h_r_8 +(11 9) routing sp4_v_b_8 sp4_h_r_8 +(12 0) routing sp4_h_l_46 sp4_h_r_2 +(12 0) routing sp4_v_b_2 sp4_h_r_2 +(12 0) routing sp4_v_b_8 sp4_h_r_2 +(12 0) routing sp4_v_t_39 sp4_h_r_2 +(12 1) routing sp4_h_l_39 sp4_v_b_2 +(12 1) routing sp4_h_l_45 sp4_v_b_2 +(12 1) routing sp4_h_r_2 sp4_v_b_2 +(12 1) routing sp4_v_t_46 sp4_v_b_2 +(12 10) routing sp4_v_b_8 sp4_h_l_45 +(12 10) routing sp4_v_t_39 sp4_h_l_45 +(12 10) routing sp4_v_t_45 sp4_h_l_45 +(12 11) routing sp4_h_l_45 sp4_v_t_45 +(12 11) routing sp4_h_r_2 sp4_v_t_45 +(12 11) routing sp4_h_r_8 sp4_v_t_45 +(12 11) routing sp4_v_b_5 sp4_v_t_45 +(12 12) routing sp4_v_b_11 sp4_h_r_11 +(12 12) routing sp4_v_b_5 sp4_h_r_11 +(12 12) routing sp4_v_t_46 sp4_h_r_11 +(12 13) routing sp4_h_l_40 sp4_v_b_11 +(12 13) routing sp4_h_l_46 sp4_v_b_11 +(12 13) routing sp4_h_r_11 sp4_v_b_11 +(12 13) routing sp4_v_t_45 sp4_v_b_11 +(12 14) routing sp4_h_r_8 sp4_h_l_46 +(12 14) routing sp4_v_b_11 sp4_h_l_46 +(12 14) routing sp4_v_t_40 sp4_h_l_46 +(12 14) routing sp4_v_t_46 sp4_h_l_46 +(12 15) routing sp4_h_l_46 sp4_v_t_46 +(12 15) routing sp4_h_r_11 sp4_v_t_46 +(12 15) routing sp4_h_r_5 sp4_v_t_46 +(12 15) routing sp4_v_b_8 sp4_v_t_46 +(12 2) routing sp4_v_b_2 sp4_h_l_39 +(12 2) routing sp4_v_t_39 sp4_h_l_39 +(12 2) routing sp4_v_t_45 sp4_h_l_39 +(12 3) routing sp4_h_l_39 sp4_v_t_39 +(12 3) routing sp4_h_r_2 sp4_v_t_39 +(12 3) routing sp4_h_r_8 sp4_v_t_39 +(12 3) routing sp4_v_b_11 sp4_v_t_39 +(12 4) routing sp4_v_b_11 sp4_h_r_5 +(12 4) routing sp4_v_b_5 sp4_h_r_5 +(12 4) routing sp4_v_t_40 sp4_h_r_5 +(12 5) routing sp4_h_l_40 sp4_v_b_5 +(12 5) routing sp4_h_l_46 sp4_v_b_5 +(12 5) routing sp4_h_r_5 sp4_v_b_5 +(12 5) routing sp4_v_t_39 sp4_v_b_5 +(12 6) routing sp4_h_r_2 sp4_h_l_40 +(12 6) routing sp4_v_b_5 sp4_h_l_40 +(12 6) routing sp4_v_t_40 sp4_h_l_40 +(12 6) routing sp4_v_t_46 sp4_h_l_40 +(12 7) routing sp4_h_l_40 sp4_v_t_40 +(12 7) routing sp4_h_r_11 sp4_v_t_40 +(12 7) routing sp4_h_r_5 sp4_v_t_40 +(12 7) routing sp4_v_b_2 sp4_v_t_40 +(12 8) routing sp4_h_l_40 sp4_h_r_8 +(12 8) routing sp4_v_b_2 sp4_h_r_8 +(12 8) routing sp4_v_b_8 sp4_h_r_8 +(12 8) routing sp4_v_t_45 sp4_h_r_8 +(12 9) routing sp4_h_l_39 sp4_v_b_8 +(12 9) routing sp4_h_l_45 sp4_v_b_8 +(12 9) routing sp4_h_r_8 sp4_v_b_8 +(12 9) routing sp4_v_t_40 sp4_v_b_8 +(13 0) routing sp4_h_l_39 sp4_v_b_2 +(13 0) routing sp4_h_l_45 sp4_v_b_2 +(13 0) routing sp4_v_t_39 sp4_v_b_2 +(13 0) routing sp4_v_t_43 sp4_v_b_2 +(13 1) routing sp4_h_l_46 sp4_h_r_2 +(13 1) routing sp4_v_b_8 sp4_h_r_2 +(13 1) routing sp4_v_t_44 sp4_h_r_2 +(13 10) routing sp4_h_r_2 sp4_v_t_45 +(13 10) routing sp4_h_r_8 sp4_v_t_45 +(13 10) routing sp4_v_b_0 sp4_v_t_45 +(13 10) routing sp4_v_b_8 sp4_v_t_45 +(13 11) routing sp4_h_r_0 sp4_h_l_45 +(13 11) routing sp4_v_b_3 sp4_h_l_45 +(13 11) routing sp4_v_t_39 sp4_h_l_45 +(13 12) routing sp4_h_l_40 sp4_v_b_11 +(13 12) routing sp4_h_l_46 sp4_v_b_11 +(13 12) routing sp4_v_t_38 sp4_v_b_11 +(13 12) routing sp4_v_t_46 sp4_v_b_11 +(13 13) routing sp4_v_b_5 sp4_h_r_11 +(13 13) routing sp4_v_t_43 sp4_h_r_11 +(13 14) routing sp4_h_r_11 sp4_v_t_46 +(13 14) routing sp4_h_r_5 sp4_v_t_46 +(13 14) routing sp4_v_b_11 sp4_v_t_46 +(13 14) routing sp4_v_b_3 sp4_v_t_46 +(13 15) routing sp4_h_r_3 sp4_h_l_46 +(13 15) routing sp4_h_r_8 sp4_h_l_46 +(13 15) routing sp4_v_b_6 sp4_h_l_46 +(13 15) routing sp4_v_t_40 sp4_h_l_46 +(13 2) routing sp4_h_r_2 sp4_v_t_39 +(13 2) routing sp4_h_r_8 sp4_v_t_39 +(13 2) routing sp4_v_b_2 sp4_v_t_39 +(13 2) routing sp4_v_b_6 sp4_v_t_39 +(13 3) routing sp4_h_r_6 sp4_h_l_39 +(13 3) routing sp4_v_b_9 sp4_h_l_39 +(13 3) routing sp4_v_t_45 sp4_h_l_39 +(13 4) routing sp4_h_l_40 sp4_v_b_5 +(13 4) routing sp4_h_l_46 sp4_v_b_5 +(13 4) routing sp4_v_t_40 sp4_v_b_5 +(13 4) routing sp4_v_t_44 sp4_v_b_5 +(13 5) routing sp4_h_l_44 sp4_h_r_5 +(13 5) routing sp4_v_b_11 sp4_h_r_5 +(13 5) routing sp4_v_t_37 sp4_h_r_5 +(13 6) routing sp4_h_r_11 sp4_v_t_40 +(13 6) routing sp4_h_r_5 sp4_v_t_40 +(13 6) routing sp4_v_b_5 sp4_v_t_40 +(13 6) routing sp4_v_b_9 sp4_v_t_40 +(13 7) routing sp4_h_r_2 sp4_h_l_40 +(13 7) routing sp4_v_b_0 sp4_h_l_40 +(13 7) routing sp4_v_t_46 sp4_h_l_40 +(13 8) routing sp4_h_l_39 sp4_v_b_8 +(13 8) routing sp4_h_l_45 sp4_v_b_8 +(13 8) routing sp4_v_t_37 sp4_v_b_8 +(13 8) routing sp4_v_t_45 sp4_v_b_8 +(13 9) routing sp4_h_l_37 sp4_h_r_8 +(13 9) routing sp4_h_l_40 sp4_h_r_8 +(13 9) routing sp4_v_b_2 sp4_h_r_8 +(13 9) routing sp4_v_t_38 sp4_h_r_8 +(14 0) routing sp12_h_r_0 lc_trk_g0_0 +(14 0) routing sp4_h_l_5 lc_trk_g0_0 +(14 0) routing sp4_h_r_8 lc_trk_g0_0 +(14 0) routing sp4_v_b_0 lc_trk_g0_0 +(14 0) routing sp4_v_b_8 lc_trk_g0_0 +(14 1) routing sp12_h_r_0 lc_trk_g0_0 +(14 1) routing sp12_h_r_16 lc_trk_g0_0 +(14 1) routing sp4_h_l_5 lc_trk_g0_0 +(14 1) routing sp4_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 +(14 1) routing sp4_v_b_8 lc_trk_g0_0 +(14 10) routing bnl_op_4 lc_trk_g2_4 +(14 10) routing rgt_op_4 lc_trk_g2_4 +(14 10) routing sp12_v_t_3 lc_trk_g2_4 +(14 10) routing sp4_h_l_25 lc_trk_g2_4 +(14 10) routing sp4_h_l_33 lc_trk_g2_4 +(14 10) routing sp4_v_b_28 lc_trk_g2_4 +(14 10) routing sp4_v_t_25 lc_trk_g2_4 +(14 11) routing bnl_op_4 lc_trk_g2_4 +(14 11) routing sp12_v_b_20 lc_trk_g2_4 +(14 11) routing sp12_v_t_3 lc_trk_g2_4 +(14 11) routing sp4_h_l_17 lc_trk_g2_4 +(14 11) routing sp4_h_l_33 lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 +(14 11) routing sp4_v_t_25 lc_trk_g2_4 +(14 11) routing tnl_op_4 lc_trk_g2_4 +(14 12) routing bnl_op_0 lc_trk_g3_0 +(14 12) routing rgt_op_0 lc_trk_g3_0 +(14 12) routing sp12_v_b_0 lc_trk_g3_0 +(14 12) routing sp4_h_r_32 lc_trk_g3_0 +(14 12) routing sp4_h_r_40 lc_trk_g3_0 +(14 12) routing sp4_v_b_32 lc_trk_g3_0 +(14 12) routing sp4_v_t_13 lc_trk_g3_0 +(14 13) routing bnl_op_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_16 lc_trk_g3_0 +(14 13) routing sp4_h_l_13 lc_trk_g3_0 +(14 13) routing sp4_h_r_40 lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 +(14 13) routing sp4_v_b_32 lc_trk_g3_0 +(14 13) routing tnl_op_0 lc_trk_g3_0 +(14 14) routing bnl_op_4 lc_trk_g3_4 +(14 14) routing rgt_op_4 lc_trk_g3_4 +(14 14) routing sp12_v_t_3 lc_trk_g3_4 +(14 14) routing sp4_h_l_25 lc_trk_g3_4 +(14 14) routing sp4_h_l_33 lc_trk_g3_4 +(14 14) routing sp4_v_b_28 lc_trk_g3_4 +(14 14) routing sp4_v_t_25 lc_trk_g3_4 +(14 15) routing bnl_op_4 lc_trk_g3_4 +(14 15) routing sp12_v_b_20 lc_trk_g3_4 +(14 15) routing sp12_v_t_3 lc_trk_g3_4 +(14 15) routing sp4_h_l_17 lc_trk_g3_4 +(14 15) routing sp4_h_l_33 lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 +(14 15) routing sp4_v_t_25 lc_trk_g3_4 +(14 15) routing tnl_op_4 lc_trk_g3_4 +(14 2) routing bnr_op_4 lc_trk_g0_4 +(14 2) routing lft_op_4 lc_trk_g0_4 +(14 2) routing sp12_h_r_4 lc_trk_g0_4 +(14 2) routing sp4_h_r_12 lc_trk_g0_4 +(14 2) routing sp4_h_r_20 lc_trk_g0_4 +(14 2) routing sp4_v_b_4 lc_trk_g0_4 +(14 2) routing sp4_v_t_1 lc_trk_g0_4 +(14 3) routing bnr_op_4 lc_trk_g0_4 +(14 3) routing sp12_h_r_20 lc_trk_g0_4 +(14 3) routing sp12_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_h_r_20 lc_trk_g0_4 +(14 3) routing sp4_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 +(14 3) routing sp4_v_t_1 lc_trk_g0_4 +(14 4) routing bnr_op_0 lc_trk_g1_0 +(14 4) routing lft_op_0 lc_trk_g1_0 +(14 4) routing sp12_h_r_0 lc_trk_g1_0 +(14 4) routing sp4_h_l_5 lc_trk_g1_0 +(14 4) routing sp4_h_r_8 lc_trk_g1_0 +(14 4) routing sp4_v_b_0 lc_trk_g1_0 +(14 4) routing sp4_v_b_8 lc_trk_g1_0 +(14 5) routing bnr_op_0 lc_trk_g1_0 +(14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp12_h_r_16 lc_trk_g1_0 +(14 5) routing sp4_h_l_5 lc_trk_g1_0 +(14 5) routing sp4_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 +(14 5) routing sp4_v_b_8 lc_trk_g1_0 +(14 6) routing bnr_op_4 lc_trk_g1_4 +(14 6) routing sp12_h_r_4 lc_trk_g1_4 +(14 6) routing sp4_h_r_12 lc_trk_g1_4 +(14 6) routing sp4_h_r_20 lc_trk_g1_4 +(14 6) routing sp4_v_b_4 lc_trk_g1_4 +(14 6) routing sp4_v_t_1 lc_trk_g1_4 +(14 7) routing bnr_op_4 lc_trk_g1_4 +(14 7) routing sp12_h_r_20 lc_trk_g1_4 +(14 7) routing sp12_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_h_r_20 lc_trk_g1_4 +(14 7) routing sp4_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 +(14 7) routing sp4_v_t_1 lc_trk_g1_4 +(14 8) routing bnl_op_0 lc_trk_g2_0 +(14 8) routing rgt_op_0 lc_trk_g2_0 +(14 8) routing sp12_v_b_0 lc_trk_g2_0 +(14 8) routing sp4_h_r_32 lc_trk_g2_0 +(14 8) routing sp4_h_r_40 lc_trk_g2_0 +(14 8) routing sp4_v_b_32 lc_trk_g2_0 +(14 8) routing sp4_v_t_13 lc_trk_g2_0 +(14 9) routing bnl_op_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_16 lc_trk_g2_0 +(14 9) routing sp4_h_l_13 lc_trk_g2_0 +(14 9) routing sp4_h_r_40 lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 +(14 9) routing sp4_v_b_32 lc_trk_g2_0 +(14 9) routing tnl_op_0 lc_trk_g2_0 +(15 0) routing lft_op_1 lc_trk_g0_1 +(15 0) routing sp12_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_17 lc_trk_g0_1 +(15 0) routing sp4_h_r_9 lc_trk_g0_1 +(15 0) routing sp4_v_b_17 lc_trk_g0_1 +(15 1) routing sp12_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_l_5 lc_trk_g0_0 +(15 1) routing sp4_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_8 lc_trk_g0_0 +(15 1) routing sp4_v_t_5 lc_trk_g0_0 +(15 10) routing rgt_op_5 lc_trk_g2_5 +(15 10) routing sp12_v_b_5 lc_trk_g2_5 +(15 10) routing sp4_h_l_24 lc_trk_g2_5 +(15 10) routing sp4_h_r_29 lc_trk_g2_5 +(15 10) routing sp4_h_r_45 lc_trk_g2_5 +(15 10) routing sp4_v_t_32 lc_trk_g2_5 +(15 10) routing tnl_op_5 lc_trk_g2_5 +(15 10) routing tnr_op_5 lc_trk_g2_5 +(15 11) routing rgt_op_4 lc_trk_g2_4 +(15 11) routing sp12_v_t_3 lc_trk_g2_4 +(15 11) routing sp4_h_l_17 lc_trk_g2_4 +(15 11) routing sp4_h_l_25 lc_trk_g2_4 +(15 11) routing sp4_h_l_33 lc_trk_g2_4 +(15 11) routing sp4_v_b_44 lc_trk_g2_4 +(15 11) routing tnl_op_4 lc_trk_g2_4 +(15 11) routing tnr_op_4 lc_trk_g2_4 +(15 12) routing rgt_op_1 lc_trk_g3_1 +(15 12) routing sp12_v_b_1 lc_trk_g3_1 +(15 12) routing sp4_h_l_20 lc_trk_g3_1 +(15 12) routing sp4_h_r_25 lc_trk_g3_1 +(15 12) routing sp4_h_r_41 lc_trk_g3_1 +(15 12) routing sp4_v_b_41 lc_trk_g3_1 +(15 12) routing tnl_op_1 lc_trk_g3_1 +(15 12) routing tnr_op_1 lc_trk_g3_1 +(15 13) routing rgt_op_0 lc_trk_g3_0 +(15 13) routing sp12_v_b_0 lc_trk_g3_0 +(15 13) routing sp4_h_l_13 lc_trk_g3_0 +(15 13) routing sp4_h_r_32 lc_trk_g3_0 +(15 13) routing sp4_h_r_40 lc_trk_g3_0 +(15 13) routing sp4_v_t_29 lc_trk_g3_0 +(15 13) routing tnl_op_0 lc_trk_g3_0 +(15 13) routing tnr_op_0 lc_trk_g3_0 +(15 14) routing rgt_op_5 lc_trk_g3_5 +(15 14) routing sp12_v_b_5 lc_trk_g3_5 +(15 14) routing sp4_h_l_24 lc_trk_g3_5 +(15 14) routing sp4_h_r_29 lc_trk_g3_5 +(15 14) routing sp4_h_r_45 lc_trk_g3_5 +(15 14) routing sp4_v_t_32 lc_trk_g3_5 +(15 14) routing tnl_op_5 lc_trk_g3_5 +(15 14) routing tnr_op_5 lc_trk_g3_5 +(15 15) routing rgt_op_4 lc_trk_g3_4 +(15 15) routing sp12_v_t_3 lc_trk_g3_4 +(15 15) routing sp4_h_l_17 lc_trk_g3_4 +(15 15) routing sp4_h_l_25 lc_trk_g3_4 +(15 15) routing sp4_h_l_33 lc_trk_g3_4 +(15 15) routing sp4_v_b_44 lc_trk_g3_4 +(15 15) routing tnl_op_4 lc_trk_g3_4 +(15 15) routing tnr_op_4 lc_trk_g3_4 +(15 2) routing lft_op_5 lc_trk_g0_5 +(15 2) routing sp12_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_h_l_0 lc_trk_g0_5 +(15 2) routing sp4_h_r_21 lc_trk_g0_5 +(15 2) routing sp4_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_v_t_8 lc_trk_g0_5 +(15 3) routing lft_op_4 lc_trk_g0_4 +(15 3) routing sp12_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_h_r_12 lc_trk_g0_4 +(15 3) routing sp4_h_r_20 lc_trk_g0_4 +(15 3) routing sp4_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_v_b_20 lc_trk_g0_4 +(15 4) routing lft_op_1 lc_trk_g1_1 +(15 4) routing sp12_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_17 lc_trk_g1_1 +(15 4) routing sp4_h_r_9 lc_trk_g1_1 +(15 4) routing sp4_v_b_17 lc_trk_g1_1 +(15 5) routing lft_op_0 lc_trk_g1_0 +(15 5) routing sp12_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_l_5 lc_trk_g1_0 +(15 5) routing sp4_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_8 lc_trk_g1_0 +(15 5) routing sp4_v_t_5 lc_trk_g1_0 +(15 6) routing lft_op_5 lc_trk_g1_5 +(15 6) routing sp12_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_h_l_0 lc_trk_g1_5 +(15 6) routing sp4_h_r_21 lc_trk_g1_5 +(15 6) routing sp4_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_v_t_8 lc_trk_g1_5 +(15 7) routing sp12_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_h_r_12 lc_trk_g1_4 +(15 7) routing sp4_h_r_20 lc_trk_g1_4 +(15 7) routing sp4_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_v_b_20 lc_trk_g1_4 +(15 8) routing rgt_op_1 lc_trk_g2_1 +(15 8) routing sp12_v_b_1 lc_trk_g2_1 +(15 8) routing sp4_h_l_20 lc_trk_g2_1 +(15 8) routing sp4_h_r_25 lc_trk_g2_1 +(15 8) routing sp4_h_r_41 lc_trk_g2_1 +(15 8) routing sp4_v_b_41 lc_trk_g2_1 +(15 8) routing tnl_op_1 lc_trk_g2_1 +(15 8) routing tnr_op_1 lc_trk_g2_1 +(15 9) routing rgt_op_0 lc_trk_g2_0 +(15 9) routing sp12_v_b_0 lc_trk_g2_0 +(15 9) routing sp4_h_l_13 lc_trk_g2_0 +(15 9) routing sp4_h_r_32 lc_trk_g2_0 +(15 9) routing sp4_h_r_40 lc_trk_g2_0 +(15 9) routing sp4_v_t_29 lc_trk_g2_0 +(15 9) routing tnl_op_0 lc_trk_g2_0 +(15 9) routing tnr_op_0 lc_trk_g2_0 +(16 0) routing sp12_h_l_14 lc_trk_g0_1 +(16 0) routing sp12_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_h_r_1 lc_trk_g0_1 +(16 0) routing sp4_h_r_17 lc_trk_g0_1 +(16 0) routing sp4_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_v_b_1 lc_trk_g0_1 +(16 0) routing sp4_v_b_17 lc_trk_g0_1 +(16 0) routing sp4_v_b_9 lc_trk_g0_1 +(16 1) routing sp12_h_r_16 lc_trk_g0_0 +(16 1) routing sp12_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_h_l_5 lc_trk_g0_0 +(16 1) routing sp4_h_r_0 lc_trk_g0_0 +(16 1) routing sp4_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_v_b_0 lc_trk_g0_0 +(16 1) routing sp4_v_b_8 lc_trk_g0_0 +(16 1) routing sp4_v_t_5 lc_trk_g0_0 +(16 10) routing sp12_v_b_21 lc_trk_g2_5 +(16 10) routing sp12_v_t_10 lc_trk_g2_5 +(16 10) routing sp4_h_l_24 lc_trk_g2_5 +(16 10) routing sp4_h_r_29 lc_trk_g2_5 +(16 10) routing sp4_h_r_45 lc_trk_g2_5 +(16 10) routing sp4_v_b_37 lc_trk_g2_5 +(16 10) routing sp4_v_t_16 lc_trk_g2_5 +(16 10) routing sp4_v_t_32 lc_trk_g2_5 +(16 11) routing sp12_v_b_12 lc_trk_g2_4 +(16 11) routing sp12_v_b_20 lc_trk_g2_4 +(16 11) routing sp4_h_l_17 lc_trk_g2_4 +(16 11) routing sp4_h_l_25 lc_trk_g2_4 +(16 11) routing sp4_h_l_33 lc_trk_g2_4 +(16 11) routing sp4_v_b_28 lc_trk_g2_4 +(16 11) routing sp4_v_b_44 lc_trk_g2_4 +(16 11) routing sp4_v_t_25 lc_trk_g2_4 +(16 12) routing sp12_v_b_9 lc_trk_g3_1 +(16 12) routing sp12_v_t_14 lc_trk_g3_1 +(16 12) routing sp4_h_l_20 lc_trk_g3_1 +(16 12) routing sp4_h_r_25 lc_trk_g3_1 +(16 12) routing sp4_h_r_41 lc_trk_g3_1 +(16 12) routing sp4_v_b_41 lc_trk_g3_1 +(16 12) routing sp4_v_t_12 lc_trk_g3_1 +(16 12) routing sp4_v_t_20 lc_trk_g3_1 +(16 13) routing sp12_v_b_16 lc_trk_g3_0 +(16 13) routing sp12_v_t_7 lc_trk_g3_0 +(16 13) routing sp4_h_l_13 lc_trk_g3_0 +(16 13) routing sp4_h_r_32 lc_trk_g3_0 +(16 13) routing sp4_h_r_40 lc_trk_g3_0 +(16 13) routing sp4_v_b_32 lc_trk_g3_0 +(16 13) routing sp4_v_t_13 lc_trk_g3_0 +(16 13) routing sp4_v_t_29 lc_trk_g3_0 +(16 14) routing sp12_v_b_21 lc_trk_g3_5 +(16 14) routing sp12_v_t_10 lc_trk_g3_5 +(16 14) routing sp4_h_l_24 lc_trk_g3_5 +(16 14) routing sp4_h_r_29 lc_trk_g3_5 +(16 14) routing sp4_h_r_45 lc_trk_g3_5 +(16 14) routing sp4_v_b_37 lc_trk_g3_5 +(16 14) routing sp4_v_t_16 lc_trk_g3_5 +(16 14) routing sp4_v_t_32 lc_trk_g3_5 +(16 15) routing sp12_v_b_12 lc_trk_g3_4 +(16 15) routing sp12_v_b_20 lc_trk_g3_4 +(16 15) routing sp4_h_l_17 lc_trk_g3_4 +(16 15) routing sp4_h_l_25 lc_trk_g3_4 +(16 15) routing sp4_h_l_33 lc_trk_g3_4 +(16 15) routing sp4_v_b_28 lc_trk_g3_4 +(16 15) routing sp4_v_b_44 lc_trk_g3_4 +(16 15) routing sp4_v_t_25 lc_trk_g3_4 +(16 2) routing sp12_h_l_10 lc_trk_g0_5 +(16 2) routing sp12_h_r_21 lc_trk_g0_5 +(16 2) routing sp4_h_l_0 lc_trk_g0_5 +(16 2) routing sp4_h_r_21 lc_trk_g0_5 +(16 2) routing sp4_h_r_5 lc_trk_g0_5 +(16 2) routing sp4_v_b_5 lc_trk_g0_5 +(16 2) routing sp4_v_t_0 lc_trk_g0_5 +(16 2) routing sp4_v_t_8 lc_trk_g0_5 +(16 3) routing sp12_h_l_11 lc_trk_g0_4 +(16 3) routing sp12_h_r_20 lc_trk_g0_4 +(16 3) routing sp4_h_r_12 lc_trk_g0_4 +(16 3) routing sp4_h_r_20 lc_trk_g0_4 +(16 3) routing sp4_h_r_4 lc_trk_g0_4 +(16 3) routing sp4_v_b_20 lc_trk_g0_4 +(16 3) routing sp4_v_b_4 lc_trk_g0_4 +(16 3) routing sp4_v_t_1 lc_trk_g0_4 +(16 4) routing sp12_h_l_14 lc_trk_g1_1 +(16 4) routing sp12_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_h_r_1 lc_trk_g1_1 +(16 4) routing sp4_h_r_17 lc_trk_g1_1 +(16 4) routing sp4_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_v_b_1 lc_trk_g1_1 +(16 4) routing sp4_v_b_17 lc_trk_g1_1 +(16 4) routing sp4_v_b_9 lc_trk_g1_1 +(16 5) routing sp12_h_r_16 lc_trk_g1_0 +(16 5) routing sp12_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_h_l_5 lc_trk_g1_0 +(16 5) routing sp4_h_r_0 lc_trk_g1_0 +(16 5) routing sp4_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_v_b_0 lc_trk_g1_0 +(16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 5) routing sp4_v_t_5 lc_trk_g1_0 +(16 6) routing sp12_h_l_10 lc_trk_g1_5 +(16 6) routing sp12_h_r_21 lc_trk_g1_5 +(16 6) routing sp4_h_l_0 lc_trk_g1_5 +(16 6) routing sp4_h_r_21 lc_trk_g1_5 +(16 6) routing sp4_h_r_5 lc_trk_g1_5 +(16 6) routing sp4_v_b_5 lc_trk_g1_5 +(16 6) routing sp4_v_t_0 lc_trk_g1_5 +(16 6) routing sp4_v_t_8 lc_trk_g1_5 +(16 7) routing sp12_h_l_11 lc_trk_g1_4 +(16 7) routing sp12_h_r_20 lc_trk_g1_4 +(16 7) routing sp4_h_r_12 lc_trk_g1_4 +(16 7) routing sp4_h_r_20 lc_trk_g1_4 +(16 7) routing sp4_h_r_4 lc_trk_g1_4 +(16 7) routing sp4_v_b_20 lc_trk_g1_4 +(16 7) routing sp4_v_b_4 lc_trk_g1_4 +(16 7) routing sp4_v_t_1 lc_trk_g1_4 +(16 8) routing sp12_v_b_9 lc_trk_g2_1 +(16 8) routing sp12_v_t_14 lc_trk_g2_1 +(16 8) routing sp4_h_l_20 lc_trk_g2_1 +(16 8) routing sp4_h_r_25 lc_trk_g2_1 +(16 8) routing sp4_h_r_41 lc_trk_g2_1 +(16 8) routing sp4_v_b_41 lc_trk_g2_1 +(16 8) routing sp4_v_t_12 lc_trk_g2_1 +(16 8) routing sp4_v_t_20 lc_trk_g2_1 +(16 9) routing sp12_v_b_16 lc_trk_g2_0 +(16 9) routing sp12_v_t_7 lc_trk_g2_0 +(16 9) routing sp4_h_l_13 lc_trk_g2_0 +(16 9) routing sp4_h_r_32 lc_trk_g2_0 +(16 9) routing sp4_h_r_40 lc_trk_g2_0 +(16 9) routing sp4_v_b_32 lc_trk_g2_0 +(16 9) routing sp4_v_t_13 lc_trk_g2_0 +(16 9) routing sp4_v_t_29 lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_t_5 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_32 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_32 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_t_5 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 lc_trk_g0_1 +(18 0) routing lft_op_1 lc_trk_g0_1 +(18 0) routing sp12_h_r_1 lc_trk_g0_1 +(18 0) routing sp4_h_r_17 lc_trk_g0_1 +(18 0) routing sp4_h_r_9 lc_trk_g0_1 +(18 0) routing sp4_v_b_1 lc_trk_g0_1 +(18 0) routing sp4_v_b_9 lc_trk_g0_1 +(18 1) routing bnr_op_1 lc_trk_g0_1 +(18 1) routing sp12_h_l_14 lc_trk_g0_1 +(18 1) routing sp12_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 +(18 1) routing sp4_v_b_9 lc_trk_g0_1 +(18 10) routing bnl_op_5 lc_trk_g2_5 +(18 10) routing rgt_op_5 lc_trk_g2_5 +(18 10) routing sp12_v_b_5 lc_trk_g2_5 +(18 10) routing sp4_h_l_24 lc_trk_g2_5 +(18 10) routing sp4_h_r_45 lc_trk_g2_5 +(18 10) routing sp4_v_b_37 lc_trk_g2_5 +(18 10) routing sp4_v_t_16 lc_trk_g2_5 +(18 11) routing bnl_op_5 lc_trk_g2_5 +(18 11) routing sp12_v_b_21 lc_trk_g2_5 +(18 11) routing sp12_v_b_5 lc_trk_g2_5 +(18 11) routing sp4_h_r_29 lc_trk_g2_5 +(18 11) routing sp4_h_r_45 lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 +(18 11) routing sp4_v_b_37 lc_trk_g2_5 +(18 11) routing tnl_op_5 lc_trk_g2_5 +(18 12) routing bnl_op_1 lc_trk_g3_1 +(18 12) routing rgt_op_1 lc_trk_g3_1 +(18 12) routing sp12_v_b_1 lc_trk_g3_1 +(18 12) routing sp4_h_l_20 lc_trk_g3_1 +(18 12) routing sp4_h_r_41 lc_trk_g3_1 +(18 12) routing sp4_v_t_12 lc_trk_g3_1 +(18 12) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing bnl_op_1 lc_trk_g3_1 +(18 13) routing sp12_v_b_1 lc_trk_g3_1 +(18 13) routing sp12_v_t_14 lc_trk_g3_1 +(18 13) routing sp4_h_r_25 lc_trk_g3_1 +(18 13) routing sp4_h_r_41 lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 +(18 13) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing tnl_op_1 lc_trk_g3_1 +(18 14) routing bnl_op_5 lc_trk_g3_5 +(18 14) routing rgt_op_5 lc_trk_g3_5 +(18 14) routing sp12_v_b_5 lc_trk_g3_5 +(18 14) routing sp4_h_l_24 lc_trk_g3_5 +(18 14) routing sp4_h_r_45 lc_trk_g3_5 +(18 14) routing sp4_v_b_37 lc_trk_g3_5 +(18 14) routing sp4_v_t_16 lc_trk_g3_5 +(18 15) routing bnl_op_5 lc_trk_g3_5 +(18 15) routing sp12_v_b_21 lc_trk_g3_5 +(18 15) routing sp12_v_b_5 lc_trk_g3_5 +(18 15) routing sp4_h_r_29 lc_trk_g3_5 +(18 15) routing sp4_h_r_45 lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 +(18 15) routing sp4_v_b_37 lc_trk_g3_5 +(18 15) routing tnl_op_5 lc_trk_g3_5 +(18 2) routing bnr_op_5 lc_trk_g0_5 +(18 2) routing lft_op_5 lc_trk_g0_5 +(18 2) routing sp12_h_r_5 lc_trk_g0_5 +(18 2) routing sp4_h_l_0 lc_trk_g0_5 +(18 2) routing sp4_h_r_21 lc_trk_g0_5 +(18 2) routing sp4_v_b_5 lc_trk_g0_5 +(18 2) routing sp4_v_t_0 lc_trk_g0_5 +(18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_r_21 lc_trk_g0_5 +(18 3) routing sp12_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_h_r_21 lc_trk_g0_5 +(18 3) routing sp4_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 +(18 3) routing sp4_v_t_0 lc_trk_g0_5 +(18 4) routing bnr_op_1 lc_trk_g1_1 +(18 4) routing lft_op_1 lc_trk_g1_1 +(18 4) routing sp12_h_r_1 lc_trk_g1_1 +(18 4) routing sp4_h_r_17 lc_trk_g1_1 +(18 4) routing sp4_h_r_9 lc_trk_g1_1 +(18 4) routing sp4_v_b_1 lc_trk_g1_1 +(18 4) routing sp4_v_b_9 lc_trk_g1_1 +(18 5) routing bnr_op_1 lc_trk_g1_1 +(18 5) routing sp12_h_l_14 lc_trk_g1_1 +(18 5) routing sp12_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_17 lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 +(18 5) routing sp4_v_b_9 lc_trk_g1_1 +(18 6) routing bnr_op_5 lc_trk_g1_5 +(18 6) routing lft_op_5 lc_trk_g1_5 +(18 6) routing sp12_h_r_5 lc_trk_g1_5 +(18 6) routing sp4_h_l_0 lc_trk_g1_5 +(18 6) routing sp4_h_r_21 lc_trk_g1_5 +(18 6) routing sp4_v_b_5 lc_trk_g1_5 +(18 6) routing sp4_v_t_0 lc_trk_g1_5 +(18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_r_21 lc_trk_g1_5 +(18 7) routing sp12_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_h_r_21 lc_trk_g1_5 +(18 7) routing sp4_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 +(18 7) routing sp4_v_t_0 lc_trk_g1_5 +(18 8) routing bnl_op_1 lc_trk_g2_1 +(18 8) routing rgt_op_1 lc_trk_g2_1 +(18 8) routing sp12_v_b_1 lc_trk_g2_1 +(18 8) routing sp4_h_l_20 lc_trk_g2_1 +(18 8) routing sp4_h_r_41 lc_trk_g2_1 +(18 8) routing sp4_v_t_12 lc_trk_g2_1 +(18 8) routing sp4_v_t_20 lc_trk_g2_1 +(18 9) routing bnl_op_1 lc_trk_g2_1 +(18 9) routing sp12_v_b_1 lc_trk_g2_1 +(18 9) routing sp12_v_t_14 lc_trk_g2_1 +(18 9) routing sp4_h_r_25 lc_trk_g2_1 +(18 9) routing sp4_h_r_41 lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 +(18 9) routing sp4_v_t_20 lc_trk_g2_1 +(18 9) routing tnl_op_1 lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_t_0 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_r_4 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_b_15 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_t_5 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 +(21 0) routing bnr_op_3 lc_trk_g0_3 +(21 0) routing sp12_h_l_0 lc_trk_g0_3 +(21 0) routing sp4_h_l_6 lc_trk_g0_3 +(21 0) routing sp4_h_r_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_3 lc_trk_g0_3 +(21 1) routing bnr_op_3 lc_trk_g0_3 +(21 1) routing sp12_h_l_0 lc_trk_g0_3 +(21 1) routing sp12_h_r_19 lc_trk_g0_3 +(21 1) routing sp4_h_l_6 lc_trk_g0_3 +(21 1) routing sp4_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 +(21 1) routing sp4_v_b_11 lc_trk_g0_3 +(21 10) routing bnl_op_7 lc_trk_g2_7 +(21 10) routing rgt_op_7 lc_trk_g2_7 +(21 10) routing sp12_v_t_4 lc_trk_g2_7 +(21 10) routing sp4_h_r_39 lc_trk_g2_7 +(21 10) routing sp4_h_r_47 lc_trk_g2_7 +(21 10) routing sp4_v_b_31 lc_trk_g2_7 +(21 10) routing sp4_v_b_39 lc_trk_g2_7 +(21 11) routing bnl_op_7 lc_trk_g2_7 +(21 11) routing sp12_v_t_20 lc_trk_g2_7 +(21 11) routing sp12_v_t_4 lc_trk_g2_7 +(21 11) routing sp4_h_l_18 lc_trk_g2_7 +(21 11) routing sp4_h_r_47 lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 +(21 11) routing sp4_v_b_39 lc_trk_g2_7 +(21 11) routing tnl_op_7 lc_trk_g2_7 +(21 12) routing bnl_op_3 lc_trk_g3_3 +(21 12) routing rgt_op_3 lc_trk_g3_3 +(21 12) routing sp12_v_t_0 lc_trk_g3_3 +(21 12) routing sp4_h_l_30 lc_trk_g3_3 +(21 12) routing sp4_h_r_35 lc_trk_g3_3 +(21 12) routing sp4_v_b_27 lc_trk_g3_3 +(21 12) routing sp4_v_b_35 lc_trk_g3_3 +(21 13) routing bnl_op_3 lc_trk_g3_3 +(21 13) routing sp12_v_t_0 lc_trk_g3_3 +(21 13) routing sp12_v_t_16 lc_trk_g3_3 +(21 13) routing sp4_h_l_30 lc_trk_g3_3 +(21 13) routing sp4_h_r_27 lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 +(21 13) routing sp4_v_b_35 lc_trk_g3_3 +(21 13) routing tnl_op_3 lc_trk_g3_3 +(21 14) routing bnl_op_7 lc_trk_g3_7 +(21 14) routing rgt_op_7 lc_trk_g3_7 +(21 14) routing sp12_v_t_4 lc_trk_g3_7 +(21 14) routing sp4_h_r_39 lc_trk_g3_7 +(21 14) routing sp4_h_r_47 lc_trk_g3_7 +(21 14) routing sp4_v_b_31 lc_trk_g3_7 +(21 14) routing sp4_v_b_39 lc_trk_g3_7 +(21 15) routing bnl_op_7 lc_trk_g3_7 +(21 15) routing sp12_v_t_20 lc_trk_g3_7 +(21 15) routing sp12_v_t_4 lc_trk_g3_7 +(21 15) routing sp4_h_l_18 lc_trk_g3_7 +(21 15) routing sp4_h_r_47 lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 +(21 15) routing sp4_v_b_39 lc_trk_g3_7 +(21 15) routing tnl_op_7 lc_trk_g3_7 +(21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_r_7 lc_trk_g0_7 +(21 2) routing sp4_h_r_15 lc_trk_g0_7 +(21 2) routing sp4_h_r_23 lc_trk_g0_7 +(21 2) routing sp4_v_b_15 lc_trk_g0_7 +(21 2) routing sp4_v_b_7 lc_trk_g0_7 +(21 3) routing sp12_h_l_20 lc_trk_g0_7 +(21 3) routing sp12_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_h_r_23 lc_trk_g0_7 +(21 3) routing sp4_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 +(21 3) routing sp4_v_b_15 lc_trk_g0_7 +(21 4) routing lft_op_3 lc_trk_g1_3 +(21 4) routing sp12_h_l_0 lc_trk_g1_3 +(21 4) routing sp4_h_l_6 lc_trk_g1_3 +(21 4) routing sp4_h_r_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_3 lc_trk_g1_3 +(21 5) routing sp12_h_l_0 lc_trk_g1_3 +(21 5) routing sp12_h_r_19 lc_trk_g1_3 +(21 5) routing sp4_h_l_6 lc_trk_g1_3 +(21 5) routing sp4_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 +(21 5) routing sp4_v_b_11 lc_trk_g1_3 +(21 6) routing bnr_op_7 lc_trk_g1_7 +(21 6) routing lft_op_7 lc_trk_g1_7 +(21 6) routing sp12_h_r_7 lc_trk_g1_7 +(21 6) routing sp4_h_r_15 lc_trk_g1_7 +(21 6) routing sp4_h_r_23 lc_trk_g1_7 +(21 6) routing sp4_v_b_15 lc_trk_g1_7 +(21 6) routing sp4_v_b_7 lc_trk_g1_7 +(21 7) routing bnr_op_7 lc_trk_g1_7 +(21 7) routing sp12_h_l_20 lc_trk_g1_7 +(21 7) routing sp12_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_h_r_23 lc_trk_g1_7 +(21 7) routing sp4_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 +(21 7) routing sp4_v_b_15 lc_trk_g1_7 +(21 8) routing bnl_op_3 lc_trk_g2_3 +(21 8) routing sp12_v_t_0 lc_trk_g2_3 +(21 8) routing sp4_h_l_30 lc_trk_g2_3 +(21 8) routing sp4_h_r_35 lc_trk_g2_3 +(21 8) routing sp4_v_b_27 lc_trk_g2_3 +(21 8) routing sp4_v_b_35 lc_trk_g2_3 +(21 9) routing bnl_op_3 lc_trk_g2_3 +(21 9) routing sp12_v_t_0 lc_trk_g2_3 +(21 9) routing sp12_v_t_16 lc_trk_g2_3 +(21 9) routing sp4_h_l_30 lc_trk_g2_3 +(21 9) routing sp4_h_r_27 lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 +(21 9) routing sp4_v_b_35 lc_trk_g2_3 +(21 9) routing tnl_op_3 lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_8 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_13 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_13 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_8 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_8 lc_trk_g0_3 +(23 0) routing sp12_h_r_19 lc_trk_g0_3 +(23 0) routing sp4_h_l_6 lc_trk_g0_3 +(23 0) routing sp4_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_3 lc_trk_g0_3 +(23 0) routing sp4_v_b_11 lc_trk_g0_3 +(23 0) routing sp4_v_b_19 lc_trk_g0_3 +(23 0) routing sp4_v_b_3 lc_trk_g0_3 +(23 1) routing sp12_h_l_17 lc_trk_g0_2 +(23 1) routing sp12_h_l_9 lc_trk_g0_2 +(23 1) routing sp4_h_l_7 lc_trk_g0_2 +(23 1) routing sp4_h_r_10 lc_trk_g0_2 +(23 1) routing sp4_h_r_2 lc_trk_g0_2 +(23 1) routing sp4_v_b_10 lc_trk_g0_2 +(23 1) routing sp4_v_b_18 lc_trk_g0_2 +(23 1) routing sp4_v_b_2 lc_trk_g0_2 +(23 10) routing sp12_v_t_12 lc_trk_g2_7 +(23 10) routing sp12_v_t_20 lc_trk_g2_7 +(23 10) routing sp4_h_l_18 lc_trk_g2_7 +(23 10) routing sp4_h_r_39 lc_trk_g2_7 +(23 10) routing sp4_h_r_47 lc_trk_g2_7 +(23 10) routing sp4_v_b_31 lc_trk_g2_7 +(23 10) routing sp4_v_b_39 lc_trk_g2_7 +(23 10) routing sp4_v_t_34 lc_trk_g2_7 +(23 11) routing sp12_v_b_22 lc_trk_g2_6 +(23 11) routing sp12_v_t_13 lc_trk_g2_6 +(23 11) routing sp4_h_l_27 lc_trk_g2_6 +(23 11) routing sp4_h_r_30 lc_trk_g2_6 +(23 11) routing sp4_h_r_46 lc_trk_g2_6 +(23 11) routing sp4_v_b_46 lc_trk_g2_6 +(23 11) routing sp4_v_t_19 lc_trk_g2_6 +(23 11) routing sp4_v_t_27 lc_trk_g2_6 +(23 12) routing sp12_v_t_16 lc_trk_g3_3 +(23 12) routing sp12_v_t_8 lc_trk_g3_3 +(23 12) routing sp4_h_l_30 lc_trk_g3_3 +(23 12) routing sp4_h_r_27 lc_trk_g3_3 +(23 12) routing sp4_h_r_35 lc_trk_g3_3 +(23 12) routing sp4_v_b_27 lc_trk_g3_3 +(23 12) routing sp4_v_b_35 lc_trk_g3_3 +(23 12) routing sp4_v_b_43 lc_trk_g3_3 +(23 13) routing sp12_v_t_17 lc_trk_g3_2 +(23 13) routing sp12_v_t_9 lc_trk_g3_2 +(23 13) routing sp4_h_l_15 lc_trk_g3_2 +(23 13) routing sp4_h_r_34 lc_trk_g3_2 +(23 13) routing sp4_h_r_42 lc_trk_g3_2 +(23 13) routing sp4_v_b_26 lc_trk_g3_2 +(23 13) routing sp4_v_t_23 lc_trk_g3_2 +(23 13) routing sp4_v_t_31 lc_trk_g3_2 +(23 14) routing sp12_v_t_12 lc_trk_g3_7 +(23 14) routing sp12_v_t_20 lc_trk_g3_7 +(23 14) routing sp4_h_l_18 lc_trk_g3_7 +(23 14) routing sp4_h_r_39 lc_trk_g3_7 +(23 14) routing sp4_h_r_47 lc_trk_g3_7 +(23 14) routing sp4_v_b_31 lc_trk_g3_7 +(23 14) routing sp4_v_b_39 lc_trk_g3_7 +(23 14) routing sp4_v_t_34 lc_trk_g3_7 +(23 15) routing sp12_v_b_22 lc_trk_g3_6 +(23 15) routing sp12_v_t_13 lc_trk_g3_6 +(23 15) routing sp4_h_l_27 lc_trk_g3_6 +(23 15) routing sp4_h_r_30 lc_trk_g3_6 +(23 15) routing sp4_h_r_46 lc_trk_g3_6 +(23 15) routing sp4_v_b_46 lc_trk_g3_6 +(23 15) routing sp4_v_t_19 lc_trk_g3_6 +(23 15) routing sp4_v_t_27 lc_trk_g3_6 +(23 2) routing sp12_h_l_20 lc_trk_g0_7 +(23 2) routing sp12_h_r_15 lc_trk_g0_7 +(23 2) routing sp4_h_r_15 lc_trk_g0_7 +(23 2) routing sp4_h_r_23 lc_trk_g0_7 +(23 2) routing sp4_h_r_7 lc_trk_g0_7 +(23 2) routing sp4_v_b_15 lc_trk_g0_7 +(23 2) routing sp4_v_b_7 lc_trk_g0_7 +(23 2) routing sp4_v_t_10 lc_trk_g0_7 +(23 3) routing sp12_h_r_14 lc_trk_g0_6 +(23 3) routing sp12_h_r_22 lc_trk_g0_6 +(23 3) routing sp4_h_l_11 lc_trk_g0_6 +(23 3) routing sp4_h_l_3 lc_trk_g0_6 +(23 3) routing sp4_h_r_6 lc_trk_g0_6 +(23 3) routing sp4_v_b_14 lc_trk_g0_6 +(23 3) routing sp4_v_b_22 lc_trk_g0_6 +(23 3) routing sp4_v_b_6 lc_trk_g0_6 +(23 4) routing sp12_h_l_8 lc_trk_g1_3 +(23 4) routing sp12_h_r_19 lc_trk_g1_3 +(23 4) routing sp4_h_l_6 lc_trk_g1_3 +(23 4) routing sp4_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_3 lc_trk_g1_3 +(23 4) routing sp4_v_b_11 lc_trk_g1_3 +(23 4) routing sp4_v_b_19 lc_trk_g1_3 +(23 4) routing sp4_v_b_3 lc_trk_g1_3 +(23 5) routing sp12_h_l_17 lc_trk_g1_2 +(23 5) routing sp12_h_l_9 lc_trk_g1_2 +(23 5) routing sp4_h_l_7 lc_trk_g1_2 +(23 5) routing sp4_h_r_10 lc_trk_g1_2 +(23 5) routing sp4_h_r_2 lc_trk_g1_2 +(23 5) routing sp4_v_b_10 lc_trk_g1_2 +(23 5) routing sp4_v_b_18 lc_trk_g1_2 +(23 5) routing sp4_v_b_2 lc_trk_g1_2 +(23 6) routing sp12_h_l_20 lc_trk_g1_7 +(23 6) routing sp12_h_r_15 lc_trk_g1_7 +(23 6) routing sp4_h_r_15 lc_trk_g1_7 +(23 6) routing sp4_h_r_23 lc_trk_g1_7 +(23 6) routing sp4_h_r_7 lc_trk_g1_7 +(23 6) routing sp4_v_b_15 lc_trk_g1_7 +(23 6) routing sp4_v_b_7 lc_trk_g1_7 +(23 6) routing sp4_v_t_10 lc_trk_g1_7 +(23 7) routing sp12_h_r_14 lc_trk_g1_6 +(23 7) routing sp12_h_r_22 lc_trk_g1_6 +(23 7) routing sp4_h_l_11 lc_trk_g1_6 +(23 7) routing sp4_h_l_3 lc_trk_g1_6 +(23 7) routing sp4_h_r_6 lc_trk_g1_6 +(23 7) routing sp4_v_b_14 lc_trk_g1_6 +(23 7) routing sp4_v_b_22 lc_trk_g1_6 +(23 7) routing sp4_v_b_6 lc_trk_g1_6 +(23 8) routing sp12_v_t_16 lc_trk_g2_3 +(23 8) routing sp12_v_t_8 lc_trk_g2_3 +(23 8) routing sp4_h_l_30 lc_trk_g2_3 +(23 8) routing sp4_h_r_27 lc_trk_g2_3 +(23 8) routing sp4_h_r_35 lc_trk_g2_3 +(23 8) routing sp4_v_b_27 lc_trk_g2_3 +(23 8) routing sp4_v_b_35 lc_trk_g2_3 +(23 8) routing sp4_v_b_43 lc_trk_g2_3 +(23 9) routing sp12_v_t_17 lc_trk_g2_2 +(23 9) routing sp12_v_t_9 lc_trk_g2_2 +(23 9) routing sp4_h_l_15 lc_trk_g2_2 +(23 9) routing sp4_h_r_34 lc_trk_g2_2 +(23 9) routing sp4_h_r_42 lc_trk_g2_2 +(23 9) routing sp4_v_b_26 lc_trk_g2_2 +(23 9) routing sp4_v_t_23 lc_trk_g2_2 +(23 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 0) routing sp12_h_l_0 lc_trk_g0_3 +(24 0) routing sp4_h_l_6 lc_trk_g0_3 +(24 0) routing sp4_h_r_11 lc_trk_g0_3 +(24 0) routing sp4_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_v_b_19 lc_trk_g0_3 +(24 1) routing lft_op_2 lc_trk_g0_2 +(24 1) routing sp12_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_h_l_7 lc_trk_g0_2 +(24 1) routing sp4_h_r_10 lc_trk_g0_2 +(24 1) routing sp4_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_v_b_18 lc_trk_g0_2 +(24 10) routing rgt_op_7 lc_trk_g2_7 +(24 10) routing sp12_v_t_4 lc_trk_g2_7 +(24 10) routing sp4_h_l_18 lc_trk_g2_7 +(24 10) routing sp4_h_r_39 lc_trk_g2_7 +(24 10) routing sp4_h_r_47 lc_trk_g2_7 +(24 10) routing sp4_v_t_34 lc_trk_g2_7 +(24 10) routing tnl_op_7 lc_trk_g2_7 +(24 10) routing tnr_op_7 lc_trk_g2_7 +(24 11) routing rgt_op_6 lc_trk_g2_6 +(24 11) routing sp12_v_b_6 lc_trk_g2_6 +(24 11) routing sp4_h_l_27 lc_trk_g2_6 +(24 11) routing sp4_h_r_30 lc_trk_g2_6 +(24 11) routing sp4_h_r_46 lc_trk_g2_6 +(24 11) routing sp4_v_b_46 lc_trk_g2_6 +(24 11) routing tnl_op_6 lc_trk_g2_6 +(24 11) routing tnr_op_6 lc_trk_g2_6 +(24 12) routing rgt_op_3 lc_trk_g3_3 +(24 12) routing sp12_v_t_0 lc_trk_g3_3 +(24 12) routing sp4_h_l_30 lc_trk_g3_3 +(24 12) routing sp4_h_r_27 lc_trk_g3_3 +(24 12) routing sp4_h_r_35 lc_trk_g3_3 +(24 12) routing sp4_v_b_43 lc_trk_g3_3 +(24 12) routing tnl_op_3 lc_trk_g3_3 +(24 12) routing tnr_op_3 lc_trk_g3_3 +(24 13) routing rgt_op_2 lc_trk_g3_2 +(24 13) routing sp12_v_t_1 lc_trk_g3_2 +(24 13) routing sp4_h_l_15 lc_trk_g3_2 +(24 13) routing sp4_h_r_34 lc_trk_g3_2 +(24 13) routing sp4_h_r_42 lc_trk_g3_2 +(24 13) routing sp4_v_t_31 lc_trk_g3_2 +(24 13) routing tnl_op_2 lc_trk_g3_2 +(24 13) routing tnr_op_2 lc_trk_g3_2 +(24 14) routing rgt_op_7 lc_trk_g3_7 +(24 14) routing sp12_v_t_4 lc_trk_g3_7 +(24 14) routing sp4_h_l_18 lc_trk_g3_7 +(24 14) routing sp4_h_r_39 lc_trk_g3_7 +(24 14) routing sp4_h_r_47 lc_trk_g3_7 +(24 14) routing sp4_v_t_34 lc_trk_g3_7 +(24 14) routing tnl_op_7 lc_trk_g3_7 +(24 14) routing tnr_op_7 lc_trk_g3_7 +(24 15) routing rgt_op_6 lc_trk_g3_6 +(24 15) routing sp12_v_b_6 lc_trk_g3_6 +(24 15) routing sp4_h_l_27 lc_trk_g3_6 +(24 15) routing sp4_h_r_30 lc_trk_g3_6 +(24 15) routing sp4_h_r_46 lc_trk_g3_6 +(24 15) routing sp4_v_b_46 lc_trk_g3_6 +(24 15) routing tnl_op_6 lc_trk_g3_6 +(24 15) routing tnr_op_6 lc_trk_g3_6 +(24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_h_r_15 lc_trk_g0_7 +(24 2) routing sp4_h_r_23 lc_trk_g0_7 +(24 2) routing sp4_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_v_t_10 lc_trk_g0_7 +(24 3) routing lft_op_6 lc_trk_g0_6 +(24 3) routing sp12_h_l_5 lc_trk_g0_6 +(24 3) routing sp4_h_l_11 lc_trk_g0_6 +(24 3) routing sp4_h_l_3 lc_trk_g0_6 +(24 3) routing sp4_h_r_6 lc_trk_g0_6 +(24 3) routing sp4_v_b_22 lc_trk_g0_6 +(24 4) routing lft_op_3 lc_trk_g1_3 +(24 4) routing sp12_h_l_0 lc_trk_g1_3 +(24 4) routing sp4_h_l_6 lc_trk_g1_3 +(24 4) routing sp4_h_r_11 lc_trk_g1_3 +(24 4) routing sp4_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_v_b_19 lc_trk_g1_3 +(24 5) routing lft_op_2 lc_trk_g1_2 +(24 5) routing sp12_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_h_l_7 lc_trk_g1_2 +(24 5) routing sp4_h_r_10 lc_trk_g1_2 +(24 5) routing sp4_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_v_b_18 lc_trk_g1_2 +(24 6) routing lft_op_7 lc_trk_g1_7 +(24 6) routing sp12_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_h_r_15 lc_trk_g1_7 +(24 6) routing sp4_h_r_23 lc_trk_g1_7 +(24 6) routing sp4_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_v_t_10 lc_trk_g1_7 +(24 7) routing lft_op_6 lc_trk_g1_6 +(24 7) routing sp12_h_l_5 lc_trk_g1_6 +(24 7) routing sp4_h_l_11 lc_trk_g1_6 +(24 7) routing sp4_h_l_3 lc_trk_g1_6 +(24 7) routing sp4_h_r_6 lc_trk_g1_6 +(24 7) routing sp4_v_b_22 lc_trk_g1_6 +(24 8) routing sp12_v_t_0 lc_trk_g2_3 +(24 8) routing sp4_h_l_30 lc_trk_g2_3 +(24 8) routing sp4_h_r_27 lc_trk_g2_3 +(24 8) routing sp4_h_r_35 lc_trk_g2_3 +(24 8) routing sp4_v_b_43 lc_trk_g2_3 +(24 8) routing tnl_op_3 lc_trk_g2_3 +(24 8) routing tnr_op_3 lc_trk_g2_3 +(24 9) routing rgt_op_2 lc_trk_g2_2 +(24 9) routing sp12_v_t_1 lc_trk_g2_2 +(24 9) routing sp4_h_l_15 lc_trk_g2_2 +(24 9) routing sp4_h_r_34 lc_trk_g2_2 +(24 9) routing sp4_h_r_42 lc_trk_g2_2 +(24 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 9) routing tnl_op_2 lc_trk_g2_2 +(24 9) routing tnr_op_2 lc_trk_g2_2 +(25 0) routing bnr_op_2 lc_trk_g0_2 +(25 0) routing lft_op_2 lc_trk_g0_2 +(25 0) routing sp12_h_r_2 lc_trk_g0_2 +(25 0) routing sp4_h_l_7 lc_trk_g0_2 +(25 0) routing sp4_h_r_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_2 lc_trk_g0_2 +(25 1) routing bnr_op_2 lc_trk_g0_2 +(25 1) routing sp12_h_l_17 lc_trk_g0_2 +(25 1) routing sp12_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_h_l_7 lc_trk_g0_2 +(25 1) routing sp4_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 +(25 1) routing sp4_v_b_10 lc_trk_g0_2 +(25 10) routing bnl_op_6 lc_trk_g2_6 +(25 10) routing rgt_op_6 lc_trk_g2_6 +(25 10) routing sp12_v_b_6 lc_trk_g2_6 +(25 10) routing sp4_h_l_27 lc_trk_g2_6 +(25 10) routing sp4_h_r_46 lc_trk_g2_6 +(25 10) routing sp4_v_t_19 lc_trk_g2_6 +(25 10) routing sp4_v_t_27 lc_trk_g2_6 +(25 11) routing bnl_op_6 lc_trk_g2_6 +(25 11) routing sp12_v_b_22 lc_trk_g2_6 +(25 11) routing sp12_v_b_6 lc_trk_g2_6 +(25 11) routing sp4_h_r_30 lc_trk_g2_6 +(25 11) routing sp4_h_r_46 lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 +(25 11) routing sp4_v_t_27 lc_trk_g2_6 +(25 11) routing tnl_op_6 lc_trk_g2_6 +(25 12) routing bnl_op_2 lc_trk_g3_2 +(25 12) routing rgt_op_2 lc_trk_g3_2 +(25 12) routing sp12_v_t_1 lc_trk_g3_2 +(25 12) routing sp4_h_r_34 lc_trk_g3_2 +(25 12) routing sp4_h_r_42 lc_trk_g3_2 +(25 12) routing sp4_v_b_26 lc_trk_g3_2 +(25 12) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing bnl_op_2 lc_trk_g3_2 +(25 13) routing sp12_v_t_1 lc_trk_g3_2 +(25 13) routing sp12_v_t_17 lc_trk_g3_2 +(25 13) routing sp4_h_l_15 lc_trk_g3_2 +(25 13) routing sp4_h_r_42 lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 +(25 13) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing tnl_op_2 lc_trk_g3_2 +(25 14) routing bnl_op_6 lc_trk_g3_6 +(25 14) routing rgt_op_6 lc_trk_g3_6 +(25 14) routing sp12_v_b_6 lc_trk_g3_6 +(25 14) routing sp4_h_l_27 lc_trk_g3_6 +(25 14) routing sp4_h_r_46 lc_trk_g3_6 +(25 14) routing sp4_v_t_19 lc_trk_g3_6 +(25 14) routing sp4_v_t_27 lc_trk_g3_6 +(25 15) routing bnl_op_6 lc_trk_g3_6 +(25 15) routing sp12_v_b_22 lc_trk_g3_6 +(25 15) routing sp12_v_b_6 lc_trk_g3_6 +(25 15) routing sp4_h_r_30 lc_trk_g3_6 +(25 15) routing sp4_h_r_46 lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 +(25 15) routing sp4_v_t_27 lc_trk_g3_6 +(25 15) routing tnl_op_6 lc_trk_g3_6 +(25 2) routing bnr_op_6 lc_trk_g0_6 +(25 2) routing lft_op_6 lc_trk_g0_6 +(25 2) routing sp12_h_l_5 lc_trk_g0_6 +(25 2) routing sp4_h_l_11 lc_trk_g0_6 +(25 2) routing sp4_h_l_3 lc_trk_g0_6 +(25 2) routing sp4_v_b_14 lc_trk_g0_6 +(25 2) routing sp4_v_b_6 lc_trk_g0_6 +(25 3) routing bnr_op_6 lc_trk_g0_6 +(25 3) routing sp12_h_l_5 lc_trk_g0_6 +(25 3) routing sp12_h_r_22 lc_trk_g0_6 +(25 3) routing sp4_h_l_11 lc_trk_g0_6 +(25 3) routing sp4_h_r_6 lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 +(25 3) routing sp4_v_b_14 lc_trk_g0_6 +(25 4) routing bnr_op_2 lc_trk_g1_2 +(25 4) routing lft_op_2 lc_trk_g1_2 +(25 4) routing sp12_h_r_2 lc_trk_g1_2 +(25 4) routing sp4_h_l_7 lc_trk_g1_2 +(25 4) routing sp4_h_r_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_2 lc_trk_g1_2 +(25 5) routing bnr_op_2 lc_trk_g1_2 +(25 5) routing sp12_h_l_17 lc_trk_g1_2 +(25 5) routing sp12_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_h_l_7 lc_trk_g1_2 +(25 5) routing sp4_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 +(25 5) routing sp4_v_b_10 lc_trk_g1_2 +(25 6) routing bnr_op_6 lc_trk_g1_6 +(25 6) routing lft_op_6 lc_trk_g1_6 +(25 6) routing sp12_h_l_5 lc_trk_g1_6 +(25 6) routing sp4_h_l_11 lc_trk_g1_6 +(25 6) routing sp4_h_l_3 lc_trk_g1_6 +(25 6) routing sp4_v_b_14 lc_trk_g1_6 +(25 6) routing sp4_v_b_6 lc_trk_g1_6 +(25 7) routing bnr_op_6 lc_trk_g1_6 +(25 7) routing sp12_h_l_5 lc_trk_g1_6 +(25 7) routing sp12_h_r_22 lc_trk_g1_6 +(25 7) routing sp4_h_l_11 lc_trk_g1_6 +(25 7) routing sp4_h_r_6 lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 +(25 7) routing sp4_v_b_14 lc_trk_g1_6 +(25 8) routing bnl_op_2 lc_trk_g2_2 +(25 8) routing rgt_op_2 lc_trk_g2_2 +(25 8) routing sp12_v_t_1 lc_trk_g2_2 +(25 8) routing sp4_h_r_34 lc_trk_g2_2 +(25 8) routing sp4_h_r_42 lc_trk_g2_2 +(25 8) routing sp4_v_b_26 lc_trk_g2_2 +(25 8) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing bnl_op_2 lc_trk_g2_2 +(25 9) routing sp12_v_t_1 lc_trk_g2_2 +(25 9) routing sp12_v_t_17 lc_trk_g2_2 +(25 9) routing sp4_h_l_15 lc_trk_g2_2 +(25 9) routing sp4_h_r_42 lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 +(25 9) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing tnl_op_2 lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(26 2) routing lc_trk_g0_5 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g0_7 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_4 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_6 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_5 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_7 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_4 wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_3 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_7 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_2 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_6 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_3 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_7 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_2 wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(26 4) routing lc_trk_g0_4 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g0_6 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_5 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_7 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_4 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_6 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_5 wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_2 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_6 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_3 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_7 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_2 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_6 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_3 wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(26 6) routing lc_trk_g0_5 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g0_7 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_4 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_6 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_5 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_7 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_4 wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_3 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_7 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_2 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_6 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_3 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_7 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_2 wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(27 0) routing lc_trk_g1_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(27 3) routing lc_trk_g1_0 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_2 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_4 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_6 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_0 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_2 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_4 wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(27 4) routing lc_trk_g1_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(27 5) routing lc_trk_g1_1 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_3 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_5 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_7 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_1 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_3 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_5 wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(27 6) routing lc_trk_g1_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(27 7) routing lc_trk_g1_0 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_2 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_4 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_6 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_0 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_2 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_4 wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(27 8) routing lc_trk_g1_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(28 0) routing lc_trk_g2_1 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(28 3) routing lc_trk_g2_1 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_3 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_5 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_7 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_0 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_2 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_4 wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_6 wire_mult/lc_1/in_0 +(28 4) routing lc_trk_g2_1 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(28 5) routing lc_trk_g2_0 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_2 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_4 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_6 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_1 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_3 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_5 wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_7 wire_mult/lc_2/in_0 +(28 6) routing lc_trk_g2_0 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(28 7) routing lc_trk_g2_1 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_3 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_5 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_7 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_0 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_2 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_4 wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_6 wire_mult/lc_3/in_0 +(28 8) routing lc_trk_g2_1 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_6 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_6 wire_mult/lc_1/in_0 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_7 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_7 wire_mult/lc_2/in_0 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_6 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_6 wire_mult/lc_3/in_0 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(3 0) routing sp12_h_r_0 sp12_v_b_0 +(3 0) routing sp12_v_t_23 sp12_v_b_0 +(3 1) routing sp12_h_l_23 sp12_v_b_0 +(3 1) routing sp12_h_r_0 sp12_v_b_0 +(3 10) routing sp12_v_t_22 sp12_h_l_22 +(3 11) routing sp12_v_b_1 sp12_h_l_22 +(3 12) routing sp12_v_b_1 sp12_h_r_1 +(3 12) routing sp12_v_t_22 sp12_h_r_1 +(3 13) routing sp12_h_l_22 sp12_h_r_1 +(3 13) routing sp12_v_b_1 sp12_h_r_1 +(3 14) routing sp12_h_r_1 sp12_v_t_22 +(3 14) routing sp12_v_b_1 sp12_v_t_22 +(3 15) routing sp12_h_l_22 sp12_v_t_22 +(3 15) routing sp12_h_r_1 sp12_v_t_22 +(3 2) routing sp12_h_r_0 sp12_h_l_23 +(3 2) routing sp12_v_t_23 sp12_h_l_23 +(3 3) routing sp12_h_r_0 sp12_h_l_23 +(3 3) routing sp12_v_b_0 sp12_h_l_23 +(3 4) routing sp12_v_b_0 sp12_h_r_0 +(3 4) routing sp12_v_t_23 sp12_h_r_0 +(3 5) routing sp12_h_l_23 sp12_h_r_0 +(3 5) routing sp12_v_b_0 sp12_h_r_0 +(3 6) routing sp12_h_r_0 sp12_v_t_23 +(3 6) routing sp12_v_b_0 sp12_v_t_23 +(3 7) routing sp12_h_l_23 sp12_v_t_23 +(3 7) routing sp12_h_r_0 sp12_v_t_23 +(3 8) routing sp12_h_r_1 sp12_v_b_1 +(3 8) routing sp12_v_t_22 sp12_v_b_1 +(3 9) routing sp12_h_l_22 sp12_v_b_1 +(3 9) routing sp12_h_r_1 sp12_v_b_1 +(30 0) routing lc_trk_g0_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 sp4_v_b_0 +(4 0) routing sp4_h_l_43 sp4_v_b_0 +(4 0) routing sp4_v_t_37 sp4_v_b_0 +(4 0) routing sp4_v_t_41 sp4_v_b_0 +(4 1) routing sp4_h_l_41 sp4_h_r_0 +(4 1) routing sp4_v_b_6 sp4_h_r_0 +(4 1) routing sp4_v_t_42 sp4_h_r_0 +(4 10) routing sp4_h_r_0 sp4_v_t_43 +(4 10) routing sp4_h_r_6 sp4_v_t_43 +(4 10) routing sp4_v_b_10 sp4_v_t_43 +(4 10) routing sp4_v_b_6 sp4_v_t_43 +(4 11) routing sp4_h_r_10 sp4_h_l_43 +(4 11) routing sp4_v_b_1 sp4_h_l_43 +(4 11) routing sp4_v_t_37 sp4_h_l_43 +(4 12) routing sp4_h_l_38 sp4_v_b_9 +(4 12) routing sp4_h_l_44 sp4_v_b_9 +(4 12) routing sp4_v_t_36 sp4_v_b_9 +(4 12) routing sp4_v_t_44 sp4_v_b_9 +(4 13) routing sp4_v_b_3 sp4_h_r_9 +(4 13) routing sp4_v_t_41 sp4_h_r_9 +(4 14) routing sp4_h_r_3 sp4_v_t_44 +(4 14) routing sp4_h_r_9 sp4_v_t_44 +(4 14) routing sp4_v_b_1 sp4_v_t_44 +(4 14) routing sp4_v_b_9 sp4_v_t_44 +(4 15) routing sp4_h_r_1 sp4_h_l_44 +(4 15) routing sp4_h_r_6 sp4_h_l_44 +(4 15) routing sp4_v_b_4 sp4_h_l_44 +(4 15) routing sp4_v_t_38 sp4_h_l_44 +(4 2) routing sp4_h_r_0 sp4_v_t_37 +(4 2) routing sp4_h_r_6 sp4_v_t_37 +(4 2) routing sp4_v_b_0 sp4_v_t_37 +(4 2) routing sp4_v_b_4 sp4_v_t_37 +(4 3) routing sp4_h_r_4 sp4_h_l_37 +(4 3) routing sp4_v_b_7 sp4_h_l_37 +(4 3) routing sp4_v_t_43 sp4_h_l_37 +(4 4) routing sp4_h_l_38 sp4_v_b_3 +(4 4) routing sp4_h_l_44 sp4_v_b_3 +(4 4) routing sp4_v_t_38 sp4_v_b_3 +(4 4) routing sp4_v_t_42 sp4_v_b_3 +(4 5) routing sp4_v_b_9 sp4_h_r_3 +(4 5) routing sp4_v_t_47 sp4_h_r_3 +(4 6) routing sp4_h_r_3 sp4_v_t_38 +(4 6) routing sp4_h_r_9 sp4_v_t_38 +(4 6) routing sp4_v_b_3 sp4_v_t_38 +(4 6) routing sp4_v_b_7 sp4_v_t_38 +(4 7) routing sp4_h_r_0 sp4_h_l_38 +(4 7) routing sp4_v_b_10 sp4_h_l_38 +(4 7) routing sp4_v_t_44 sp4_h_l_38 +(4 8) routing sp4_h_l_37 sp4_v_b_6 +(4 8) routing sp4_h_l_43 sp4_v_b_6 +(4 8) routing sp4_v_t_43 sp4_v_b_6 +(4 8) routing sp4_v_t_47 sp4_v_b_6 +(4 9) routing sp4_v_b_0 sp4_h_r_6 +(4 9) routing sp4_v_t_36 sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_24 sp4_h_l_5 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_24 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_29 sp4_h_l_15 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_29 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_30 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_30 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_31 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_31 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_25 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_25 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_26 sp4_h_r_20 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_26 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_27 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_27 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_28 sp4_h_l_13 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_28 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_24 sp12_h_r_8 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_24 sp4_h_r_32 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_29 sp12_h_r_2 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_29 sp4_h_r_42 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_30 sp12_h_r_4 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_30 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_31 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_31 sp4_h_r_46 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_25 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_25 sp4_h_r_34 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_26 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_26 sp4_h_l_25 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_27 sp12_h_r_14 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_27 sp4_h_l_27 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_28 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_28 sp4_h_r_40 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_24 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_24 sp4_v_t_5 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_29 sp12_h_l_17 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_29 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_30 sp12_h_r_20 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_30 sp4_v_t_1 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_31 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_31 sp4_v_b_14 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_25 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_25 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_26 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_26 sp4_v_b_20 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_27 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_27 sp4_v_b_22 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_28 sp12_h_r_16 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_28 sp4_v_b_8 +(5 0) routing sp4_v_b_0 sp4_h_r_0 +(5 0) routing sp4_v_b_6 sp4_h_r_0 +(5 1) routing sp4_h_l_37 sp4_v_b_0 +(5 1) routing sp4_h_l_43 sp4_v_b_0 +(5 1) routing sp4_h_r_0 sp4_v_b_0 +(5 1) routing sp4_v_t_44 sp4_v_b_0 +(5 10) routing sp4_v_b_6 sp4_h_l_43 +(5 10) routing sp4_v_t_37 sp4_h_l_43 +(5 10) routing sp4_v_t_43 sp4_h_l_43 +(5 11) routing sp4_h_l_43 sp4_v_t_43 +(5 11) routing sp4_h_r_0 sp4_v_t_43 +(5 11) routing sp4_h_r_6 sp4_v_t_43 +(5 11) routing sp4_v_b_3 sp4_v_t_43 +(5 12) routing sp4_v_b_3 sp4_h_r_9 +(5 12) routing sp4_v_b_9 sp4_h_r_9 +(5 12) routing sp4_v_t_44 sp4_h_r_9 +(5 13) routing sp4_h_l_38 sp4_v_b_9 +(5 13) routing sp4_h_l_44 sp4_v_b_9 +(5 13) routing sp4_v_t_43 sp4_v_b_9 +(5 14) routing sp4_h_r_6 sp4_h_l_44 +(5 14) routing sp4_v_b_9 sp4_h_l_44 +(5 14) routing sp4_v_t_38 sp4_h_l_44 +(5 15) routing sp4_h_l_44 sp4_v_t_44 +(5 15) routing sp4_h_r_3 sp4_v_t_44 +(5 15) routing sp4_h_r_9 sp4_v_t_44 +(5 15) routing sp4_v_b_6 sp4_v_t_44 +(5 2) routing sp4_v_b_0 sp4_h_l_37 +(5 2) routing sp4_v_t_37 sp4_h_l_37 +(5 2) routing sp4_v_t_43 sp4_h_l_37 +(5 3) routing sp4_h_l_37 sp4_v_t_37 +(5 3) routing sp4_h_r_0 sp4_v_t_37 +(5 3) routing sp4_h_r_6 sp4_v_t_37 +(5 3) routing sp4_v_b_9 sp4_v_t_37 +(5 4) routing sp4_v_b_3 sp4_h_r_3 +(5 4) routing sp4_v_b_9 sp4_h_r_3 +(5 4) routing sp4_v_t_38 sp4_h_r_3 +(5 5) routing sp4_h_l_38 sp4_v_b_3 +(5 5) routing sp4_h_l_44 sp4_v_b_3 +(5 5) routing sp4_h_r_3 sp4_v_b_3 +(5 5) routing sp4_v_t_37 sp4_v_b_3 +(5 6) routing sp4_h_r_0 sp4_h_l_38 +(5 6) routing sp4_v_b_3 sp4_h_l_38 +(5 6) routing sp4_v_t_38 sp4_h_l_38 +(5 6) routing sp4_v_t_44 sp4_h_l_38 +(5 7) routing sp4_h_l_38 sp4_v_t_38 +(5 7) routing sp4_h_r_3 sp4_v_t_38 +(5 7) routing sp4_h_r_9 sp4_v_t_38 +(5 7) routing sp4_v_b_0 sp4_v_t_38 +(5 8) routing sp4_v_b_0 sp4_h_r_6 +(5 8) routing sp4_v_b_6 sp4_h_r_6 +(5 8) routing sp4_v_t_43 sp4_h_r_6 +(5 9) routing sp4_h_l_37 sp4_v_b_6 +(5 9) routing sp4_h_l_43 sp4_v_b_6 +(5 9) routing sp4_h_r_6 sp4_v_b_6 +(5 9) routing sp4_v_t_38 sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT3_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT3_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT3_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT3_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT3_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT3_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT3_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT3_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_24 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_24 sp4_v_b_32 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_29 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_29 sp4_v_b_26 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_30 sp4_v_b_44 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_30 sp4_v_b_28 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_31 sp4_v_b_46 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_31 sp4_v_t_19 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_25 sp12_v_t_1 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_25 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_26 sp12_v_t_3 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_26 sp4_v_t_25 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_27 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_27 sp4_v_t_27 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_28 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_28 sp4_v_t_13 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_24 sp12_v_b_16 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_24 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_29 sp12_v_t_9 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_29 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_30 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_30 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_31 sp12_v_t_13 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_31 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_25 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_25 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_26 sp12_v_b_20 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_26 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_27 sp12_v_b_22 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_27 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_28 sp12_v_t_7 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_28 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_24 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_24 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_29 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_29 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_30 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_30 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_31 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_31 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_25 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_25 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_26 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_26 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_27 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_27 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_28 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_28 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 sp4_v_b_0 +(6 0) routing sp4_h_r_7 sp4_v_b_0 +(6 0) routing sp4_v_t_41 sp4_v_b_0 +(6 0) routing sp4_v_t_44 sp4_v_b_0 +(6 1) routing sp4_h_l_41 sp4_h_r_0 +(6 1) routing sp4_v_b_0 sp4_h_r_0 +(6 1) routing sp4_v_b_6 sp4_h_r_0 +(6 10) routing sp4_h_l_36 sp4_v_t_43 +(6 10) routing sp4_h_r_0 sp4_v_t_43 +(6 10) routing sp4_v_b_10 sp4_v_t_43 +(6 10) routing sp4_v_b_3 sp4_v_t_43 +(6 11) routing sp4_h_r_10 sp4_h_l_43 +(6 11) routing sp4_h_r_6 sp4_h_l_43 +(6 11) routing sp4_v_t_37 sp4_h_l_43 +(6 11) routing sp4_v_t_43 sp4_h_l_43 +(6 12) routing sp4_h_l_38 sp4_v_b_9 +(6 12) routing sp4_h_r_4 sp4_v_b_9 +(6 12) routing sp4_v_t_36 sp4_v_b_9 +(6 12) routing sp4_v_t_43 sp4_v_b_9 +(6 13) routing sp4_v_b_3 sp4_h_r_9 +(6 13) routing sp4_v_b_9 sp4_h_r_9 +(6 14) routing sp4_h_l_41 sp4_v_t_44 +(6 14) routing sp4_h_r_3 sp4_v_t_44 +(6 14) routing sp4_v_b_1 sp4_v_t_44 +(6 14) routing sp4_v_b_6 sp4_v_t_44 +(6 15) routing sp4_h_r_1 sp4_h_l_44 +(6 15) routing sp4_v_t_38 sp4_h_l_44 +(6 2) routing sp4_h_l_42 sp4_v_t_37 +(6 2) routing sp4_h_r_6 sp4_v_t_37 +(6 2) routing sp4_v_b_4 sp4_v_t_37 +(6 2) routing sp4_v_b_9 sp4_v_t_37 +(6 3) routing sp4_h_r_0 sp4_h_l_37 +(6 3) routing sp4_h_r_4 sp4_h_l_37 +(6 3) routing sp4_v_t_37 sp4_h_l_37 +(6 3) routing sp4_v_t_43 sp4_h_l_37 +(6 4) routing sp4_h_l_44 sp4_v_b_3 +(6 4) routing sp4_h_r_10 sp4_v_b_3 +(6 4) routing sp4_v_t_37 sp4_v_b_3 +(6 4) routing sp4_v_t_42 sp4_v_b_3 +(6 5) routing sp4_v_b_3 sp4_h_r_3 +(6 5) routing sp4_v_b_9 sp4_h_r_3 +(6 6) routing sp4_h_l_47 sp4_v_t_38 +(6 6) routing sp4_h_r_9 sp4_v_t_38 +(6 6) routing sp4_v_b_0 sp4_v_t_38 +(6 6) routing sp4_v_b_7 sp4_v_t_38 +(6 7) routing sp4_v_t_38 sp4_h_l_38 +(6 7) routing sp4_v_t_44 sp4_h_l_38 +(6 8) routing sp4_h_l_37 sp4_v_b_6 +(6 8) routing sp4_h_r_1 sp4_v_b_6 +(6 8) routing sp4_v_t_38 sp4_v_b_6 +(6 8) routing sp4_v_t_47 sp4_v_b_6 +(6 9) routing sp4_v_b_0 sp4_h_r_6 +(6 9) routing sp4_v_b_6 sp4_h_r_6 +(7 1) MAC16 functional bit: MULT3_bram_cbit_0 +(7 10) Column buffer control bit: MULT3_colbuf_cntl_3 +(7 11) Column buffer control bit: MULT3_colbuf_cntl_2 +(7 12) Column buffer control bit: MULT3_colbuf_cntl_5 +(7 13) Column buffer control bit: MULT3_colbuf_cntl_4 +(7 14) Column buffer control bit: MULT3_colbuf_cntl_7 +(7 15) Column buffer control bit: MULT3_colbuf_cntl_6 +(7 8) Column buffer control bit: MULT3_colbuf_cntl_1 +(7 9) Column buffer control bit: MULT3_colbuf_cntl_0 +(8 0) routing sp4_h_l_40 sp4_h_r_1 +(8 0) routing sp4_v_b_1 sp4_h_r_1 +(8 0) routing sp4_v_b_7 sp4_h_r_1 +(8 1) routing sp4_h_l_36 sp4_v_b_1 +(8 1) routing sp4_h_l_42 sp4_v_b_1 +(8 1) routing sp4_h_r_1 sp4_v_b_1 +(8 1) routing sp4_v_t_47 sp4_v_b_1 +(8 10) routing sp4_v_t_36 sp4_h_l_42 +(8 10) routing sp4_v_t_42 sp4_h_l_42 +(8 11) routing sp4_h_l_42 sp4_v_t_42 +(8 11) routing sp4_h_r_1 sp4_v_t_42 +(8 11) routing sp4_h_r_7 sp4_v_t_42 +(8 11) routing sp4_v_b_4 sp4_v_t_42 +(8 12) routing sp4_v_b_10 sp4_h_r_10 +(8 12) routing sp4_v_b_4 sp4_h_r_10 +(8 13) routing sp4_h_l_41 sp4_v_b_10 +(8 13) routing sp4_h_l_47 sp4_v_b_10 +(8 13) routing sp4_h_r_10 sp4_v_b_10 +(8 13) routing sp4_v_t_42 sp4_v_b_10 +(8 14) routing sp4_h_r_10 sp4_h_l_47 +(8 14) routing sp4_h_r_2 sp4_h_l_47 +(8 14) routing sp4_v_t_41 sp4_h_l_47 +(8 14) routing sp4_v_t_47 sp4_h_l_47 +(8 15) routing sp4_h_l_47 sp4_v_t_47 +(8 15) routing sp4_h_r_10 sp4_v_t_47 +(8 15) routing sp4_h_r_4 sp4_v_t_47 +(8 15) routing sp4_v_b_7 sp4_v_t_47 +(8 2) routing sp4_h_r_1 sp4_h_l_36 +(8 2) routing sp4_v_t_42 sp4_h_l_36 +(8 3) routing sp4_h_l_36 sp4_v_t_36 +(8 3) routing sp4_h_r_1 sp4_v_t_36 +(8 3) routing sp4_h_r_7 sp4_v_t_36 +(8 3) routing sp4_v_b_10 sp4_v_t_36 +(8 4) routing sp4_h_l_45 sp4_h_r_4 +(8 4) routing sp4_v_b_10 sp4_h_r_4 +(8 4) routing sp4_v_b_4 sp4_h_r_4 +(8 5) routing sp4_h_l_41 sp4_v_b_4 +(8 5) routing sp4_h_l_47 sp4_v_b_4 +(8 5) routing sp4_h_r_4 sp4_v_b_4 +(8 5) routing sp4_v_t_36 sp4_v_b_4 +(8 6) routing sp4_h_r_4 sp4_h_l_41 +(8 6) routing sp4_h_r_8 sp4_h_l_41 +(8 6) routing sp4_v_t_41 sp4_h_l_41 +(8 6) routing sp4_v_t_47 sp4_h_l_41 +(8 7) routing sp4_h_l_41 sp4_v_t_41 +(8 7) routing sp4_h_r_10 sp4_v_t_41 +(8 7) routing sp4_h_r_4 sp4_v_t_41 +(8 7) routing sp4_v_b_1 sp4_v_t_41 +(8 8) routing sp4_h_l_46 sp4_h_r_7 +(8 8) routing sp4_v_b_1 sp4_h_r_7 +(8 8) routing sp4_v_b_7 sp4_h_r_7 +(8 9) routing sp4_h_l_36 sp4_v_b_7 +(8 9) routing sp4_h_l_42 sp4_v_b_7 +(8 9) routing sp4_h_r_7 sp4_v_b_7 +(8 9) routing sp4_v_t_41 sp4_v_b_7 +(9 0) routing sp4_v_b_1 sp4_h_r_1 +(9 0) routing sp4_v_b_7 sp4_h_r_1 +(9 0) routing sp4_v_t_36 sp4_h_r_1 +(9 1) routing sp4_h_l_36 sp4_v_b_1 +(9 1) routing sp4_h_l_42 sp4_v_b_1 +(9 1) routing sp4_v_t_36 sp4_v_b_1 +(9 1) routing sp4_v_t_40 sp4_v_b_1 +(9 10) routing sp4_h_r_4 sp4_h_l_42 +(9 10) routing sp4_v_b_7 sp4_h_l_42 +(9 10) routing sp4_v_t_36 sp4_h_l_42 +(9 10) routing sp4_v_t_42 sp4_h_l_42 +(9 11) routing sp4_h_r_1 sp4_v_t_42 +(9 11) routing sp4_h_r_7 sp4_v_t_42 +(9 11) routing sp4_v_b_11 sp4_v_t_42 +(9 11) routing sp4_v_b_7 sp4_v_t_42 +(9 12) routing sp4_h_l_42 sp4_h_r_10 +(9 12) routing sp4_v_b_10 sp4_h_r_10 +(9 12) routing sp4_v_b_4 sp4_h_r_10 +(9 12) routing sp4_v_t_47 sp4_h_r_10 +(9 13) routing sp4_h_l_41 sp4_v_b_10 +(9 13) routing sp4_h_l_47 sp4_v_b_10 +(9 13) routing sp4_v_t_39 sp4_v_b_10 +(9 13) routing sp4_v_t_47 sp4_v_b_10 +(9 14) routing sp4_v_b_10 sp4_h_l_47 +(9 14) routing sp4_v_t_41 sp4_h_l_47 +(9 14) routing sp4_v_t_47 sp4_h_l_47 +(9 15) routing sp4_h_r_10 sp4_v_t_47 +(9 15) routing sp4_h_r_4 sp4_v_t_47 +(9 15) routing sp4_v_b_10 sp4_v_t_47 +(9 15) routing sp4_v_b_2 sp4_v_t_47 +(9 2) routing sp4_h_r_10 sp4_h_l_36 +(9 2) routing sp4_v_b_1 sp4_h_l_36 +(9 2) routing sp4_v_t_42 sp4_h_l_36 +(9 3) routing sp4_h_r_1 sp4_v_t_36 +(9 3) routing sp4_h_r_7 sp4_v_t_36 +(9 3) routing sp4_v_b_1 sp4_v_t_36 +(9 3) routing sp4_v_b_5 sp4_v_t_36 +(9 4) routing sp4_v_b_10 sp4_h_r_4 +(9 4) routing sp4_v_b_4 sp4_h_r_4 +(9 4) routing sp4_v_t_41 sp4_h_r_4 +(9 5) routing sp4_h_l_41 sp4_v_b_4 +(9 5) routing sp4_h_l_47 sp4_v_b_4 +(9 5) routing sp4_v_t_41 sp4_v_b_4 +(9 5) routing sp4_v_t_45 sp4_v_b_4 +(9 6) routing sp4_v_b_4 sp4_h_l_41 +(9 6) routing sp4_v_t_41 sp4_h_l_41 +(9 6) routing sp4_v_t_47 sp4_h_l_41 +(9 7) routing sp4_h_r_10 sp4_v_t_41 +(9 7) routing sp4_h_r_4 sp4_v_t_41 +(9 7) routing sp4_v_b_4 sp4_v_t_41 +(9 7) routing sp4_v_b_8 sp4_v_t_41 +(9 8) routing sp4_h_l_41 sp4_h_r_7 +(9 8) routing sp4_v_b_1 sp4_h_r_7 +(9 8) routing sp4_v_b_7 sp4_h_r_7 +(9 8) routing sp4_v_t_42 sp4_h_r_7 +(9 9) routing sp4_h_l_36 sp4_v_b_7 +(9 9) routing sp4_h_l_42 sp4_v_b_7 +(9 9) routing sp4_v_t_42 sp4_v_b_7 +(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/cached_ipcon_5k.txt b/icefuzz/cached_ipcon_5k.txt index e69de29..6667a0a 100644 --- a/icefuzz/cached_ipcon_5k.txt +++ b/icefuzz/cached_ipcon_5k.txt @@ -0,0 +1,3471 @@ +(0 10) routing glb_netwk_2 glb2local_2 +(0 10) routing glb_netwk_3 glb2local_2 +(0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 +(0 11) routing glb_netwk_3 glb2local_2 +(0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_2 glb2local_3 +(0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 +(0 13) routing glb_netwk_1 glb2local_3 +(0 13) routing glb_netwk_3 glb2local_3 +(0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 +(0 2) routing glb_netwk_2 clk +(0 2) routing glb_netwk_3 clk +(0 2) routing glb_netwk_6 clk +(0 2) routing glb_netwk_7 clk +(0 2) routing lc_trk_g2_0 clk +(0 2) routing lc_trk_g3_1 clk +(0 3) routing glb_netwk_1 clk +(0 3) routing glb_netwk_3 clk +(0 3) routing glb_netwk_5 clk +(0 3) routing glb_netwk_7 clk +(0 3) routing lc_trk_g1_1 clk +(0 3) routing lc_trk_g3_1 clk +(0 6) routing glb_netwk_2 glb2local_0 +(0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 +(0 7) routing glb_netwk_1 glb2local_0 +(0 7) routing glb_netwk_3 glb2local_0 +(0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_2 glb2local_1 +(0 8) routing glb_netwk_3 glb2local_1 +(0 8) routing glb_netwk_6 glb2local_1 +(0 8) routing glb_netwk_7 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 +(0 9) routing glb_netwk_5 glb2local_1 +(0 9) routing glb_netwk_7 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 glb2local_2 +(1 11) routing glb_netwk_5 glb2local_2 +(1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 +(1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 2) routing glb_netwk_4 clk +(1 2) routing glb_netwk_5 clk +(1 2) routing glb_netwk_6 clk +(1 2) routing glb_netwk_7 clk +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 +(1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 +(1 9) routing glb_netwk_5 glb2local_1 +(1 9) routing glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_7 glb2local_1 +(10 0) routing sp4_h_l_40 sp4_h_r_1 +(10 0) routing sp4_h_l_47 sp4_h_r_1 +(10 0) routing sp4_v_b_7 sp4_h_r_1 +(10 0) routing sp4_v_t_45 sp4_h_r_1 +(10 1) routing sp4_h_l_42 sp4_v_b_1 +(10 1) routing sp4_h_r_8 sp4_v_b_1 +(10 1) routing sp4_v_t_40 sp4_v_b_1 +(10 1) routing sp4_v_t_47 sp4_v_b_1 +(10 10) routing sp4_h_r_11 sp4_h_l_42 +(10 10) routing sp4_h_r_4 sp4_h_l_42 +(10 10) routing sp4_v_b_2 sp4_h_l_42 +(10 10) routing sp4_v_t_36 sp4_h_l_42 +(10 11) routing sp4_h_l_39 sp4_v_t_42 +(10 11) routing sp4_h_r_1 sp4_v_t_42 +(10 11) routing sp4_v_b_11 sp4_v_t_42 +(10 11) routing sp4_v_b_4 sp4_v_t_42 +(10 12) routing sp4_h_l_42 sp4_h_r_10 +(10 12) routing sp4_v_b_4 sp4_h_r_10 +(10 12) routing sp4_v_t_40 sp4_h_r_10 +(10 13) routing sp4_h_l_41 sp4_v_b_10 +(10 13) routing sp4_h_r_5 sp4_v_b_10 +(10 13) routing sp4_v_t_39 sp4_v_b_10 +(10 13) routing sp4_v_t_42 sp4_v_b_10 +(10 14) routing sp4_h_r_2 sp4_h_l_47 +(10 14) routing sp4_v_b_5 sp4_h_l_47 +(10 14) routing sp4_v_t_41 sp4_h_l_47 +(10 15) routing sp4_h_l_40 sp4_v_t_47 +(10 15) routing sp4_h_r_4 sp4_v_t_47 +(10 15) routing sp4_v_b_2 sp4_v_t_47 +(10 15) routing sp4_v_b_7 sp4_v_t_47 +(10 2) routing sp4_h_r_10 sp4_h_l_36 +(10 2) routing sp4_h_r_5 sp4_h_l_36 +(10 2) routing sp4_v_b_8 sp4_h_l_36 +(10 2) routing sp4_v_t_42 sp4_h_l_36 +(10 3) routing sp4_h_l_45 sp4_v_t_36 +(10 3) routing sp4_h_r_7 sp4_v_t_36 +(10 3) routing sp4_v_b_10 sp4_v_t_36 +(10 3) routing sp4_v_b_5 sp4_v_t_36 +(10 4) routing sp4_h_l_36 sp4_h_r_4 +(10 4) routing sp4_h_l_45 sp4_h_r_4 +(10 4) routing sp4_v_b_10 sp4_h_r_4 +(10 4) routing sp4_v_t_46 sp4_h_r_4 +(10 5) routing sp4_h_l_47 sp4_v_b_4 +(10 5) routing sp4_h_r_11 sp4_v_b_4 +(10 5) routing sp4_v_t_36 sp4_v_b_4 +(10 5) routing sp4_v_t_45 sp4_v_b_4 +(10 6) routing sp4_h_r_1 sp4_h_l_41 +(10 6) routing sp4_h_r_8 sp4_h_l_41 +(10 6) routing sp4_v_b_11 sp4_h_l_41 +(10 6) routing sp4_v_t_47 sp4_h_l_41 +(10 7) routing sp4_h_l_46 sp4_v_t_41 +(10 7) routing sp4_h_r_10 sp4_v_t_41 +(10 7) routing sp4_v_b_1 sp4_v_t_41 +(10 7) routing sp4_v_b_8 sp4_v_t_41 +(10 8) routing sp4_h_l_41 sp4_h_r_7 +(10 8) routing sp4_h_l_46 sp4_h_r_7 +(10 8) routing sp4_v_b_1 sp4_h_r_7 +(10 8) routing sp4_v_t_39 sp4_h_r_7 +(10 9) routing sp4_h_l_36 sp4_v_b_7 +(10 9) routing sp4_h_r_2 sp4_v_b_7 +(10 9) routing sp4_v_t_41 sp4_v_b_7 +(10 9) routing sp4_v_t_46 sp4_v_b_7 +(11 0) routing sp4_h_l_45 sp4_v_b_2 +(11 0) routing sp4_h_r_9 sp4_v_b_2 +(11 0) routing sp4_v_t_43 sp4_v_b_2 +(11 0) routing sp4_v_t_46 sp4_v_b_2 +(11 1) routing sp4_h_l_39 sp4_h_r_2 +(11 1) routing sp4_h_l_43 sp4_h_r_2 +(11 1) routing sp4_v_b_2 sp4_h_r_2 +(11 1) routing sp4_v_b_8 sp4_h_r_2 +(11 10) routing sp4_h_l_38 sp4_v_t_45 +(11 10) routing sp4_h_r_2 sp4_v_t_45 +(11 10) routing sp4_v_b_0 sp4_v_t_45 +(11 10) routing sp4_v_b_5 sp4_v_t_45 +(11 11) routing sp4_h_r_0 sp4_h_l_45 +(11 11) routing sp4_h_r_8 sp4_h_l_45 +(11 11) routing sp4_v_t_39 sp4_h_l_45 +(11 11) routing sp4_v_t_45 sp4_h_l_45 +(11 12) routing sp4_h_l_40 sp4_v_b_11 +(11 12) routing sp4_h_r_6 sp4_v_b_11 +(11 12) routing sp4_v_t_38 sp4_v_b_11 +(11 12) routing sp4_v_t_45 sp4_v_b_11 +(11 13) routing sp4_h_l_46 sp4_h_r_11 +(11 13) routing sp4_v_b_11 sp4_h_r_11 +(11 13) routing sp4_v_b_5 sp4_h_r_11 +(11 14) routing sp4_h_l_43 sp4_v_t_46 +(11 14) routing sp4_h_r_5 sp4_v_t_46 +(11 14) routing sp4_v_b_3 sp4_v_t_46 +(11 14) routing sp4_v_b_8 sp4_v_t_46 +(11 15) routing sp4_h_r_11 sp4_h_l_46 +(11 15) routing sp4_h_r_3 sp4_h_l_46 +(11 15) routing sp4_v_t_40 sp4_h_l_46 +(11 15) routing sp4_v_t_46 sp4_h_l_46 +(11 2) routing sp4_h_l_44 sp4_v_t_39 +(11 2) routing sp4_h_r_8 sp4_v_t_39 +(11 2) routing sp4_v_b_11 sp4_v_t_39 +(11 2) routing sp4_v_b_6 sp4_v_t_39 +(11 3) routing sp4_h_r_2 sp4_h_l_39 +(11 3) routing sp4_h_r_6 sp4_h_l_39 +(11 3) routing sp4_v_t_39 sp4_h_l_39 +(11 3) routing sp4_v_t_45 sp4_h_l_39 +(11 4) routing sp4_h_l_46 sp4_v_b_5 +(11 4) routing sp4_h_r_0 sp4_v_b_5 +(11 4) routing sp4_v_t_39 sp4_v_b_5 +(11 4) routing sp4_v_t_44 sp4_v_b_5 +(11 5) routing sp4_h_l_40 sp4_h_r_5 +(11 5) routing sp4_h_l_44 sp4_h_r_5 +(11 5) routing sp4_v_b_11 sp4_h_r_5 +(11 5) routing sp4_v_b_5 sp4_h_r_5 +(11 6) routing sp4_h_l_37 sp4_v_t_40 +(11 6) routing sp4_h_r_11 sp4_v_t_40 +(11 6) routing sp4_v_b_2 sp4_v_t_40 +(11 6) routing sp4_v_b_9 sp4_v_t_40 +(11 7) routing sp4_v_t_40 sp4_h_l_40 +(11 7) routing sp4_v_t_46 sp4_h_l_40 +(11 8) routing sp4_h_l_39 sp4_v_b_8 +(11 8) routing sp4_h_r_3 sp4_v_b_8 +(11 8) routing sp4_v_t_37 sp4_v_b_8 +(11 8) routing sp4_v_t_40 sp4_v_b_8 +(11 9) routing sp4_h_l_37 sp4_h_r_8 +(11 9) routing sp4_h_l_45 sp4_h_r_8 +(11 9) routing sp4_v_b_2 sp4_h_r_8 +(11 9) routing sp4_v_b_8 sp4_h_r_8 +(12 0) routing sp4_h_l_46 sp4_h_r_2 +(12 0) routing sp4_v_b_2 sp4_h_r_2 +(12 0) routing sp4_v_b_8 sp4_h_r_2 +(12 0) routing sp4_v_t_39 sp4_h_r_2 +(12 1) routing sp4_h_l_39 sp4_v_b_2 +(12 1) routing sp4_h_l_45 sp4_v_b_2 +(12 1) routing sp4_h_r_2 sp4_v_b_2 +(12 1) routing sp4_v_t_46 sp4_v_b_2 +(12 10) routing sp4_v_b_8 sp4_h_l_45 +(12 10) routing sp4_v_t_39 sp4_h_l_45 +(12 10) routing sp4_v_t_45 sp4_h_l_45 +(12 11) routing sp4_h_l_45 sp4_v_t_45 +(12 11) routing sp4_h_r_2 sp4_v_t_45 +(12 11) routing sp4_h_r_8 sp4_v_t_45 +(12 11) routing sp4_v_b_5 sp4_v_t_45 +(12 12) routing sp4_h_l_45 sp4_h_r_11 +(12 12) routing sp4_v_b_11 sp4_h_r_11 +(12 12) routing sp4_v_b_5 sp4_h_r_11 +(12 12) routing sp4_v_t_46 sp4_h_r_11 +(12 13) routing sp4_h_l_40 sp4_v_b_11 +(12 13) routing sp4_h_l_46 sp4_v_b_11 +(12 13) routing sp4_h_r_11 sp4_v_b_11 +(12 13) routing sp4_v_t_45 sp4_v_b_11 +(12 14) routing sp4_h_r_8 sp4_h_l_46 +(12 14) routing sp4_v_b_11 sp4_h_l_46 +(12 14) routing sp4_v_t_40 sp4_h_l_46 +(12 14) routing sp4_v_t_46 sp4_h_l_46 +(12 15) routing sp4_h_l_46 sp4_v_t_46 +(12 15) routing sp4_h_r_11 sp4_v_t_46 +(12 15) routing sp4_h_r_5 sp4_v_t_46 +(12 15) routing sp4_v_b_8 sp4_v_t_46 +(12 2) routing sp4_v_b_2 sp4_h_l_39 +(12 2) routing sp4_v_t_39 sp4_h_l_39 +(12 2) routing sp4_v_t_45 sp4_h_l_39 +(12 3) routing sp4_h_l_39 sp4_v_t_39 +(12 3) routing sp4_h_r_2 sp4_v_t_39 +(12 3) routing sp4_h_r_8 sp4_v_t_39 +(12 3) routing sp4_v_b_11 sp4_v_t_39 +(12 4) routing sp4_h_l_39 sp4_h_r_5 +(12 4) routing sp4_v_b_11 sp4_h_r_5 +(12 4) routing sp4_v_b_5 sp4_h_r_5 +(12 4) routing sp4_v_t_40 sp4_h_r_5 +(12 5) routing sp4_h_l_40 sp4_v_b_5 +(12 5) routing sp4_h_l_46 sp4_v_b_5 +(12 5) routing sp4_h_r_5 sp4_v_b_5 +(12 5) routing sp4_v_t_39 sp4_v_b_5 +(12 6) routing sp4_h_r_2 sp4_h_l_40 +(12 6) routing sp4_v_b_5 sp4_h_l_40 +(12 6) routing sp4_v_t_40 sp4_h_l_40 +(12 6) routing sp4_v_t_46 sp4_h_l_40 +(12 7) routing sp4_h_l_40 sp4_v_t_40 +(12 7) routing sp4_h_r_11 sp4_v_t_40 +(12 7) routing sp4_h_r_5 sp4_v_t_40 +(12 7) routing sp4_v_b_2 sp4_v_t_40 +(12 8) routing sp4_h_l_40 sp4_h_r_8 +(12 8) routing sp4_v_b_2 sp4_h_r_8 +(12 8) routing sp4_v_b_8 sp4_h_r_8 +(12 8) routing sp4_v_t_45 sp4_h_r_8 +(12 9) routing sp4_h_l_39 sp4_v_b_8 +(12 9) routing sp4_h_l_45 sp4_v_b_8 +(12 9) routing sp4_h_r_8 sp4_v_b_8 +(12 9) routing sp4_v_t_40 sp4_v_b_8 +(13 0) routing sp4_h_l_39 sp4_v_b_2 +(13 0) routing sp4_h_l_45 sp4_v_b_2 +(13 0) routing sp4_v_t_39 sp4_v_b_2 +(13 0) routing sp4_v_t_43 sp4_v_b_2 +(13 1) routing sp4_h_l_43 sp4_h_r_2 +(13 1) routing sp4_h_l_46 sp4_h_r_2 +(13 1) routing sp4_v_b_8 sp4_h_r_2 +(13 1) routing sp4_v_t_44 sp4_h_r_2 +(13 10) routing sp4_h_r_2 sp4_v_t_45 +(13 10) routing sp4_h_r_8 sp4_v_t_45 +(13 10) routing sp4_v_b_0 sp4_v_t_45 +(13 10) routing sp4_v_b_8 sp4_v_t_45 +(13 11) routing sp4_h_r_0 sp4_h_l_45 +(13 11) routing sp4_v_b_3 sp4_h_l_45 +(13 11) routing sp4_v_t_39 sp4_h_l_45 +(13 12) routing sp4_h_l_40 sp4_v_b_11 +(13 12) routing sp4_h_l_46 sp4_v_b_11 +(13 12) routing sp4_v_t_38 sp4_v_b_11 +(13 12) routing sp4_v_t_46 sp4_v_b_11 +(13 13) routing sp4_h_l_45 sp4_h_r_11 +(13 13) routing sp4_v_b_5 sp4_h_r_11 +(13 13) routing sp4_v_t_43 sp4_h_r_11 +(13 14) routing sp4_h_r_11 sp4_v_t_46 +(13 14) routing sp4_h_r_5 sp4_v_t_46 +(13 14) routing sp4_v_b_11 sp4_v_t_46 +(13 14) routing sp4_v_b_3 sp4_v_t_46 +(13 15) routing sp4_h_r_3 sp4_h_l_46 +(13 15) routing sp4_h_r_8 sp4_h_l_46 +(13 15) routing sp4_v_b_6 sp4_h_l_46 +(13 15) routing sp4_v_t_40 sp4_h_l_46 +(13 2) routing sp4_h_r_2 sp4_v_t_39 +(13 2) routing sp4_h_r_8 sp4_v_t_39 +(13 2) routing sp4_v_b_2 sp4_v_t_39 +(13 2) routing sp4_v_b_6 sp4_v_t_39 +(13 3) routing sp4_h_r_6 sp4_h_l_39 +(13 3) routing sp4_v_b_9 sp4_h_l_39 +(13 3) routing sp4_v_t_45 sp4_h_l_39 +(13 4) routing sp4_h_l_40 sp4_v_b_5 +(13 4) routing sp4_h_l_46 sp4_v_b_5 +(13 4) routing sp4_v_t_40 sp4_v_b_5 +(13 4) routing sp4_v_t_44 sp4_v_b_5 +(13 5) routing sp4_h_l_39 sp4_h_r_5 +(13 5) routing sp4_h_l_44 sp4_h_r_5 +(13 5) routing sp4_v_b_11 sp4_h_r_5 +(13 5) routing sp4_v_t_37 sp4_h_r_5 +(13 6) routing sp4_h_r_11 sp4_v_t_40 +(13 6) routing sp4_h_r_5 sp4_v_t_40 +(13 6) routing sp4_v_b_5 sp4_v_t_40 +(13 6) routing sp4_v_b_9 sp4_v_t_40 +(13 7) routing sp4_h_r_2 sp4_h_l_40 +(13 7) routing sp4_v_b_0 sp4_h_l_40 +(13 7) routing sp4_v_t_46 sp4_h_l_40 +(13 8) routing sp4_h_l_39 sp4_v_b_8 +(13 8) routing sp4_h_l_45 sp4_v_b_8 +(13 8) routing sp4_v_t_37 sp4_v_b_8 +(13 8) routing sp4_v_t_45 sp4_v_b_8 +(13 9) routing sp4_h_l_37 sp4_h_r_8 +(13 9) routing sp4_h_l_40 sp4_h_r_8 +(13 9) routing sp4_v_b_2 sp4_h_r_8 +(13 9) routing sp4_v_t_38 sp4_h_r_8 +(14 0) routing bnr_op_0 lc_trk_g0_0 +(14 0) routing lft_op_0 lc_trk_g0_0 +(14 0) routing sp12_h_r_0 lc_trk_g0_0 +(14 0) routing sp4_h_r_16 lc_trk_g0_0 +(14 0) routing sp4_h_r_8 lc_trk_g0_0 +(14 0) routing sp4_v_b_0 lc_trk_g0_0 +(14 0) routing sp4_v_b_8 lc_trk_g0_0 +(14 1) routing bnr_op_0 lc_trk_g0_0 +(14 1) routing sp12_h_l_15 lc_trk_g0_0 +(14 1) routing sp12_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_h_r_0 lc_trk_g0_0 +(14 1) routing sp4_h_r_16 lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 +(14 1) routing sp4_v_b_8 lc_trk_g0_0 +(14 10) routing bnl_op_4 lc_trk_g2_4 +(14 10) routing rgt_op_4 lc_trk_g2_4 +(14 10) routing sp12_v_b_4 lc_trk_g2_4 +(14 10) routing sp4_h_l_33 lc_trk_g2_4 +(14 10) routing sp4_h_r_36 lc_trk_g2_4 +(14 10) routing sp4_v_b_36 lc_trk_g2_4 +(14 10) routing sp4_v_t_17 lc_trk_g2_4 +(14 11) routing bnl_op_4 lc_trk_g2_4 +(14 11) routing sp12_v_b_20 lc_trk_g2_4 +(14 11) routing sp12_v_b_4 lc_trk_g2_4 +(14 11) routing sp4_h_l_33 lc_trk_g2_4 +(14 11) routing sp4_h_r_28 lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 +(14 11) routing sp4_v_b_36 lc_trk_g2_4 +(14 12) routing bnl_op_0 lc_trk_g3_0 +(14 12) routing rgt_op_0 lc_trk_g3_0 +(14 12) routing sp12_v_b_0 lc_trk_g3_0 +(14 12) routing sp4_h_l_21 lc_trk_g3_0 +(14 12) routing sp4_h_l_29 lc_trk_g3_0 +(14 12) routing sp4_v_t_13 lc_trk_g3_0 +(14 12) routing sp4_v_t_21 lc_trk_g3_0 +(14 13) routing bnl_op_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_16 lc_trk_g3_0 +(14 13) routing sp4_h_l_29 lc_trk_g3_0 +(14 13) routing sp4_h_r_24 lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 +(14 13) routing sp4_v_t_21 lc_trk_g3_0 +(14 13) routing tnl_op_0 lc_trk_g3_0 +(14 14) routing bnl_op_4 lc_trk_g3_4 +(14 14) routing rgt_op_4 lc_trk_g3_4 +(14 14) routing slf_op_4 lc_trk_g3_4 +(14 14) routing sp12_v_b_4 lc_trk_g3_4 +(14 14) routing sp4_h_l_33 lc_trk_g3_4 +(14 14) routing sp4_h_r_36 lc_trk_g3_4 +(14 14) routing sp4_v_b_36 lc_trk_g3_4 +(14 14) routing sp4_v_t_17 lc_trk_g3_4 +(14 15) routing bnl_op_4 lc_trk_g3_4 +(14 15) routing sp12_v_b_20 lc_trk_g3_4 +(14 15) routing sp12_v_b_4 lc_trk_g3_4 +(14 15) routing sp4_h_l_33 lc_trk_g3_4 +(14 15) routing sp4_h_r_28 lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 +(14 15) routing sp4_v_b_36 lc_trk_g3_4 +(14 2) routing bnr_op_4 lc_trk_g0_4 +(14 2) routing lft_op_4 lc_trk_g0_4 +(14 2) routing sp12_h_r_4 lc_trk_g0_4 +(14 2) routing sp4_h_l_1 lc_trk_g0_4 +(14 2) routing sp4_h_r_20 lc_trk_g0_4 +(14 2) routing sp4_v_b_12 lc_trk_g0_4 +(14 2) routing sp4_v_b_4 lc_trk_g0_4 +(14 3) routing bnr_op_4 lc_trk_g0_4 +(14 3) routing sp12_h_r_20 lc_trk_g0_4 +(14 3) routing sp12_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_h_r_20 lc_trk_g0_4 +(14 3) routing sp4_h_r_4 lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 +(14 3) routing sp4_v_b_12 lc_trk_g0_4 +(14 4) routing bnr_op_0 lc_trk_g1_0 +(14 4) routing lft_op_0 lc_trk_g1_0 +(14 4) routing sp12_h_r_0 lc_trk_g1_0 +(14 4) routing sp4_h_r_16 lc_trk_g1_0 +(14 4) routing sp4_h_r_8 lc_trk_g1_0 +(14 4) routing sp4_v_b_0 lc_trk_g1_0 +(14 4) routing sp4_v_b_8 lc_trk_g1_0 +(14 5) routing bnr_op_0 lc_trk_g1_0 +(14 5) routing sp12_h_l_15 lc_trk_g1_0 +(14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_r_16 lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 +(14 5) routing sp4_v_b_8 lc_trk_g1_0 +(14 5) routing top_op_0 lc_trk_g1_0 +(14 6) routing bnr_op_4 lc_trk_g1_4 +(14 6) routing lft_op_4 lc_trk_g1_4 +(14 6) routing sp12_h_r_4 lc_trk_g1_4 +(14 6) routing sp4_h_l_1 lc_trk_g1_4 +(14 6) routing sp4_h_r_20 lc_trk_g1_4 +(14 6) routing sp4_v_b_12 lc_trk_g1_4 +(14 6) routing sp4_v_b_4 lc_trk_g1_4 +(14 7) routing bnr_op_4 lc_trk_g1_4 +(14 7) routing sp12_h_r_20 lc_trk_g1_4 +(14 7) routing sp12_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_h_r_20 lc_trk_g1_4 +(14 7) routing sp4_h_r_4 lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 +(14 7) routing sp4_v_b_12 lc_trk_g1_4 +(14 8) routing bnl_op_0 lc_trk_g2_0 +(14 8) routing rgt_op_0 lc_trk_g2_0 +(14 8) routing slf_op_0 lc_trk_g2_0 +(14 8) routing sp12_v_b_0 lc_trk_g2_0 +(14 8) routing sp4_h_l_21 lc_trk_g2_0 +(14 8) routing sp4_h_l_29 lc_trk_g2_0 +(14 8) routing sp4_v_t_13 lc_trk_g2_0 +(14 8) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing bnl_op_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_16 lc_trk_g2_0 +(14 9) routing sp4_h_l_29 lc_trk_g2_0 +(14 9) routing sp4_h_r_24 lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 +(14 9) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing tnl_op_0 lc_trk_g2_0 +(15 0) routing lft_op_1 lc_trk_g0_1 +(15 0) routing sp12_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_17 lc_trk_g0_1 +(15 0) routing sp4_h_r_9 lc_trk_g0_1 +(15 0) routing sp4_v_b_17 lc_trk_g0_1 +(15 0) routing top_op_1 lc_trk_g0_1 +(15 1) routing lft_op_0 lc_trk_g0_0 +(15 1) routing sp12_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_0 lc_trk_g0_0 +(15 1) routing sp4_h_r_16 lc_trk_g0_0 +(15 1) routing sp4_h_r_8 lc_trk_g0_0 +(15 1) routing sp4_v_t_5 lc_trk_g0_0 +(15 10) routing rgt_op_5 lc_trk_g2_5 +(15 10) routing sp12_v_b_5 lc_trk_g2_5 +(15 10) routing sp4_h_l_16 lc_trk_g2_5 +(15 10) routing sp4_h_r_37 lc_trk_g2_5 +(15 10) routing sp4_h_r_45 lc_trk_g2_5 +(15 10) routing sp4_v_b_45 lc_trk_g2_5 +(15 11) routing rgt_op_4 lc_trk_g2_4 +(15 11) routing sp12_v_b_4 lc_trk_g2_4 +(15 11) routing sp4_h_l_33 lc_trk_g2_4 +(15 11) routing sp4_h_r_28 lc_trk_g2_4 +(15 11) routing sp4_h_r_36 lc_trk_g2_4 +(15 11) routing sp4_v_t_33 lc_trk_g2_4 +(15 11) routing tnr_op_4 lc_trk_g2_4 +(15 12) routing rgt_op_1 lc_trk_g3_1 +(15 12) routing sp12_v_b_1 lc_trk_g3_1 +(15 12) routing sp4_h_l_28 lc_trk_g3_1 +(15 12) routing sp4_h_r_25 lc_trk_g3_1 +(15 12) routing sp4_h_r_33 lc_trk_g3_1 +(15 12) routing sp4_v_b_41 lc_trk_g3_1 +(15 13) routing rgt_op_0 lc_trk_g3_0 +(15 13) routing sp12_v_b_0 lc_trk_g3_0 +(15 13) routing sp4_h_l_21 lc_trk_g3_0 +(15 13) routing sp4_h_l_29 lc_trk_g3_0 +(15 13) routing sp4_h_r_24 lc_trk_g3_0 +(15 13) routing sp4_v_b_40 lc_trk_g3_0 +(15 13) routing tnl_op_0 lc_trk_g3_0 +(15 13) routing tnr_op_0 lc_trk_g3_0 +(15 14) routing rgt_op_5 lc_trk_g3_5 +(15 14) routing sp12_v_b_5 lc_trk_g3_5 +(15 14) routing sp4_h_l_16 lc_trk_g3_5 +(15 14) routing sp4_h_r_37 lc_trk_g3_5 +(15 14) routing sp4_h_r_45 lc_trk_g3_5 +(15 14) routing sp4_v_b_45 lc_trk_g3_5 +(15 14) routing tnl_op_5 lc_trk_g3_5 +(15 14) routing tnr_op_5 lc_trk_g3_5 +(15 15) routing rgt_op_4 lc_trk_g3_4 +(15 15) routing sp12_v_b_4 lc_trk_g3_4 +(15 15) routing sp4_h_l_33 lc_trk_g3_4 +(15 15) routing sp4_h_r_28 lc_trk_g3_4 +(15 15) routing sp4_h_r_36 lc_trk_g3_4 +(15 15) routing sp4_v_t_33 lc_trk_g3_4 +(15 2) routing lft_op_5 lc_trk_g0_5 +(15 2) routing sp12_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_h_l_8 lc_trk_g0_5 +(15 2) routing sp4_h_r_13 lc_trk_g0_5 +(15 2) routing sp4_h_r_5 lc_trk_g0_5 +(15 2) routing sp4_v_t_8 lc_trk_g0_5 +(15 3) routing bot_op_4 lc_trk_g0_4 +(15 3) routing lft_op_4 lc_trk_g0_4 +(15 3) routing sp12_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_h_l_1 lc_trk_g0_4 +(15 3) routing sp4_h_r_20 lc_trk_g0_4 +(15 3) routing sp4_h_r_4 lc_trk_g0_4 +(15 3) routing sp4_v_t_9 lc_trk_g0_4 +(15 4) routing bot_op_1 lc_trk_g1_1 +(15 4) routing lft_op_1 lc_trk_g1_1 +(15 4) routing sp12_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_1 lc_trk_g1_1 +(15 4) routing sp4_h_r_17 lc_trk_g1_1 +(15 4) routing sp4_h_r_9 lc_trk_g1_1 +(15 4) routing sp4_v_b_17 lc_trk_g1_1 +(15 5) routing bot_op_0 lc_trk_g1_0 +(15 5) routing lft_op_0 lc_trk_g1_0 +(15 5) routing sp12_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_16 lc_trk_g1_0 +(15 5) routing sp4_h_r_8 lc_trk_g1_0 +(15 5) routing sp4_v_t_5 lc_trk_g1_0 +(15 5) routing top_op_0 lc_trk_g1_0 +(15 6) routing bot_op_5 lc_trk_g1_5 +(15 6) routing lft_op_5 lc_trk_g1_5 +(15 6) routing sp12_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_h_l_8 lc_trk_g1_5 +(15 6) routing sp4_h_r_13 lc_trk_g1_5 +(15 6) routing sp4_h_r_5 lc_trk_g1_5 +(15 6) routing sp4_v_t_8 lc_trk_g1_5 +(15 6) routing top_op_5 lc_trk_g1_5 +(15 7) routing bot_op_4 lc_trk_g1_4 +(15 7) routing lft_op_4 lc_trk_g1_4 +(15 7) routing sp12_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_h_l_1 lc_trk_g1_4 +(15 7) routing sp4_h_r_20 lc_trk_g1_4 +(15 7) routing sp4_h_r_4 lc_trk_g1_4 +(15 7) routing sp4_v_t_9 lc_trk_g1_4 +(15 8) routing rgt_op_1 lc_trk_g2_1 +(15 8) routing sp12_v_b_1 lc_trk_g2_1 +(15 8) routing sp4_h_l_28 lc_trk_g2_1 +(15 8) routing sp4_h_r_25 lc_trk_g2_1 +(15 8) routing sp4_h_r_33 lc_trk_g2_1 +(15 8) routing sp4_v_b_41 lc_trk_g2_1 +(15 8) routing tnl_op_1 lc_trk_g2_1 +(15 8) routing tnr_op_1 lc_trk_g2_1 +(15 9) routing rgt_op_0 lc_trk_g2_0 +(15 9) routing sp12_v_b_0 lc_trk_g2_0 +(15 9) routing sp4_h_l_21 lc_trk_g2_0 +(15 9) routing sp4_h_l_29 lc_trk_g2_0 +(15 9) routing sp4_h_r_24 lc_trk_g2_0 +(15 9) routing sp4_v_b_40 lc_trk_g2_0 +(15 9) routing tnl_op_0 lc_trk_g2_0 +(16 0) routing sp12_h_r_17 lc_trk_g0_1 +(16 0) routing sp12_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_h_r_1 lc_trk_g0_1 +(16 0) routing sp4_h_r_17 lc_trk_g0_1 +(16 0) routing sp4_h_r_9 lc_trk_g0_1 +(16 0) routing sp4_v_b_1 lc_trk_g0_1 +(16 0) routing sp4_v_b_17 lc_trk_g0_1 +(16 0) routing sp4_v_b_9 lc_trk_g0_1 +(16 1) routing sp12_h_l_15 lc_trk_g0_0 +(16 1) routing sp12_h_l_7 lc_trk_g0_0 +(16 1) routing sp4_h_r_0 lc_trk_g0_0 +(16 1) routing sp4_h_r_16 lc_trk_g0_0 +(16 1) routing sp4_h_r_8 lc_trk_g0_0 +(16 1) routing sp4_v_b_0 lc_trk_g0_0 +(16 1) routing sp4_v_b_8 lc_trk_g0_0 +(16 1) routing sp4_v_t_5 lc_trk_g0_0 +(16 10) routing sp12_v_b_21 lc_trk_g2_5 +(16 10) routing sp12_v_t_10 lc_trk_g2_5 +(16 10) routing sp4_h_l_16 lc_trk_g2_5 +(16 10) routing sp4_h_r_37 lc_trk_g2_5 +(16 10) routing sp4_h_r_45 lc_trk_g2_5 +(16 10) routing sp4_v_b_29 lc_trk_g2_5 +(16 10) routing sp4_v_b_45 lc_trk_g2_5 +(16 10) routing sp4_v_t_24 lc_trk_g2_5 +(16 11) routing sp12_v_b_12 lc_trk_g2_4 +(16 11) routing sp12_v_b_20 lc_trk_g2_4 +(16 11) routing sp4_h_l_33 lc_trk_g2_4 +(16 11) routing sp4_h_r_28 lc_trk_g2_4 +(16 11) routing sp4_h_r_36 lc_trk_g2_4 +(16 11) routing sp4_v_b_36 lc_trk_g2_4 +(16 11) routing sp4_v_t_17 lc_trk_g2_4 +(16 11) routing sp4_v_t_33 lc_trk_g2_4 +(16 12) routing sp12_v_b_9 lc_trk_g3_1 +(16 12) routing sp12_v_t_14 lc_trk_g3_1 +(16 12) routing sp4_h_l_28 lc_trk_g3_1 +(16 12) routing sp4_h_r_25 lc_trk_g3_1 +(16 12) routing sp4_h_r_33 lc_trk_g3_1 +(16 12) routing sp4_v_b_33 lc_trk_g3_1 +(16 12) routing sp4_v_b_41 lc_trk_g3_1 +(16 12) routing sp4_v_t_12 lc_trk_g3_1 +(16 13) routing sp12_v_b_16 lc_trk_g3_0 +(16 13) routing sp12_v_t_7 lc_trk_g3_0 +(16 13) routing sp4_h_l_21 lc_trk_g3_0 +(16 13) routing sp4_h_l_29 lc_trk_g3_0 +(16 13) routing sp4_h_r_24 lc_trk_g3_0 +(16 13) routing sp4_v_b_40 lc_trk_g3_0 +(16 13) routing sp4_v_t_13 lc_trk_g3_0 +(16 13) routing sp4_v_t_21 lc_trk_g3_0 +(16 14) routing sp12_v_b_21 lc_trk_g3_5 +(16 14) routing sp12_v_t_10 lc_trk_g3_5 +(16 14) routing sp4_h_l_16 lc_trk_g3_5 +(16 14) routing sp4_h_r_37 lc_trk_g3_5 +(16 14) routing sp4_h_r_45 lc_trk_g3_5 +(16 14) routing sp4_v_b_29 lc_trk_g3_5 +(16 14) routing sp4_v_b_45 lc_trk_g3_5 +(16 14) routing sp4_v_t_24 lc_trk_g3_5 +(16 15) routing sp12_v_b_12 lc_trk_g3_4 +(16 15) routing sp12_v_b_20 lc_trk_g3_4 +(16 15) routing sp4_h_l_33 lc_trk_g3_4 +(16 15) routing sp4_h_r_28 lc_trk_g3_4 +(16 15) routing sp4_h_r_36 lc_trk_g3_4 +(16 15) routing sp4_v_b_36 lc_trk_g3_4 +(16 15) routing sp4_v_t_17 lc_trk_g3_4 +(16 15) routing sp4_v_t_33 lc_trk_g3_4 +(16 2) routing sp12_h_l_10 lc_trk_g0_5 +(16 2) routing sp12_h_r_21 lc_trk_g0_5 +(16 2) routing sp4_h_l_8 lc_trk_g0_5 +(16 2) routing sp4_h_r_13 lc_trk_g0_5 +(16 2) routing sp4_h_r_5 lc_trk_g0_5 +(16 2) routing sp4_v_b_5 lc_trk_g0_5 +(16 2) routing sp4_v_t_0 lc_trk_g0_5 +(16 2) routing sp4_v_t_8 lc_trk_g0_5 +(16 3) routing sp12_h_l_11 lc_trk_g0_4 +(16 3) routing sp12_h_r_20 lc_trk_g0_4 +(16 3) routing sp4_h_l_1 lc_trk_g0_4 +(16 3) routing sp4_h_r_20 lc_trk_g0_4 +(16 3) routing sp4_h_r_4 lc_trk_g0_4 +(16 3) routing sp4_v_b_12 lc_trk_g0_4 +(16 3) routing sp4_v_b_4 lc_trk_g0_4 +(16 3) routing sp4_v_t_9 lc_trk_g0_4 +(16 4) routing sp12_h_r_17 lc_trk_g1_1 +(16 4) routing sp12_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_h_r_1 lc_trk_g1_1 +(16 4) routing sp4_h_r_17 lc_trk_g1_1 +(16 4) routing sp4_h_r_9 lc_trk_g1_1 +(16 4) routing sp4_v_b_1 lc_trk_g1_1 +(16 4) routing sp4_v_b_17 lc_trk_g1_1 +(16 4) routing sp4_v_b_9 lc_trk_g1_1 +(16 5) routing sp12_h_l_15 lc_trk_g1_0 +(16 5) routing sp12_h_l_7 lc_trk_g1_0 +(16 5) routing sp4_h_r_0 lc_trk_g1_0 +(16 5) routing sp4_h_r_16 lc_trk_g1_0 +(16 5) routing sp4_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_v_b_0 lc_trk_g1_0 +(16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 5) routing sp4_v_t_5 lc_trk_g1_0 +(16 6) routing sp12_h_l_10 lc_trk_g1_5 +(16 6) routing sp12_h_r_21 lc_trk_g1_5 +(16 6) routing sp4_h_l_8 lc_trk_g1_5 +(16 6) routing sp4_h_r_13 lc_trk_g1_5 +(16 6) routing sp4_h_r_5 lc_trk_g1_5 +(16 6) routing sp4_v_b_5 lc_trk_g1_5 +(16 6) routing sp4_v_t_0 lc_trk_g1_5 +(16 6) routing sp4_v_t_8 lc_trk_g1_5 +(16 7) routing sp12_h_l_11 lc_trk_g1_4 +(16 7) routing sp12_h_r_20 lc_trk_g1_4 +(16 7) routing sp4_h_l_1 lc_trk_g1_4 +(16 7) routing sp4_h_r_20 lc_trk_g1_4 +(16 7) routing sp4_h_r_4 lc_trk_g1_4 +(16 7) routing sp4_v_b_12 lc_trk_g1_4 +(16 7) routing sp4_v_b_4 lc_trk_g1_4 +(16 7) routing sp4_v_t_9 lc_trk_g1_4 +(16 8) routing sp12_v_b_9 lc_trk_g2_1 +(16 8) routing sp12_v_t_14 lc_trk_g2_1 +(16 8) routing sp4_h_l_28 lc_trk_g2_1 +(16 8) routing sp4_h_r_25 lc_trk_g2_1 +(16 8) routing sp4_h_r_33 lc_trk_g2_1 +(16 8) routing sp4_v_b_33 lc_trk_g2_1 +(16 8) routing sp4_v_b_41 lc_trk_g2_1 +(16 8) routing sp4_v_t_12 lc_trk_g2_1 +(16 9) routing sp12_v_b_16 lc_trk_g2_0 +(16 9) routing sp12_v_t_7 lc_trk_g2_0 +(16 9) routing sp4_h_l_21 lc_trk_g2_0 +(16 9) routing sp4_h_l_29 lc_trk_g2_0 +(16 9) routing sp4_h_r_24 lc_trk_g2_0 +(16 9) routing sp4_v_b_40 lc_trk_g2_0 +(16 9) routing sp4_v_t_13 lc_trk_g2_0 +(16 9) routing sp4_v_t_21 lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => top_op_1 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_7 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_t_5 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => slf_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => slf_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_9 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bot_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_7 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_t_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bot_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => top_op_5 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_9 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => slf_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 lc_trk_g0_1 +(18 0) routing lft_op_1 lc_trk_g0_1 +(18 0) routing sp12_h_r_1 lc_trk_g0_1 +(18 0) routing sp4_h_r_17 lc_trk_g0_1 +(18 0) routing sp4_h_r_9 lc_trk_g0_1 +(18 0) routing sp4_v_b_1 lc_trk_g0_1 +(18 0) routing sp4_v_b_9 lc_trk_g0_1 +(18 1) routing bnr_op_1 lc_trk_g0_1 +(18 1) routing sp12_h_r_1 lc_trk_g0_1 +(18 1) routing sp12_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_h_r_1 lc_trk_g0_1 +(18 1) routing sp4_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 +(18 1) routing sp4_v_b_9 lc_trk_g0_1 +(18 1) routing top_op_1 lc_trk_g0_1 +(18 10) routing bnl_op_5 lc_trk_g2_5 +(18 10) routing rgt_op_5 lc_trk_g2_5 +(18 10) routing sp12_v_b_5 lc_trk_g2_5 +(18 10) routing sp4_h_r_37 lc_trk_g2_5 +(18 10) routing sp4_h_r_45 lc_trk_g2_5 +(18 10) routing sp4_v_b_29 lc_trk_g2_5 +(18 10) routing sp4_v_t_24 lc_trk_g2_5 +(18 11) routing bnl_op_5 lc_trk_g2_5 +(18 11) routing sp12_v_b_21 lc_trk_g2_5 +(18 11) routing sp12_v_b_5 lc_trk_g2_5 +(18 11) routing sp4_h_l_16 lc_trk_g2_5 +(18 11) routing sp4_h_r_45 lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 +(18 11) routing sp4_v_t_24 lc_trk_g2_5 +(18 12) routing bnl_op_1 lc_trk_g3_1 +(18 12) routing rgt_op_1 lc_trk_g3_1 +(18 12) routing slf_op_1 lc_trk_g3_1 +(18 12) routing sp12_v_b_1 lc_trk_g3_1 +(18 12) routing sp4_h_l_28 lc_trk_g3_1 +(18 12) routing sp4_h_r_33 lc_trk_g3_1 +(18 12) routing sp4_v_b_33 lc_trk_g3_1 +(18 12) routing sp4_v_t_12 lc_trk_g3_1 +(18 13) routing bnl_op_1 lc_trk_g3_1 +(18 13) routing sp12_v_b_1 lc_trk_g3_1 +(18 13) routing sp12_v_t_14 lc_trk_g3_1 +(18 13) routing sp4_h_l_28 lc_trk_g3_1 +(18 13) routing sp4_h_r_25 lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 +(18 13) routing sp4_v_b_33 lc_trk_g3_1 +(18 14) routing bnl_op_5 lc_trk_g3_5 +(18 14) routing rgt_op_5 lc_trk_g3_5 +(18 14) routing sp12_v_b_5 lc_trk_g3_5 +(18 14) routing sp4_h_r_37 lc_trk_g3_5 +(18 14) routing sp4_h_r_45 lc_trk_g3_5 +(18 14) routing sp4_v_b_29 lc_trk_g3_5 +(18 14) routing sp4_v_t_24 lc_trk_g3_5 +(18 15) routing bnl_op_5 lc_trk_g3_5 +(18 15) routing sp12_v_b_21 lc_trk_g3_5 +(18 15) routing sp12_v_b_5 lc_trk_g3_5 +(18 15) routing sp4_h_l_16 lc_trk_g3_5 +(18 15) routing sp4_h_r_45 lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 +(18 15) routing sp4_v_t_24 lc_trk_g3_5 +(18 15) routing tnl_op_5 lc_trk_g3_5 +(18 2) routing bnr_op_5 lc_trk_g0_5 +(18 2) routing lft_op_5 lc_trk_g0_5 +(18 2) routing sp12_h_r_5 lc_trk_g0_5 +(18 2) routing sp4_h_l_8 lc_trk_g0_5 +(18 2) routing sp4_h_r_13 lc_trk_g0_5 +(18 2) routing sp4_v_b_5 lc_trk_g0_5 +(18 2) routing sp4_v_t_0 lc_trk_g0_5 +(18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_r_21 lc_trk_g0_5 +(18 3) routing sp12_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_h_l_8 lc_trk_g0_5 +(18 3) routing sp4_h_r_5 lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 +(18 3) routing sp4_v_t_0 lc_trk_g0_5 +(18 4) routing bnr_op_1 lc_trk_g1_1 +(18 4) routing lft_op_1 lc_trk_g1_1 +(18 4) routing sp12_h_r_1 lc_trk_g1_1 +(18 4) routing sp4_h_r_17 lc_trk_g1_1 +(18 4) routing sp4_h_r_9 lc_trk_g1_1 +(18 4) routing sp4_v_b_1 lc_trk_g1_1 +(18 4) routing sp4_v_b_9 lc_trk_g1_1 +(18 5) routing bnr_op_1 lc_trk_g1_1 +(18 5) routing sp12_h_r_1 lc_trk_g1_1 +(18 5) routing sp12_h_r_17 lc_trk_g1_1 +(18 5) routing sp4_h_r_1 lc_trk_g1_1 +(18 5) routing sp4_h_r_17 lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 +(18 5) routing sp4_v_b_9 lc_trk_g1_1 +(18 6) routing bnr_op_5 lc_trk_g1_5 +(18 6) routing lft_op_5 lc_trk_g1_5 +(18 6) routing sp12_h_r_5 lc_trk_g1_5 +(18 6) routing sp4_h_l_8 lc_trk_g1_5 +(18 6) routing sp4_h_r_13 lc_trk_g1_5 +(18 6) routing sp4_v_b_5 lc_trk_g1_5 +(18 6) routing sp4_v_t_0 lc_trk_g1_5 +(18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_r_21 lc_trk_g1_5 +(18 7) routing sp12_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_h_l_8 lc_trk_g1_5 +(18 7) routing sp4_h_r_5 lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 +(18 7) routing sp4_v_t_0 lc_trk_g1_5 +(18 7) routing top_op_5 lc_trk_g1_5 +(18 8) routing bnl_op_1 lc_trk_g2_1 +(18 8) routing rgt_op_1 lc_trk_g2_1 +(18 8) routing sp12_v_b_1 lc_trk_g2_1 +(18 8) routing sp4_h_l_28 lc_trk_g2_1 +(18 8) routing sp4_h_r_33 lc_trk_g2_1 +(18 8) routing sp4_v_b_33 lc_trk_g2_1 +(18 8) routing sp4_v_t_12 lc_trk_g2_1 +(18 9) routing bnl_op_1 lc_trk_g2_1 +(18 9) routing sp12_v_b_1 lc_trk_g2_1 +(18 9) routing sp12_v_t_14 lc_trk_g2_1 +(18 9) routing sp4_h_l_28 lc_trk_g2_1 +(18 9) routing sp4_h_r_25 lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 +(18 9) routing sp4_v_b_33 lc_trk_g2_1 +(18 9) routing tnl_op_1 lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_t_0 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_b_23 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_r_4 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_b_15 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_t_3 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_t_5 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_t_9 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_l_7 sp4_h_r_16 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_l_8 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_l_10 +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 clk +(2 3) routing lc_trk_g0_0 clk +(2 3) routing lc_trk_g1_1 clk +(2 3) routing lc_trk_g2_0 clk +(2 3) routing lc_trk_g3_1 clk +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_r_19 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_r_20 +(21 0) routing bnr_op_3 lc_trk_g0_3 +(21 0) routing lft_op_3 lc_trk_g0_3 +(21 0) routing slf_op_3 lc_trk_g0_3 +(21 0) routing sp12_h_r_3 lc_trk_g0_3 +(21 0) routing sp4_h_r_11 lc_trk_g0_3 +(21 0) routing sp4_h_r_19 lc_trk_g0_3 +(21 0) routing sp4_v_b_11 lc_trk_g0_3 +(21 0) routing sp4_v_b_3 lc_trk_g0_3 +(21 1) routing bnr_op_3 lc_trk_g0_3 +(21 1) routing sp12_h_l_16 lc_trk_g0_3 +(21 1) routing sp12_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_h_r_19 lc_trk_g0_3 +(21 1) routing sp4_h_r_3 lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 +(21 1) routing sp4_v_b_11 lc_trk_g0_3 +(21 10) routing bnl_op_7 lc_trk_g2_7 +(21 10) routing rgt_op_7 lc_trk_g2_7 +(21 10) routing slf_op_7 lc_trk_g2_7 +(21 10) routing sp12_v_t_4 lc_trk_g2_7 +(21 10) routing sp4_h_l_26 lc_trk_g2_7 +(21 10) routing sp4_h_l_34 lc_trk_g2_7 +(21 10) routing sp4_v_b_39 lc_trk_g2_7 +(21 10) routing sp4_v_t_18 lc_trk_g2_7 +(21 11) routing bnl_op_7 lc_trk_g2_7 +(21 11) routing sp12_v_b_23 lc_trk_g2_7 +(21 11) routing sp12_v_t_4 lc_trk_g2_7 +(21 11) routing sp4_h_l_34 lc_trk_g2_7 +(21 11) routing sp4_h_r_31 lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 +(21 11) routing sp4_v_b_39 lc_trk_g2_7 +(21 12) routing bnl_op_3 lc_trk_g3_3 +(21 12) routing rgt_op_3 lc_trk_g3_3 +(21 12) routing sp12_v_b_3 lc_trk_g3_3 +(21 12) routing sp4_h_r_35 lc_trk_g3_3 +(21 12) routing sp4_h_r_43 lc_trk_g3_3 +(21 12) routing sp4_v_b_27 lc_trk_g3_3 +(21 12) routing sp4_v_t_22 lc_trk_g3_3 +(21 13) routing bnl_op_3 lc_trk_g3_3 +(21 13) routing sp12_v_b_19 lc_trk_g3_3 +(21 13) routing sp12_v_b_3 lc_trk_g3_3 +(21 13) routing sp4_h_l_14 lc_trk_g3_3 +(21 13) routing sp4_h_r_43 lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 +(21 13) routing sp4_v_t_22 lc_trk_g3_3 +(21 13) routing tnl_op_3 lc_trk_g3_3 +(21 14) routing bnl_op_7 lc_trk_g3_7 +(21 14) routing rgt_op_7 lc_trk_g3_7 +(21 14) routing sp12_v_t_4 lc_trk_g3_7 +(21 14) routing sp4_h_l_26 lc_trk_g3_7 +(21 14) routing sp4_h_l_34 lc_trk_g3_7 +(21 14) routing sp4_v_b_39 lc_trk_g3_7 +(21 14) routing sp4_v_t_18 lc_trk_g3_7 +(21 15) routing bnl_op_7 lc_trk_g3_7 +(21 15) routing sp12_v_b_23 lc_trk_g3_7 +(21 15) routing sp12_v_t_4 lc_trk_g3_7 +(21 15) routing sp4_h_l_34 lc_trk_g3_7 +(21 15) routing sp4_h_r_31 lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 +(21 15) routing sp4_v_b_39 lc_trk_g3_7 +(21 15) routing tnl_op_7 lc_trk_g3_7 +(21 2) routing bnr_op_7 lc_trk_g0_7 +(21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_r_7 lc_trk_g0_7 +(21 2) routing sp4_h_l_10 lc_trk_g0_7 +(21 2) routing sp4_h_l_2 lc_trk_g0_7 +(21 2) routing sp4_v_b_15 lc_trk_g0_7 +(21 2) routing sp4_v_b_7 lc_trk_g0_7 +(21 3) routing bnr_op_7 lc_trk_g0_7 +(21 3) routing sp12_h_l_20 lc_trk_g0_7 +(21 3) routing sp12_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_h_l_10 lc_trk_g0_7 +(21 3) routing sp4_h_r_7 lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 +(21 3) routing sp4_v_b_15 lc_trk_g0_7 +(21 3) routing top_op_7 lc_trk_g0_7 +(21 4) routing bnr_op_3 lc_trk_g1_3 +(21 4) routing lft_op_3 lc_trk_g1_3 +(21 4) routing sp12_h_r_3 lc_trk_g1_3 +(21 4) routing sp4_h_r_11 lc_trk_g1_3 +(21 4) routing sp4_h_r_19 lc_trk_g1_3 +(21 4) routing sp4_v_b_11 lc_trk_g1_3 +(21 4) routing sp4_v_b_3 lc_trk_g1_3 +(21 5) routing bnr_op_3 lc_trk_g1_3 +(21 5) routing sp12_h_l_16 lc_trk_g1_3 +(21 5) routing sp12_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_h_r_19 lc_trk_g1_3 +(21 5) routing sp4_h_r_3 lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 +(21 5) routing sp4_v_b_11 lc_trk_g1_3 +(21 5) routing top_op_3 lc_trk_g1_3 +(21 6) routing bnr_op_7 lc_trk_g1_7 +(21 6) routing lft_op_7 lc_trk_g1_7 +(21 6) routing sp12_h_r_7 lc_trk_g1_7 +(21 6) routing sp4_h_l_10 lc_trk_g1_7 +(21 6) routing sp4_h_l_2 lc_trk_g1_7 +(21 6) routing sp4_v_b_15 lc_trk_g1_7 +(21 6) routing sp4_v_b_7 lc_trk_g1_7 +(21 7) routing bnr_op_7 lc_trk_g1_7 +(21 7) routing sp12_h_l_20 lc_trk_g1_7 +(21 7) routing sp12_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_h_l_10 lc_trk_g1_7 +(21 7) routing sp4_h_r_7 lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 +(21 7) routing sp4_v_b_15 lc_trk_g1_7 +(21 7) routing top_op_7 lc_trk_g1_7 +(21 8) routing bnl_op_3 lc_trk_g2_3 +(21 8) routing rgt_op_3 lc_trk_g2_3 +(21 8) routing sp12_v_b_3 lc_trk_g2_3 +(21 8) routing sp4_h_r_35 lc_trk_g2_3 +(21 8) routing sp4_h_r_43 lc_trk_g2_3 +(21 8) routing sp4_v_b_27 lc_trk_g2_3 +(21 8) routing sp4_v_t_22 lc_trk_g2_3 +(21 9) routing bnl_op_3 lc_trk_g2_3 +(21 9) routing sp12_v_b_19 lc_trk_g2_3 +(21 9) routing sp12_v_b_3 lc_trk_g2_3 +(21 9) routing sp4_h_l_14 lc_trk_g2_3 +(21 9) routing sp4_h_r_43 lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 +(21 9) routing sp4_v_t_22 lc_trk_g2_3 +(21 9) routing tnl_op_3 lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bot_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => slf_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => slf_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => slf_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bot_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => top_op_7 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => slf_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => top_op_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => top_op_7 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => slf_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_3 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 lc_trk_g0_3 +(23 0) routing sp12_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_11 lc_trk_g0_3 +(23 0) routing sp4_h_r_19 lc_trk_g0_3 +(23 0) routing sp4_h_r_3 lc_trk_g0_3 +(23 0) routing sp4_v_b_11 lc_trk_g0_3 +(23 0) routing sp4_v_b_3 lc_trk_g0_3 +(23 0) routing sp4_v_t_6 lc_trk_g0_3 +(23 1) routing sp12_h_l_17 lc_trk_g0_2 +(23 1) routing sp12_h_l_9 lc_trk_g0_2 +(23 1) routing sp4_h_l_7 lc_trk_g0_2 +(23 1) routing sp4_h_r_10 lc_trk_g0_2 +(23 1) routing sp4_h_r_2 lc_trk_g0_2 +(23 1) routing sp4_v_b_10 lc_trk_g0_2 +(23 1) routing sp4_v_b_18 lc_trk_g0_2 +(23 1) routing sp4_v_b_2 lc_trk_g0_2 +(23 10) routing sp12_v_b_23 lc_trk_g2_7 +(23 10) routing sp12_v_t_12 lc_trk_g2_7 +(23 10) routing sp4_h_l_26 lc_trk_g2_7 +(23 10) routing sp4_h_l_34 lc_trk_g2_7 +(23 10) routing sp4_h_r_31 lc_trk_g2_7 +(23 10) routing sp4_v_b_39 lc_trk_g2_7 +(23 10) routing sp4_v_t_18 lc_trk_g2_7 +(23 10) routing sp4_v_t_34 lc_trk_g2_7 +(23 11) routing sp12_v_b_14 lc_trk_g2_6 +(23 11) routing sp12_v_t_21 lc_trk_g2_6 +(23 11) routing sp4_h_l_19 lc_trk_g2_6 +(23 11) routing sp4_h_l_35 lc_trk_g2_6 +(23 11) routing sp4_h_r_38 lc_trk_g2_6 +(23 11) routing sp4_v_b_46 lc_trk_g2_6 +(23 11) routing sp4_v_t_19 lc_trk_g2_6 +(23 11) routing sp4_v_t_27 lc_trk_g2_6 +(23 12) routing sp12_v_b_11 lc_trk_g3_3 +(23 12) routing sp12_v_b_19 lc_trk_g3_3 +(23 12) routing sp4_h_l_14 lc_trk_g3_3 +(23 12) routing sp4_h_r_35 lc_trk_g3_3 +(23 12) routing sp4_h_r_43 lc_trk_g3_3 +(23 12) routing sp4_v_b_27 lc_trk_g3_3 +(23 12) routing sp4_v_t_22 lc_trk_g3_3 +(23 12) routing sp4_v_t_30 lc_trk_g3_3 +(23 13) routing sp12_v_b_10 lc_trk_g3_2 +(23 13) routing sp12_v_t_17 lc_trk_g3_2 +(23 13) routing sp4_h_r_26 lc_trk_g3_2 +(23 13) routing sp4_h_r_34 lc_trk_g3_2 +(23 13) routing sp4_h_r_42 lc_trk_g3_2 +(23 13) routing sp4_v_t_15 lc_trk_g3_2 +(23 13) routing sp4_v_t_23 lc_trk_g3_2 +(23 13) routing sp4_v_t_31 lc_trk_g3_2 +(23 14) routing sp12_v_b_23 lc_trk_g3_7 +(23 14) routing sp12_v_t_12 lc_trk_g3_7 +(23 14) routing sp4_h_l_26 lc_trk_g3_7 +(23 14) routing sp4_h_l_34 lc_trk_g3_7 +(23 14) routing sp4_h_r_31 lc_trk_g3_7 +(23 14) routing sp4_v_b_39 lc_trk_g3_7 +(23 14) routing sp4_v_t_18 lc_trk_g3_7 +(23 14) routing sp4_v_t_34 lc_trk_g3_7 +(23 15) routing sp12_v_b_14 lc_trk_g3_6 +(23 15) routing sp12_v_t_21 lc_trk_g3_6 +(23 15) routing sp4_h_l_19 lc_trk_g3_6 +(23 15) routing sp4_h_l_35 lc_trk_g3_6 +(23 15) routing sp4_h_r_38 lc_trk_g3_6 +(23 15) routing sp4_v_b_46 lc_trk_g3_6 +(23 15) routing sp4_v_t_19 lc_trk_g3_6 +(23 15) routing sp4_v_t_27 lc_trk_g3_6 +(23 2) routing sp12_h_l_12 lc_trk_g0_7 +(23 2) routing sp12_h_l_20 lc_trk_g0_7 +(23 2) routing sp4_h_l_10 lc_trk_g0_7 +(23 2) routing sp4_h_l_2 lc_trk_g0_7 +(23 2) routing sp4_h_r_7 lc_trk_g0_7 +(23 2) routing sp4_v_b_15 lc_trk_g0_7 +(23 2) routing sp4_v_b_23 lc_trk_g0_7 +(23 2) routing sp4_v_b_7 lc_trk_g0_7 +(23 3) routing sp12_h_r_14 lc_trk_g0_6 +(23 3) routing sp12_h_r_22 lc_trk_g0_6 +(23 3) routing sp4_h_l_11 lc_trk_g0_6 +(23 3) routing sp4_h_l_3 lc_trk_g0_6 +(23 3) routing sp4_h_r_6 lc_trk_g0_6 +(23 3) routing sp4_v_b_22 lc_trk_g0_6 +(23 3) routing sp4_v_b_6 lc_trk_g0_6 +(23 3) routing sp4_v_t_3 lc_trk_g0_6 +(23 4) routing sp12_h_l_16 lc_trk_g1_3 +(23 4) routing sp12_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_11 lc_trk_g1_3 +(23 4) routing sp4_h_r_19 lc_trk_g1_3 +(23 4) routing sp4_h_r_3 lc_trk_g1_3 +(23 4) routing sp4_v_b_11 lc_trk_g1_3 +(23 4) routing sp4_v_b_3 lc_trk_g1_3 +(23 4) routing sp4_v_t_6 lc_trk_g1_3 +(23 5) routing sp12_h_l_17 lc_trk_g1_2 +(23 5) routing sp12_h_l_9 lc_trk_g1_2 +(23 5) routing sp4_h_l_7 lc_trk_g1_2 +(23 5) routing sp4_h_r_10 lc_trk_g1_2 +(23 5) routing sp4_h_r_2 lc_trk_g1_2 +(23 5) routing sp4_v_b_10 lc_trk_g1_2 +(23 5) routing sp4_v_b_18 lc_trk_g1_2 +(23 5) routing sp4_v_b_2 lc_trk_g1_2 +(23 6) routing sp12_h_l_12 lc_trk_g1_7 +(23 6) routing sp12_h_l_20 lc_trk_g1_7 +(23 6) routing sp4_h_l_10 lc_trk_g1_7 +(23 6) routing sp4_h_l_2 lc_trk_g1_7 +(23 6) routing sp4_h_r_7 lc_trk_g1_7 +(23 6) routing sp4_v_b_15 lc_trk_g1_7 +(23 6) routing sp4_v_b_23 lc_trk_g1_7 +(23 6) routing sp4_v_b_7 lc_trk_g1_7 +(23 7) routing sp12_h_r_14 lc_trk_g1_6 +(23 7) routing sp12_h_r_22 lc_trk_g1_6 +(23 7) routing sp4_h_l_11 lc_trk_g1_6 +(23 7) routing sp4_h_l_3 lc_trk_g1_6 +(23 7) routing sp4_h_r_6 lc_trk_g1_6 +(23 7) routing sp4_v_b_22 lc_trk_g1_6 +(23 7) routing sp4_v_b_6 lc_trk_g1_6 +(23 7) routing sp4_v_t_3 lc_trk_g1_6 +(23 8) routing sp12_v_b_11 lc_trk_g2_3 +(23 8) routing sp12_v_b_19 lc_trk_g2_3 +(23 8) routing sp4_h_l_14 lc_trk_g2_3 +(23 8) routing sp4_h_r_35 lc_trk_g2_3 +(23 8) routing sp4_h_r_43 lc_trk_g2_3 +(23 8) routing sp4_v_b_27 lc_trk_g2_3 +(23 8) routing sp4_v_t_22 lc_trk_g2_3 +(23 8) routing sp4_v_t_30 lc_trk_g2_3 +(23 9) routing sp12_v_b_10 lc_trk_g2_2 +(23 9) routing sp12_v_t_17 lc_trk_g2_2 +(23 9) routing sp4_h_r_26 lc_trk_g2_2 +(23 9) routing sp4_h_r_34 lc_trk_g2_2 +(23 9) routing sp4_h_r_42 lc_trk_g2_2 +(23 9) routing sp4_v_t_15 lc_trk_g2_2 +(23 9) routing sp4_v_t_23 lc_trk_g2_2 +(23 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 0) routing bot_op_3 lc_trk_g0_3 +(24 0) routing lft_op_3 lc_trk_g0_3 +(24 0) routing sp12_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_h_r_11 lc_trk_g0_3 +(24 0) routing sp4_h_r_19 lc_trk_g0_3 +(24 0) routing sp4_h_r_3 lc_trk_g0_3 +(24 0) routing sp4_v_t_6 lc_trk_g0_3 +(24 1) routing lft_op_2 lc_trk_g0_2 +(24 1) routing sp12_h_l_1 lc_trk_g0_2 +(24 1) routing sp4_h_l_7 lc_trk_g0_2 +(24 1) routing sp4_h_r_10 lc_trk_g0_2 +(24 1) routing sp4_h_r_2 lc_trk_g0_2 +(24 1) routing sp4_v_b_18 lc_trk_g0_2 +(24 10) routing rgt_op_7 lc_trk_g2_7 +(24 10) routing sp12_v_t_4 lc_trk_g2_7 +(24 10) routing sp4_h_l_26 lc_trk_g2_7 +(24 10) routing sp4_h_l_34 lc_trk_g2_7 +(24 10) routing sp4_h_r_31 lc_trk_g2_7 +(24 10) routing sp4_v_t_34 lc_trk_g2_7 +(24 10) routing tnr_op_7 lc_trk_g2_7 +(24 11) routing rgt_op_6 lc_trk_g2_6 +(24 11) routing sp12_v_b_6 lc_trk_g2_6 +(24 11) routing sp4_h_l_19 lc_trk_g2_6 +(24 11) routing sp4_h_l_35 lc_trk_g2_6 +(24 11) routing sp4_h_r_38 lc_trk_g2_6 +(24 11) routing sp4_v_b_46 lc_trk_g2_6 +(24 11) routing tnl_op_6 lc_trk_g2_6 +(24 12) routing rgt_op_3 lc_trk_g3_3 +(24 12) routing sp12_v_b_3 lc_trk_g3_3 +(24 12) routing sp4_h_l_14 lc_trk_g3_3 +(24 12) routing sp4_h_r_35 lc_trk_g3_3 +(24 12) routing sp4_h_r_43 lc_trk_g3_3 +(24 12) routing sp4_v_t_30 lc_trk_g3_3 +(24 12) routing tnl_op_3 lc_trk_g3_3 +(24 12) routing tnr_op_3 lc_trk_g3_3 +(24 13) routing rgt_op_2 lc_trk_g3_2 +(24 13) routing sp12_v_t_1 lc_trk_g3_2 +(24 13) routing sp4_h_r_26 lc_trk_g3_2 +(24 13) routing sp4_h_r_34 lc_trk_g3_2 +(24 13) routing sp4_h_r_42 lc_trk_g3_2 +(24 13) routing sp4_v_t_31 lc_trk_g3_2 +(24 13) routing tnl_op_2 lc_trk_g3_2 +(24 13) routing tnr_op_2 lc_trk_g3_2 +(24 14) routing rgt_op_7 lc_trk_g3_7 +(24 14) routing sp12_v_t_4 lc_trk_g3_7 +(24 14) routing sp4_h_l_26 lc_trk_g3_7 +(24 14) routing sp4_h_l_34 lc_trk_g3_7 +(24 14) routing sp4_h_r_31 lc_trk_g3_7 +(24 14) routing sp4_v_t_34 lc_trk_g3_7 +(24 14) routing tnl_op_7 lc_trk_g3_7 +(24 14) routing tnr_op_7 lc_trk_g3_7 +(24 15) routing rgt_op_6 lc_trk_g3_6 +(24 15) routing sp12_v_b_6 lc_trk_g3_6 +(24 15) routing sp4_h_l_19 lc_trk_g3_6 +(24 15) routing sp4_h_l_35 lc_trk_g3_6 +(24 15) routing sp4_h_r_38 lc_trk_g3_6 +(24 15) routing sp4_v_b_46 lc_trk_g3_6 +(24 15) routing tnr_op_6 lc_trk_g3_6 +(24 2) routing bot_op_7 lc_trk_g0_7 +(24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_h_l_10 lc_trk_g0_7 +(24 2) routing sp4_h_l_2 lc_trk_g0_7 +(24 2) routing sp4_h_r_7 lc_trk_g0_7 +(24 2) routing sp4_v_b_23 lc_trk_g0_7 +(24 2) routing top_op_7 lc_trk_g0_7 +(24 3) routing lft_op_6 lc_trk_g0_6 +(24 3) routing sp12_h_l_5 lc_trk_g0_6 +(24 3) routing sp4_h_l_11 lc_trk_g0_6 +(24 3) routing sp4_h_l_3 lc_trk_g0_6 +(24 3) routing sp4_h_r_6 lc_trk_g0_6 +(24 3) routing sp4_v_b_22 lc_trk_g0_6 +(24 3) routing top_op_6 lc_trk_g0_6 +(24 4) routing lft_op_3 lc_trk_g1_3 +(24 4) routing sp12_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_h_r_11 lc_trk_g1_3 +(24 4) routing sp4_h_r_19 lc_trk_g1_3 +(24 4) routing sp4_h_r_3 lc_trk_g1_3 +(24 4) routing sp4_v_t_6 lc_trk_g1_3 +(24 4) routing top_op_3 lc_trk_g1_3 +(24 5) routing bot_op_2 lc_trk_g1_2 +(24 5) routing lft_op_2 lc_trk_g1_2 +(24 5) routing sp12_h_l_1 lc_trk_g1_2 +(24 5) routing sp4_h_l_7 lc_trk_g1_2 +(24 5) routing sp4_h_r_10 lc_trk_g1_2 +(24 5) routing sp4_h_r_2 lc_trk_g1_2 +(24 5) routing sp4_v_b_18 lc_trk_g1_2 +(24 5) routing top_op_2 lc_trk_g1_2 +(24 6) routing lft_op_7 lc_trk_g1_7 +(24 6) routing sp12_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_h_l_10 lc_trk_g1_7 +(24 6) routing sp4_h_l_2 lc_trk_g1_7 +(24 6) routing sp4_h_r_7 lc_trk_g1_7 +(24 6) routing sp4_v_b_23 lc_trk_g1_7 +(24 6) routing top_op_7 lc_trk_g1_7 +(24 7) routing bot_op_6 lc_trk_g1_6 +(24 7) routing lft_op_6 lc_trk_g1_6 +(24 7) routing sp12_h_l_5 lc_trk_g1_6 +(24 7) routing sp4_h_l_11 lc_trk_g1_6 +(24 7) routing sp4_h_l_3 lc_trk_g1_6 +(24 7) routing sp4_h_r_6 lc_trk_g1_6 +(24 7) routing sp4_v_b_22 lc_trk_g1_6 +(24 8) routing rgt_op_3 lc_trk_g2_3 +(24 8) routing sp12_v_b_3 lc_trk_g2_3 +(24 8) routing sp4_h_l_14 lc_trk_g2_3 +(24 8) routing sp4_h_r_35 lc_trk_g2_3 +(24 8) routing sp4_h_r_43 lc_trk_g2_3 +(24 8) routing sp4_v_t_30 lc_trk_g2_3 +(24 8) routing tnl_op_3 lc_trk_g2_3 +(24 9) routing rgt_op_2 lc_trk_g2_2 +(24 9) routing sp12_v_t_1 lc_trk_g2_2 +(24 9) routing sp4_h_r_26 lc_trk_g2_2 +(24 9) routing sp4_h_r_34 lc_trk_g2_2 +(24 9) routing sp4_h_r_42 lc_trk_g2_2 +(24 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 9) routing tnl_op_2 lc_trk_g2_2 +(24 9) routing tnr_op_2 lc_trk_g2_2 +(25 0) routing bnr_op_2 lc_trk_g0_2 +(25 0) routing lft_op_2 lc_trk_g0_2 +(25 0) routing sp12_h_l_1 lc_trk_g0_2 +(25 0) routing sp4_h_l_7 lc_trk_g0_2 +(25 0) routing sp4_h_r_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_10 lc_trk_g0_2 +(25 0) routing sp4_v_b_2 lc_trk_g0_2 +(25 1) routing bnr_op_2 lc_trk_g0_2 +(25 1) routing sp12_h_l_1 lc_trk_g0_2 +(25 1) routing sp12_h_l_17 lc_trk_g0_2 +(25 1) routing sp4_h_l_7 lc_trk_g0_2 +(25 1) routing sp4_h_r_2 lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 +(25 1) routing sp4_v_b_10 lc_trk_g0_2 +(25 10) routing bnl_op_6 lc_trk_g2_6 +(25 10) routing rgt_op_6 lc_trk_g2_6 +(25 10) routing sp12_v_b_6 lc_trk_g2_6 +(25 10) routing sp4_h_l_35 lc_trk_g2_6 +(25 10) routing sp4_h_r_38 lc_trk_g2_6 +(25 10) routing sp4_v_t_19 lc_trk_g2_6 +(25 10) routing sp4_v_t_27 lc_trk_g2_6 +(25 11) routing bnl_op_6 lc_trk_g2_6 +(25 11) routing sp12_v_b_6 lc_trk_g2_6 +(25 11) routing sp12_v_t_21 lc_trk_g2_6 +(25 11) routing sp4_h_l_19 lc_trk_g2_6 +(25 11) routing sp4_h_l_35 lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 +(25 11) routing sp4_v_t_27 lc_trk_g2_6 +(25 11) routing tnl_op_6 lc_trk_g2_6 +(25 12) routing bnl_op_2 lc_trk_g3_2 +(25 12) routing rgt_op_2 lc_trk_g3_2 +(25 12) routing slf_op_2 lc_trk_g3_2 +(25 12) routing sp12_v_t_1 lc_trk_g3_2 +(25 12) routing sp4_h_r_34 lc_trk_g3_2 +(25 12) routing sp4_h_r_42 lc_trk_g3_2 +(25 12) routing sp4_v_t_15 lc_trk_g3_2 +(25 12) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing bnl_op_2 lc_trk_g3_2 +(25 13) routing sp12_v_t_1 lc_trk_g3_2 +(25 13) routing sp12_v_t_17 lc_trk_g3_2 +(25 13) routing sp4_h_r_26 lc_trk_g3_2 +(25 13) routing sp4_h_r_42 lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 +(25 13) routing sp4_v_t_23 lc_trk_g3_2 +(25 13) routing tnl_op_2 lc_trk_g3_2 +(25 14) routing bnl_op_6 lc_trk_g3_6 +(25 14) routing rgt_op_6 lc_trk_g3_6 +(25 14) routing sp12_v_b_6 lc_trk_g3_6 +(25 14) routing sp4_h_l_35 lc_trk_g3_6 +(25 14) routing sp4_h_r_38 lc_trk_g3_6 +(25 14) routing sp4_v_t_19 lc_trk_g3_6 +(25 14) routing sp4_v_t_27 lc_trk_g3_6 +(25 15) routing bnl_op_6 lc_trk_g3_6 +(25 15) routing sp12_v_b_6 lc_trk_g3_6 +(25 15) routing sp12_v_t_21 lc_trk_g3_6 +(25 15) routing sp4_h_l_19 lc_trk_g3_6 +(25 15) routing sp4_h_l_35 lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 +(25 15) routing sp4_v_t_27 lc_trk_g3_6 +(25 2) routing bnr_op_6 lc_trk_g0_6 +(25 2) routing lft_op_6 lc_trk_g0_6 +(25 2) routing slf_op_6 lc_trk_g0_6 +(25 2) routing sp12_h_l_5 lc_trk_g0_6 +(25 2) routing sp4_h_l_11 lc_trk_g0_6 +(25 2) routing sp4_h_l_3 lc_trk_g0_6 +(25 2) routing sp4_v_b_6 lc_trk_g0_6 +(25 2) routing sp4_v_t_3 lc_trk_g0_6 +(25 3) routing bnr_op_6 lc_trk_g0_6 +(25 3) routing sp12_h_l_5 lc_trk_g0_6 +(25 3) routing sp12_h_r_22 lc_trk_g0_6 +(25 3) routing sp4_h_l_11 lc_trk_g0_6 +(25 3) routing sp4_h_r_6 lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 +(25 3) routing sp4_v_t_3 lc_trk_g0_6 +(25 3) routing top_op_6 lc_trk_g0_6 +(25 4) routing bnr_op_2 lc_trk_g1_2 +(25 4) routing lft_op_2 lc_trk_g1_2 +(25 4) routing sp12_h_l_1 lc_trk_g1_2 +(25 4) routing sp4_h_l_7 lc_trk_g1_2 +(25 4) routing sp4_h_r_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_10 lc_trk_g1_2 +(25 4) routing sp4_v_b_2 lc_trk_g1_2 +(25 5) routing bnr_op_2 lc_trk_g1_2 +(25 5) routing sp12_h_l_1 lc_trk_g1_2 +(25 5) routing sp12_h_l_17 lc_trk_g1_2 +(25 5) routing sp4_h_l_7 lc_trk_g1_2 +(25 5) routing sp4_h_r_2 lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 +(25 5) routing sp4_v_b_10 lc_trk_g1_2 +(25 5) routing top_op_2 lc_trk_g1_2 +(25 6) routing bnr_op_6 lc_trk_g1_6 +(25 6) routing lft_op_6 lc_trk_g1_6 +(25 6) routing slf_op_6 lc_trk_g1_6 +(25 6) routing sp12_h_l_5 lc_trk_g1_6 +(25 6) routing sp4_h_l_11 lc_trk_g1_6 +(25 6) routing sp4_h_l_3 lc_trk_g1_6 +(25 6) routing sp4_v_b_6 lc_trk_g1_6 +(25 6) routing sp4_v_t_3 lc_trk_g1_6 +(25 7) routing bnr_op_6 lc_trk_g1_6 +(25 7) routing sp12_h_l_5 lc_trk_g1_6 +(25 7) routing sp12_h_r_22 lc_trk_g1_6 +(25 7) routing sp4_h_l_11 lc_trk_g1_6 +(25 7) routing sp4_h_r_6 lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 +(25 7) routing sp4_v_t_3 lc_trk_g1_6 +(25 8) routing bnl_op_2 lc_trk_g2_2 +(25 8) routing rgt_op_2 lc_trk_g2_2 +(25 8) routing sp12_v_t_1 lc_trk_g2_2 +(25 8) routing sp4_h_r_34 lc_trk_g2_2 +(25 8) routing sp4_h_r_42 lc_trk_g2_2 +(25 8) routing sp4_v_t_15 lc_trk_g2_2 +(25 8) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing bnl_op_2 lc_trk_g2_2 +(25 9) routing sp12_v_t_1 lc_trk_g2_2 +(25 9) routing sp12_v_t_17 lc_trk_g2_2 +(25 9) routing sp4_h_r_26 lc_trk_g2_2 +(25 9) routing sp4_h_r_42 lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 +(25 9) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing tnl_op_2 lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g0_6 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g1_5 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g1_7 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g2_4 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g2_6 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g3_5 wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g3_7 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g0_2 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g0_6 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g1_3 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g1_7 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g2_2 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g2_6 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g3_3 wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g3_7 wire_con_box/lc_0/in_0 +(26 10) routing lc_trk_g0_5 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g0_7 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g1_4 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g1_6 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g2_5 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g2_7 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g3_4 wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g3_6 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g0_3 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g0_7 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g1_2 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g1_6 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g2_3 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g2_7 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g3_2 wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g3_6 wire_con_box/lc_5/in_0 +(26 12) routing lc_trk_g0_4 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g0_6 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g1_5 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g1_7 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g2_4 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g2_6 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g3_5 wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g3_7 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g0_2 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g0_6 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g1_3 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g1_7 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g2_2 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g2_6 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g3_3 wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g3_7 wire_con_box/lc_6/in_0 +(26 14) routing lc_trk_g0_5 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g0_7 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g1_4 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g1_6 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g2_5 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g2_7 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g3_4 wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g3_6 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g0_3 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g0_7 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g1_2 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g1_6 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g2_3 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g2_7 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g3_2 wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g3_6 wire_con_box/lc_7/in_0 +(26 2) routing lc_trk_g0_5 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g0_7 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g1_4 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g1_6 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g2_5 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g2_7 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g3_4 wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g3_6 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g0_3 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g0_7 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g1_2 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g1_6 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g2_3 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g2_7 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g3_2 wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g3_6 wire_con_box/lc_1/in_0 +(26 4) routing lc_trk_g0_4 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g0_6 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g1_5 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g1_7 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g2_4 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g2_6 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g3_5 wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g3_7 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g0_2 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g0_6 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g1_3 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g1_7 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g2_2 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g2_6 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g3_3 wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g3_7 wire_con_box/lc_2/in_0 +(26 6) routing lc_trk_g0_5 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g0_7 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g1_4 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g1_6 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g2_5 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g2_7 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g3_4 wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g3_6 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g0_3 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g0_7 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g1_2 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g1_6 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g2_3 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g2_7 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g3_2 wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g3_6 wire_con_box/lc_3/in_0 +(26 8) routing lc_trk_g0_4 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g0_6 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g1_5 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g1_7 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g2_4 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g2_6 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g3_5 wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g3_7 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g0_2 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g0_6 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g1_3 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g1_7 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g2_2 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g2_6 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g3_3 wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g3_7 wire_con_box/lc_4/in_0 +(27 0) routing lc_trk_g1_0 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g1_2 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g1_4 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g1_6 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_0 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_2 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_4 wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_6 wire_con_box/lc_0/in_1 +(27 1) routing lc_trk_g1_1 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g1_3 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g1_5 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g1_7 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_1 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_3 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_5 wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_7 wire_con_box/lc_0/in_0 +(27 10) routing lc_trk_g1_1 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g1_3 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g1_5 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g1_7 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_1 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_3 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_5 wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_7 wire_con_box/lc_5/in_1 +(27 11) routing lc_trk_g1_0 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g1_2 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g1_4 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g1_6 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_0 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_2 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_4 wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_6 wire_con_box/lc_5/in_0 +(27 12) routing lc_trk_g1_0 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g1_2 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g1_4 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g1_6 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_0 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_2 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_4 wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_6 wire_con_box/lc_6/in_1 +(27 13) routing lc_trk_g1_1 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g1_3 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g1_5 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g1_7 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_1 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_3 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_5 wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_7 wire_con_box/lc_6/in_0 +(27 14) routing lc_trk_g1_1 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g1_3 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g1_5 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g1_7 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_1 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_3 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_5 wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_7 wire_con_box/lc_7/in_1 +(27 15) routing lc_trk_g1_0 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g1_2 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g1_4 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g1_6 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_0 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_2 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_4 wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_6 wire_con_box/lc_7/in_0 +(27 2) routing lc_trk_g1_1 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g1_3 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g1_5 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g1_7 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_1 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_3 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_5 wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_7 wire_con_box/lc_1/in_1 +(27 3) routing lc_trk_g1_0 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g1_2 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g1_4 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g1_6 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_0 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_2 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_4 wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_6 wire_con_box/lc_1/in_0 +(27 4) routing lc_trk_g1_0 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g1_2 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g1_4 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g1_6 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_0 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_2 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_4 wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_6 wire_con_box/lc_2/in_1 +(27 5) routing lc_trk_g1_1 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g1_3 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g1_5 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g1_7 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_1 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_3 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_5 wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_7 wire_con_box/lc_2/in_0 +(27 6) routing lc_trk_g1_1 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g1_3 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g1_5 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g1_7 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_1 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_3 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_5 wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_7 wire_con_box/lc_3/in_1 +(27 7) routing lc_trk_g1_0 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g1_2 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g1_4 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g1_6 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_0 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_2 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_4 wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_6 wire_con_box/lc_3/in_0 +(27 8) routing lc_trk_g1_0 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g1_2 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g1_4 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g1_6 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_0 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_2 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_4 wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_6 wire_con_box/lc_4/in_1 +(27 9) routing lc_trk_g1_1 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g1_3 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g1_5 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g1_7 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_1 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_3 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_5 wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_7 wire_con_box/lc_4/in_0 +(28 0) routing lc_trk_g2_1 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g2_3 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g2_5 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g2_7 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_0 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_2 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_4 wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_6 wire_con_box/lc_0/in_1 +(28 1) routing lc_trk_g2_0 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g2_2 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g2_4 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g2_6 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_1 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_3 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_5 wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_7 wire_con_box/lc_0/in_0 +(28 10) routing lc_trk_g2_0 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g2_2 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g2_4 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g2_6 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_1 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_3 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_5 wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_7 wire_con_box/lc_5/in_1 +(28 11) routing lc_trk_g2_1 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g2_3 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g2_5 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g2_7 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_0 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_2 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_4 wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_6 wire_con_box/lc_5/in_0 +(28 12) routing lc_trk_g2_1 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g2_3 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g2_5 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g2_7 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_0 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_2 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_4 wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_6 wire_con_box/lc_6/in_1 +(28 13) routing lc_trk_g2_0 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g2_2 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g2_4 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g2_6 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_1 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_3 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_5 wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_7 wire_con_box/lc_6/in_0 +(28 14) routing lc_trk_g2_0 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g2_2 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g2_4 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g2_6 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_1 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_3 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_5 wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_7 wire_con_box/lc_7/in_1 +(28 15) routing lc_trk_g2_1 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g2_3 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g2_5 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g2_7 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_0 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_2 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_4 wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_6 wire_con_box/lc_7/in_0 +(28 2) routing lc_trk_g2_0 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g2_2 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g2_4 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g2_6 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_1 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_3 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_5 wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_7 wire_con_box/lc_1/in_1 +(28 3) routing lc_trk_g2_1 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g2_3 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g2_5 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g2_7 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_0 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_2 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_4 wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_6 wire_con_box/lc_1/in_0 +(28 4) routing lc_trk_g2_1 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g2_3 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g2_5 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g2_7 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_0 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_2 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_4 wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_6 wire_con_box/lc_2/in_1 +(28 5) routing lc_trk_g2_0 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g2_2 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g2_4 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g2_6 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_1 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_3 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_5 wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_7 wire_con_box/lc_2/in_0 +(28 6) routing lc_trk_g2_0 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g2_2 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g2_4 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g2_6 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_1 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_3 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_5 wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_7 wire_con_box/lc_3/in_1 +(28 7) routing lc_trk_g2_1 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g2_3 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g2_5 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g2_7 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_0 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_2 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_4 wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_6 wire_con_box/lc_3/in_0 +(28 8) routing lc_trk_g2_1 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g2_3 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g2_5 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g2_7 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_0 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_2 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_4 wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_6 wire_con_box/lc_4/in_1 +(28 9) routing lc_trk_g2_0 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g2_2 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g2_4 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g2_6 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_1 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_3 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_5 wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_7 wire_con_box/lc_4/in_0 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_1 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_3 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_5 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_7 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_0 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_2 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_4 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_6 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_1 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_3 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_5 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_7 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_0 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_2 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_4 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_6 wire_con_box/lc_0/in_1 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_0 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_2 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_4 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_6 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_1 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_3 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_5 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_7 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_0 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_2 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_4 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_6 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_1 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_3 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_5 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_7 wire_con_box/lc_0/in_0 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_0 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_2 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_4 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_6 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_1 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_3 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_5 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_7 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_0 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_2 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_4 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_6 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_1 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_3 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_5 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_7 wire_con_box/lc_5/in_1 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_1 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_3 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_5 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_7 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_0 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_2 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_4 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_6 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_1 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_3 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_5 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_7 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_0 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_2 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_4 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_6 wire_con_box/lc_5/in_0 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_1 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_3 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_5 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_7 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_0 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_2 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_4 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_6 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_1 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_3 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_5 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_7 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_0 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_2 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_4 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_6 wire_con_box/lc_6/in_1 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_0 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_2 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_4 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_6 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_1 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_3 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_5 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_7 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_0 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_2 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_4 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_6 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_1 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_3 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_5 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_7 wire_con_box/lc_6/in_0 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_0 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_2 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_4 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_6 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_1 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_3 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_5 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_7 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_0 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_2 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_4 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_6 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_1 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_3 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_5 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_7 wire_con_box/lc_7/in_1 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_1 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_3 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_5 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_7 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_0 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_2 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_4 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_6 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_1 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_3 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_5 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_7 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_0 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_2 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_4 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_6 wire_con_box/lc_7/in_0 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_0 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_2 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_4 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_6 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_1 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_3 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_5 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_7 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_0 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_2 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_4 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_6 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_1 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_3 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_5 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_7 wire_con_box/lc_1/in_1 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_1 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_3 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_5 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_7 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_0 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_2 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_4 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_6 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_1 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_3 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_5 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_7 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_0 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_2 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_4 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_6 wire_con_box/lc_1/in_0 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_1 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_3 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_5 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_7 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_0 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_2 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_4 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_6 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_1 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_3 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_5 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_7 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_0 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_2 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_4 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_6 wire_con_box/lc_2/in_1 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_0 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_2 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_4 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_6 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_1 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_3 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_5 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_7 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_0 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_2 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_4 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_6 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_1 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_3 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_5 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_7 wire_con_box/lc_2/in_0 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_0 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_2 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_4 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_6 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_1 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_3 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_5 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_7 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_0 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_2 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_4 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_6 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_1 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_3 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_5 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_7 wire_con_box/lc_3/in_1 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_1 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_3 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_5 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_7 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_0 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_2 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_4 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_6 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_1 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_3 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_5 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_7 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_0 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_2 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_4 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_6 wire_con_box/lc_3/in_0 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_1 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_3 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_5 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_7 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_0 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_2 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_4 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_6 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_1 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_3 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_5 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_7 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_0 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_2 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_4 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_6 wire_con_box/lc_4/in_1 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_0 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_2 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_4 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_6 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_1 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_3 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_5 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_7 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_0 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_2 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_4 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_6 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_1 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_3 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_5 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_7 wire_con_box/lc_4/in_0 +(3 0) routing sp12_h_r_0 sp12_v_b_0 +(3 0) routing sp12_v_t_23 sp12_v_b_0 +(3 1) routing sp12_h_l_23 sp12_v_b_0 +(3 1) routing sp12_h_r_0 sp12_v_b_0 +(3 10) routing sp12_v_t_22 sp12_h_l_22 +(3 11) routing sp12_v_b_1 sp12_h_l_22 +(3 12) routing sp12_v_b_1 sp12_h_r_1 +(3 12) routing sp12_v_t_22 sp12_h_r_1 +(3 13) routing sp12_h_l_22 sp12_h_r_1 +(3 13) routing sp12_v_b_1 sp12_h_r_1 +(3 14) routing sp12_h_r_1 sp12_v_t_22 +(3 14) routing sp12_v_b_1 sp12_v_t_22 +(3 15) routing sp12_h_l_22 sp12_v_t_22 +(3 15) routing sp12_h_r_1 sp12_v_t_22 +(3 2) routing sp12_h_r_0 sp12_h_l_23 +(3 2) routing sp12_v_t_23 sp12_h_l_23 +(3 3) routing sp12_h_r_0 sp12_h_l_23 +(3 3) routing sp12_v_b_0 sp12_h_l_23 +(3 4) routing sp12_v_b_0 sp12_h_r_0 +(3 4) routing sp12_v_t_23 sp12_h_r_0 +(3 5) routing sp12_h_l_23 sp12_h_r_0 +(3 5) routing sp12_v_b_0 sp12_h_r_0 +(3 6) routing sp12_h_r_0 sp12_v_t_23 +(3 6) routing sp12_v_b_0 sp12_v_t_23 +(3 7) routing sp12_h_l_23 sp12_v_t_23 +(3 7) routing sp12_h_r_0 sp12_v_t_23 +(3 8) routing sp12_h_r_1 sp12_v_b_1 +(3 8) routing sp12_v_t_22 sp12_v_b_1 +(3 9) routing sp12_h_l_22 sp12_v_b_1 +(3 9) routing sp12_h_r_1 sp12_v_b_1 +(30 0) routing lc_trk_g0_5 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g0_7 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g1_4 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g1_6 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g2_5 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g2_7 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g3_4 wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g3_6 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g0_3 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g0_7 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g1_2 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g1_6 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g2_3 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g2_7 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g3_2 wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g3_6 wire_con_box/lc_0/in_1 +(30 10) routing lc_trk_g0_4 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g0_6 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g1_5 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g1_7 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g2_4 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g2_6 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g3_5 wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g3_7 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g0_2 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g0_6 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g1_3 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g1_7 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g2_2 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g2_6 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g3_3 wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g3_7 wire_con_box/lc_5/in_1 +(30 12) routing lc_trk_g0_5 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g0_7 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g1_4 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g1_6 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g2_5 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g2_7 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g3_4 wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g3_6 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g0_3 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g0_7 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g1_2 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g1_6 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g2_3 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g2_7 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g3_2 wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g3_6 wire_con_box/lc_6/in_1 +(30 14) routing lc_trk_g0_4 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g0_6 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g1_5 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g1_7 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g2_4 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g2_6 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g3_5 wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g3_7 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g0_2 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g0_6 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g1_3 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g1_7 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g2_2 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g2_6 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g3_3 wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g3_7 wire_con_box/lc_7/in_1 +(30 2) routing lc_trk_g0_4 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g0_6 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g1_5 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g1_7 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g2_4 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g2_6 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g3_5 wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g3_7 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g0_2 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g0_6 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g1_3 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g1_7 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g2_2 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g2_6 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g3_3 wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g3_7 wire_con_box/lc_1/in_1 +(30 4) routing lc_trk_g0_5 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g0_7 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g1_4 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g1_6 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g2_5 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g2_7 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g3_4 wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g3_6 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g0_3 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g0_7 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g1_2 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g1_6 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g2_3 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g2_7 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g3_2 wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g3_6 wire_con_box/lc_2/in_1 +(30 6) routing lc_trk_g0_4 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g0_6 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g1_5 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g1_7 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g2_4 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g2_6 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g3_5 wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g3_7 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g0_2 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g0_6 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g1_3 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g1_7 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g2_2 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g2_6 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g3_3 wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g3_7 wire_con_box/lc_3/in_1 +(30 8) routing lc_trk_g0_5 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g0_7 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g1_4 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g1_6 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g2_5 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g2_7 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g3_4 wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g3_6 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g0_3 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g0_7 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g1_2 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g1_6 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g2_3 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g2_7 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g3_2 wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g3_6 wire_con_box/lc_4/in_1 +(31 0) routing lc_trk_g0_5 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g0_7 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g1_4 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g1_6 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g2_5 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g2_7 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g3_4 wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g3_6 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g0_3 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g0_7 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g1_2 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g1_6 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g2_3 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g2_7 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g3_2 wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g3_6 wire_con_box/lc_0/in_3 +(31 10) routing lc_trk_g0_4 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g0_6 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g1_5 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g1_7 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g2_4 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g2_6 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g3_5 wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g3_7 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g0_2 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g0_6 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g1_3 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g1_7 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g2_2 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g2_6 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g3_3 wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g3_7 wire_con_box/lc_5/in_3 +(31 12) routing lc_trk_g0_5 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g0_7 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g1_4 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g1_6 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g2_5 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g2_7 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g3_4 wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g3_6 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g0_3 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g0_7 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g1_2 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g1_6 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g2_3 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g2_7 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g3_2 wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g3_6 wire_con_box/lc_6/in_3 +(31 14) routing lc_trk_g0_4 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g0_6 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g1_5 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g1_7 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g2_4 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g2_6 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g3_5 wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g3_7 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g0_2 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g0_6 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g1_3 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g1_7 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g2_2 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g2_6 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g3_3 wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g3_7 wire_con_box/lc_7/in_3 +(31 2) routing lc_trk_g0_4 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g0_6 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g1_5 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g1_7 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g2_4 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g2_6 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g3_5 wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g3_7 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g0_2 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g0_6 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g1_3 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g1_7 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g2_2 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g2_6 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g3_3 wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g3_7 wire_con_box/lc_1/in_3 +(31 4) routing lc_trk_g0_5 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g0_7 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g1_4 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g1_6 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g2_5 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g2_7 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g3_4 wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g3_6 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g0_3 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g0_7 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g1_2 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g1_6 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g2_3 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g2_7 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g3_2 wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g3_6 wire_con_box/lc_2/in_3 +(31 6) routing lc_trk_g0_4 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g0_6 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g1_5 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g1_7 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g2_4 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g2_6 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g3_5 wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g3_7 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g0_2 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g0_6 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g1_3 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g1_7 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g2_2 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g2_6 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g3_3 wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g3_7 wire_con_box/lc_3/in_3 +(31 8) routing lc_trk_g0_5 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g0_7 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g1_4 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g1_6 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g2_5 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g2_7 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g3_4 wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g3_6 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g0_3 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g0_7 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g1_2 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g1_6 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g2_3 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g2_7 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g3_2 wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g3_6 wire_con_box/lc_4/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g0_3 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g0_5 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g0_7 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_0 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_2 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_4 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_6 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_1 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_3 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_5 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_7 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_0 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_2 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_4 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_6 wire_con_box/lc_0/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g0_2 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g0_4 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g0_6 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_1 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_3 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_5 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_7 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_0 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_2 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_4 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_6 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_1 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_3 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_5 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_7 wire_con_box/lc_5/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g0_3 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g0_5 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g0_7 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_0 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_2 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_4 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_6 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_1 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_3 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_5 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_7 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_0 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_2 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_4 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_6 wire_con_box/lc_6/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g0_2 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g0_4 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g0_6 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_1 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_3 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_5 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_7 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_0 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_2 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_4 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_6 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_1 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_3 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_5 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_7 wire_con_box/lc_7/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g0_2 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g0_4 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g0_6 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_1 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_3 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_5 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_7 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_0 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_2 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_4 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_6 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_1 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_3 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_5 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_7 wire_con_box/lc_1/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g0_3 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g0_5 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g0_7 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_0 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_2 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_4 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_6 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_1 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_3 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_5 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_7 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_0 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_2 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_4 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_6 wire_con_box/lc_2/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g0_2 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g0_4 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g0_6 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_1 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_3 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_5 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_7 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_0 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_2 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_4 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_6 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_1 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_3 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_5 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_7 wire_con_box/lc_3/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g0_3 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g0_5 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g0_7 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_0 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_2 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_4 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_6 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_1 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_3 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_5 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_7 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_0 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_2 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_4 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_6 wire_con_box/lc_4/in_3 +(33 0) routing lc_trk_g2_1 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g2_3 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g2_5 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g2_7 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_0 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_2 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_4 wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_6 wire_con_box/lc_0/in_3 +(33 10) routing lc_trk_g2_0 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g2_2 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g2_4 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g2_6 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_1 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_3 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_5 wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_7 wire_con_box/lc_5/in_3 +(33 12) routing lc_trk_g2_1 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g2_3 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g2_5 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g2_7 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_0 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_2 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_4 wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_6 wire_con_box/lc_6/in_3 +(33 14) routing lc_trk_g2_0 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g2_2 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g2_4 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g2_6 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_1 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_3 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_5 wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_7 wire_con_box/lc_7/in_3 +(33 2) routing lc_trk_g2_0 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g2_2 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g2_4 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g2_6 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_1 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_3 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_5 wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_7 wire_con_box/lc_1/in_3 +(33 4) routing lc_trk_g2_1 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g2_3 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g2_5 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g2_7 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_0 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_2 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_4 wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_6 wire_con_box/lc_2/in_3 +(33 6) routing lc_trk_g2_0 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g2_2 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g2_4 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g2_6 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_1 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_3 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_5 wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_7 wire_con_box/lc_3/in_3 +(33 8) routing lc_trk_g2_1 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g2_3 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g2_5 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g2_7 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_0 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_2 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_4 wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_6 wire_con_box/lc_4/in_3 +(34 0) routing lc_trk_g1_0 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g1_2 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g1_4 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g1_6 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_0 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_2 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_4 wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_6 wire_con_box/lc_0/in_3 +(34 10) routing lc_trk_g1_1 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g1_3 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g1_5 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g1_7 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_1 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_3 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_5 wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_7 wire_con_box/lc_5/in_3 +(34 12) routing lc_trk_g1_0 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g1_2 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g1_4 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g1_6 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_0 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_2 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_4 wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_6 wire_con_box/lc_6/in_3 +(34 14) routing lc_trk_g1_1 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g1_3 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g1_5 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g1_7 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_1 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_3 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_5 wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_7 wire_con_box/lc_7/in_3 +(34 2) routing lc_trk_g1_1 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g1_3 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g1_5 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g1_7 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_1 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_3 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_5 wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_7 wire_con_box/lc_1/in_3 +(34 4) routing lc_trk_g1_0 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g1_2 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g1_4 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g1_6 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_0 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_2 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_4 wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_6 wire_con_box/lc_2/in_3 +(34 6) routing lc_trk_g1_1 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g1_3 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g1_5 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g1_7 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_1 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_3 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_5 wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_7 wire_con_box/lc_3/in_3 +(34 8) routing lc_trk_g1_0 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g1_2 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g1_4 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g1_6 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_0 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_2 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_4 wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_6 wire_con_box/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 sp4_v_b_0 +(4 0) routing sp4_h_l_43 sp4_v_b_0 +(4 0) routing sp4_v_t_37 sp4_v_b_0 +(4 0) routing sp4_v_t_41 sp4_v_b_0 +(4 1) routing sp4_h_l_41 sp4_h_r_0 +(4 1) routing sp4_h_l_44 sp4_h_r_0 +(4 1) routing sp4_v_b_6 sp4_h_r_0 +(4 1) routing sp4_v_t_42 sp4_h_r_0 +(4 10) routing sp4_h_r_0 sp4_v_t_43 +(4 10) routing sp4_h_r_6 sp4_v_t_43 +(4 10) routing sp4_v_b_10 sp4_v_t_43 +(4 10) routing sp4_v_b_6 sp4_v_t_43 +(4 11) routing sp4_h_r_10 sp4_h_l_43 +(4 11) routing sp4_v_b_1 sp4_h_l_43 +(4 11) routing sp4_v_t_37 sp4_h_l_43 +(4 12) routing sp4_h_l_38 sp4_v_b_9 +(4 12) routing sp4_h_l_44 sp4_v_b_9 +(4 12) routing sp4_v_t_36 sp4_v_b_9 +(4 12) routing sp4_v_t_44 sp4_v_b_9 +(4 13) routing sp4_h_l_36 sp4_h_r_9 +(4 13) routing sp4_h_l_43 sp4_h_r_9 +(4 13) routing sp4_v_b_3 sp4_h_r_9 +(4 13) routing sp4_v_t_41 sp4_h_r_9 +(4 14) routing sp4_h_r_3 sp4_v_t_44 +(4 14) routing sp4_h_r_9 sp4_v_t_44 +(4 14) routing sp4_v_b_1 sp4_v_t_44 +(4 14) routing sp4_v_b_9 sp4_v_t_44 +(4 15) routing sp4_h_r_1 sp4_h_l_44 +(4 15) routing sp4_v_b_4 sp4_h_l_44 +(4 15) routing sp4_v_t_38 sp4_h_l_44 +(4 2) routing sp4_h_r_0 sp4_v_t_37 +(4 2) routing sp4_h_r_6 sp4_v_t_37 +(4 2) routing sp4_v_b_0 sp4_v_t_37 +(4 2) routing sp4_v_b_4 sp4_v_t_37 +(4 3) routing sp4_h_r_4 sp4_h_l_37 +(4 3) routing sp4_h_r_9 sp4_h_l_37 +(4 3) routing sp4_v_b_7 sp4_h_l_37 +(4 3) routing sp4_v_t_43 sp4_h_l_37 +(4 4) routing sp4_h_l_38 sp4_v_b_3 +(4 4) routing sp4_h_l_44 sp4_v_b_3 +(4 4) routing sp4_v_t_38 sp4_v_b_3 +(4 4) routing sp4_v_t_42 sp4_v_b_3 +(4 5) routing sp4_h_l_37 sp4_h_r_3 +(4 5) routing sp4_h_l_42 sp4_h_r_3 +(4 5) routing sp4_v_b_9 sp4_h_r_3 +(4 5) routing sp4_v_t_47 sp4_h_r_3 +(4 6) routing sp4_h_r_3 sp4_v_t_38 +(4 6) routing sp4_h_r_9 sp4_v_t_38 +(4 6) routing sp4_v_b_3 sp4_v_t_38 +(4 6) routing sp4_v_b_7 sp4_v_t_38 +(4 7) routing sp4_h_r_0 sp4_h_l_38 +(4 7) routing sp4_v_b_10 sp4_h_l_38 +(4 7) routing sp4_v_t_44 sp4_h_l_38 +(4 8) routing sp4_h_l_37 sp4_v_b_6 +(4 8) routing sp4_h_l_43 sp4_v_b_6 +(4 8) routing sp4_v_t_43 sp4_v_b_6 +(4 8) routing sp4_v_t_47 sp4_v_b_6 +(4 9) routing sp4_h_l_38 sp4_h_r_6 +(4 9) routing sp4_h_l_47 sp4_h_r_6 +(4 9) routing sp4_v_b_0 sp4_h_r_6 +(4 9) routing sp4_v_t_36 sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => slf_op_0 sp4_h_r_16 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => slf_op_0 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => slf_op_5 sp4_h_r_26 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => slf_op_5 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => slf_op_6 sp4_h_r_28 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => slf_op_6 sp4_h_l_1 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => slf_op_7 sp4_h_l_19 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => slf_op_7 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => slf_op_1 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => slf_op_1 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => slf_op_2 sp4_h_r_20 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => slf_op_2 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => slf_op_3 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => slf_op_3 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => slf_op_4 sp4_h_r_24 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => slf_op_4 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => slf_op_0 sp12_h_l_7 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => slf_op_0 sp4_h_l_21 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => slf_op_5 sp12_h_l_1 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => slf_op_5 sp4_h_r_42 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => slf_op_6 sp12_h_r_4 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => slf_op_6 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => slf_op_7 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => slf_op_7 sp4_h_l_35 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => slf_op_1 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => slf_op_1 sp4_h_r_34 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => slf_op_2 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => slf_op_2 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => slf_op_3 sp12_h_r_14 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => slf_op_3 sp4_h_r_38 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => slf_op_4 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => slf_op_4 sp4_h_l_29 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => slf_op_0 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => slf_op_0 sp4_v_t_5 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => slf_op_5 sp12_h_l_17 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => slf_op_5 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => slf_op_6 sp12_h_r_20 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => slf_op_6 sp4_v_b_12 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => slf_op_7 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => slf_op_7 sp4_v_t_3 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => slf_op_1 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => slf_op_1 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => slf_op_2 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => slf_op_2 sp4_v_t_9 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => slf_op_3 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => slf_op_3 sp4_v_b_22 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => slf_op_4 sp12_h_l_15 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => slf_op_4 sp4_v_b_8 +(5 0) routing sp4_h_l_44 sp4_h_r_0 +(5 0) routing sp4_v_b_0 sp4_h_r_0 +(5 0) routing sp4_v_b_6 sp4_h_r_0 +(5 0) routing sp4_v_t_37 sp4_h_r_0 +(5 1) routing sp4_h_l_37 sp4_v_b_0 +(5 1) routing sp4_h_l_43 sp4_v_b_0 +(5 1) routing sp4_h_r_0 sp4_v_b_0 +(5 1) routing sp4_v_t_44 sp4_v_b_0 +(5 10) routing sp4_v_b_6 sp4_h_l_43 +(5 10) routing sp4_v_t_37 sp4_h_l_43 +(5 10) routing sp4_v_t_43 sp4_h_l_43 +(5 11) routing sp4_h_l_43 sp4_v_t_43 +(5 11) routing sp4_h_r_0 sp4_v_t_43 +(5 11) routing sp4_h_r_6 sp4_v_t_43 +(5 11) routing sp4_v_b_3 sp4_v_t_43 +(5 12) routing sp4_h_l_43 sp4_h_r_9 +(5 12) routing sp4_v_b_3 sp4_h_r_9 +(5 12) routing sp4_v_b_9 sp4_h_r_9 +(5 12) routing sp4_v_t_44 sp4_h_r_9 +(5 13) routing sp4_h_l_38 sp4_v_b_9 +(5 13) routing sp4_h_l_44 sp4_v_b_9 +(5 13) routing sp4_h_r_9 sp4_v_b_9 +(5 13) routing sp4_v_t_43 sp4_v_b_9 +(5 14) routing sp4_v_b_9 sp4_h_l_44 +(5 14) routing sp4_v_t_38 sp4_h_l_44 +(5 14) routing sp4_v_t_44 sp4_h_l_44 +(5 15) routing sp4_h_l_44 sp4_v_t_44 +(5 15) routing sp4_h_r_3 sp4_v_t_44 +(5 15) routing sp4_h_r_9 sp4_v_t_44 +(5 15) routing sp4_v_b_6 sp4_v_t_44 +(5 2) routing sp4_h_r_9 sp4_h_l_37 +(5 2) routing sp4_v_b_0 sp4_h_l_37 +(5 2) routing sp4_v_t_37 sp4_h_l_37 +(5 2) routing sp4_v_t_43 sp4_h_l_37 +(5 3) routing sp4_h_l_37 sp4_v_t_37 +(5 3) routing sp4_h_r_0 sp4_v_t_37 +(5 3) routing sp4_h_r_6 sp4_v_t_37 +(5 3) routing sp4_v_b_9 sp4_v_t_37 +(5 4) routing sp4_h_l_37 sp4_h_r_3 +(5 4) routing sp4_v_b_3 sp4_h_r_3 +(5 4) routing sp4_v_b_9 sp4_h_r_3 +(5 4) routing sp4_v_t_38 sp4_h_r_3 +(5 5) routing sp4_h_l_38 sp4_v_b_3 +(5 5) routing sp4_h_l_44 sp4_v_b_3 +(5 5) routing sp4_h_r_3 sp4_v_b_3 +(5 5) routing sp4_v_t_37 sp4_v_b_3 +(5 6) routing sp4_h_r_0 sp4_h_l_38 +(5 6) routing sp4_v_b_3 sp4_h_l_38 +(5 6) routing sp4_v_t_38 sp4_h_l_38 +(5 6) routing sp4_v_t_44 sp4_h_l_38 +(5 7) routing sp4_h_l_38 sp4_v_t_38 +(5 7) routing sp4_h_r_3 sp4_v_t_38 +(5 7) routing sp4_h_r_9 sp4_v_t_38 +(5 7) routing sp4_v_b_0 sp4_v_t_38 +(5 8) routing sp4_h_l_38 sp4_h_r_6 +(5 8) routing sp4_v_b_0 sp4_h_r_6 +(5 8) routing sp4_v_b_6 sp4_h_r_6 +(5 8) routing sp4_v_t_43 sp4_h_r_6 +(5 9) routing sp4_h_l_37 sp4_v_b_6 +(5 9) routing sp4_h_l_43 sp4_v_b_6 +(5 9) routing sp4_h_r_6 sp4_v_b_6 +(5 9) routing sp4_v_t_38 sp4_v_b_6 +(50 0) Cascade buffer Enable bit: IPCON_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: IPCON_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: IPCON_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: IPCON_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: IPCON_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: IPCON_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: IPCON_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: IPCON_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => slf_op_0 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => slf_op_0 sp4_v_t_21 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => slf_op_5 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => slf_op_5 sp4_v_t_15 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => slf_op_6 sp4_v_t_33 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => slf_op_6 sp4_v_t_17 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => slf_op_7 sp4_v_b_46 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => slf_op_7 sp4_v_t_19 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => slf_op_1 sp12_v_t_1 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => slf_op_1 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => slf_op_2 sp12_v_b_4 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => slf_op_2 sp4_v_b_36 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => slf_op_3 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => slf_op_3 sp4_v_t_27 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => slf_op_4 sp4_v_b_40 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => slf_op_4 sp4_v_t_13 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => slf_op_0 sp12_v_b_16 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => slf_op_0 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => slf_op_5 sp12_v_b_10 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => slf_op_5 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => slf_op_6 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => slf_op_6 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => slf_op_7 sp12_v_b_14 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => slf_op_7 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => slf_op_1 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => slf_op_1 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => slf_op_2 sp12_v_b_20 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => slf_op_2 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => slf_op_3 sp12_v_t_21 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => slf_op_3 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => slf_op_4 sp12_v_t_7 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => slf_op_4 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => slf_op_0 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => slf_op_0 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => slf_op_5 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => slf_op_5 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => slf_op_6 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => slf_op_6 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => slf_op_7 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => slf_op_7 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => slf_op_1 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => slf_op_1 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => slf_op_2 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => slf_op_2 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => slf_op_3 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => slf_op_3 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => slf_op_4 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => slf_op_4 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 sp4_v_b_0 +(6 0) routing sp4_h_r_7 sp4_v_b_0 +(6 0) routing sp4_v_t_41 sp4_v_b_0 +(6 0) routing sp4_v_t_44 sp4_v_b_0 +(6 1) routing sp4_h_l_37 sp4_h_r_0 +(6 1) routing sp4_h_l_41 sp4_h_r_0 +(6 1) routing sp4_v_b_0 sp4_h_r_0 +(6 1) routing sp4_v_b_6 sp4_h_r_0 +(6 10) routing sp4_h_l_36 sp4_v_t_43 +(6 10) routing sp4_h_r_0 sp4_v_t_43 +(6 10) routing sp4_v_b_10 sp4_v_t_43 +(6 10) routing sp4_v_b_3 sp4_v_t_43 +(6 11) routing sp4_h_r_10 sp4_h_l_43 +(6 11) routing sp4_v_t_37 sp4_h_l_43 +(6 11) routing sp4_v_t_43 sp4_h_l_43 +(6 12) routing sp4_h_l_38 sp4_v_b_9 +(6 12) routing sp4_h_r_4 sp4_v_b_9 +(6 12) routing sp4_v_t_36 sp4_v_b_9 +(6 12) routing sp4_v_t_43 sp4_v_b_9 +(6 13) routing sp4_h_l_36 sp4_h_r_9 +(6 13) routing sp4_h_l_44 sp4_h_r_9 +(6 13) routing sp4_v_b_3 sp4_h_r_9 +(6 13) routing sp4_v_b_9 sp4_h_r_9 +(6 14) routing sp4_h_l_41 sp4_v_t_44 +(6 14) routing sp4_h_r_3 sp4_v_t_44 +(6 14) routing sp4_v_b_1 sp4_v_t_44 +(6 14) routing sp4_v_b_6 sp4_v_t_44 +(6 15) routing sp4_h_r_1 sp4_h_l_44 +(6 15) routing sp4_v_t_38 sp4_h_l_44 +(6 15) routing sp4_v_t_44 sp4_h_l_44 +(6 2) routing sp4_h_l_42 sp4_v_t_37 +(6 2) routing sp4_h_r_6 sp4_v_t_37 +(6 2) routing sp4_v_b_4 sp4_v_t_37 +(6 2) routing sp4_v_b_9 sp4_v_t_37 +(6 3) routing sp4_h_r_0 sp4_h_l_37 +(6 3) routing sp4_h_r_4 sp4_h_l_37 +(6 3) routing sp4_v_t_37 sp4_h_l_37 +(6 3) routing sp4_v_t_43 sp4_h_l_37 +(6 4) routing sp4_h_l_44 sp4_v_b_3 +(6 4) routing sp4_h_r_10 sp4_v_b_3 +(6 4) routing sp4_v_t_37 sp4_v_b_3 +(6 4) routing sp4_v_t_42 sp4_v_b_3 +(6 5) routing sp4_h_l_38 sp4_h_r_3 +(6 5) routing sp4_h_l_42 sp4_h_r_3 +(6 5) routing sp4_v_b_3 sp4_h_r_3 +(6 5) routing sp4_v_b_9 sp4_h_r_3 +(6 6) routing sp4_h_l_47 sp4_v_t_38 +(6 6) routing sp4_h_r_9 sp4_v_t_38 +(6 6) routing sp4_v_b_0 sp4_v_t_38 +(6 6) routing sp4_v_b_7 sp4_v_t_38 +(6 7) routing sp4_v_t_38 sp4_h_l_38 +(6 7) routing sp4_v_t_44 sp4_h_l_38 +(6 8) routing sp4_h_l_37 sp4_v_b_6 +(6 8) routing sp4_h_r_1 sp4_v_b_6 +(6 8) routing sp4_v_t_38 sp4_v_b_6 +(6 8) routing sp4_v_t_47 sp4_v_b_6 +(6 9) routing sp4_h_l_43 sp4_h_r_6 +(6 9) routing sp4_h_l_47 sp4_h_r_6 +(6 9) routing sp4_v_b_0 sp4_h_r_6 +(6 9) routing sp4_v_b_6 sp4_h_r_6 +(7 0) Hard IP config bit: IPCON_bram_cbit_1 +(7 1) Hard IP config bit: IPCON_bram_cbit_0 +(7 10) Column buffer control bit: IPCON_colbuf_cntl_3 +(7 11) Column buffer control bit: IPCON_colbuf_cntl_2 +(7 12) Column buffer control bit: IPCON_colbuf_cntl_5 +(7 13) Column buffer control bit: IPCON_colbuf_cntl_4 +(7 14) Column buffer control bit: IPCON_colbuf_cntl_7 +(7 15) Column buffer control bit: IPCON_colbuf_cntl_6 +(7 2) Hard IP config bit: IPCON_bram_cbit_3 +(7 2) MAC16 functional bit: IPCON_bram_cbit_3 +(7 3) Hard IP config bit: IPCON_bram_cbit_2 +(7 4) Hard IP config bit: IPCON_bram_cbit_5 +(7 4) MAC16 functional bit: IPCON_bram_cbit_5 +(7 5) Hard IP config bit: IPCON_bram_cbit_4 +(7 5) MAC16 functional bit: IPCON_bram_cbit_4 +(7 6) Hard IP config bit: IPCON_bram_cbit_7 +(7 7) Hard IP config bit: IPCON_bram_cbit_6 +(7 7) MAC16 functional bit: IPCON_bram_cbit_6 +(7 8) Column buffer control bit: IPCON_colbuf_cntl_1 +(7 9) Column buffer control bit: IPCON_colbuf_cntl_0 +(8 0) routing sp4_h_l_36 sp4_h_r_1 +(8 0) routing sp4_h_l_40 sp4_h_r_1 +(8 0) routing sp4_v_b_1 sp4_h_r_1 +(8 0) routing sp4_v_b_7 sp4_h_r_1 +(8 1) routing sp4_h_l_36 sp4_v_b_1 +(8 1) routing sp4_h_l_42 sp4_v_b_1 +(8 1) routing sp4_h_r_1 sp4_v_b_1 +(8 1) routing sp4_v_t_47 sp4_v_b_1 +(8 10) routing sp4_h_r_11 sp4_h_l_42 +(8 10) routing sp4_h_r_7 sp4_h_l_42 +(8 10) routing sp4_v_t_36 sp4_h_l_42 +(8 10) routing sp4_v_t_42 sp4_h_l_42 +(8 11) routing sp4_h_l_42 sp4_v_t_42 +(8 11) routing sp4_h_r_1 sp4_v_t_42 +(8 11) routing sp4_h_r_7 sp4_v_t_42 +(8 11) routing sp4_v_b_4 sp4_v_t_42 +(8 12) routing sp4_h_l_47 sp4_h_r_10 +(8 12) routing sp4_v_b_10 sp4_h_r_10 +(8 12) routing sp4_v_b_4 sp4_h_r_10 +(8 13) routing sp4_h_l_41 sp4_v_b_10 +(8 13) routing sp4_h_l_47 sp4_v_b_10 +(8 13) routing sp4_h_r_10 sp4_v_b_10 +(8 13) routing sp4_v_t_42 sp4_v_b_10 +(8 14) routing sp4_h_r_10 sp4_h_l_47 +(8 14) routing sp4_h_r_2 sp4_h_l_47 +(8 14) routing sp4_v_t_41 sp4_h_l_47 +(8 14) routing sp4_v_t_47 sp4_h_l_47 +(8 15) routing sp4_h_l_47 sp4_v_t_47 +(8 15) routing sp4_h_r_10 sp4_v_t_47 +(8 15) routing sp4_h_r_4 sp4_v_t_47 +(8 15) routing sp4_v_b_7 sp4_v_t_47 +(8 2) routing sp4_h_r_5 sp4_h_l_36 +(8 2) routing sp4_v_t_36 sp4_h_l_36 +(8 2) routing sp4_v_t_42 sp4_h_l_36 +(8 3) routing sp4_h_l_36 sp4_v_t_36 +(8 3) routing sp4_h_r_1 sp4_v_t_36 +(8 3) routing sp4_h_r_7 sp4_v_t_36 +(8 3) routing sp4_v_b_10 sp4_v_t_36 +(8 4) routing sp4_h_l_41 sp4_h_r_4 +(8 4) routing sp4_h_l_45 sp4_h_r_4 +(8 4) routing sp4_v_b_10 sp4_h_r_4 +(8 4) routing sp4_v_b_4 sp4_h_r_4 +(8 5) routing sp4_h_l_41 sp4_v_b_4 +(8 5) routing sp4_h_l_47 sp4_v_b_4 +(8 5) routing sp4_h_r_4 sp4_v_b_4 +(8 5) routing sp4_v_t_36 sp4_v_b_4 +(8 6) routing sp4_h_r_4 sp4_h_l_41 +(8 6) routing sp4_h_r_8 sp4_h_l_41 +(8 6) routing sp4_v_t_41 sp4_h_l_41 +(8 6) routing sp4_v_t_47 sp4_h_l_41 +(8 7) routing sp4_h_l_41 sp4_v_t_41 +(8 7) routing sp4_h_r_10 sp4_v_t_41 +(8 7) routing sp4_h_r_4 sp4_v_t_41 +(8 7) routing sp4_v_b_1 sp4_v_t_41 +(8 8) routing sp4_h_l_42 sp4_h_r_7 +(8 8) routing sp4_h_l_46 sp4_h_r_7 +(8 8) routing sp4_v_b_1 sp4_h_r_7 +(8 8) routing sp4_v_b_7 sp4_h_r_7 +(8 9) routing sp4_h_l_36 sp4_v_b_7 +(8 9) routing sp4_h_l_42 sp4_v_b_7 +(8 9) routing sp4_h_r_7 sp4_v_b_7 +(8 9) routing sp4_v_t_41 sp4_v_b_7 +(9 0) routing sp4_h_l_47 sp4_h_r_1 +(9 0) routing sp4_v_b_1 sp4_h_r_1 +(9 0) routing sp4_v_b_7 sp4_h_r_1 +(9 0) routing sp4_v_t_36 sp4_h_r_1 +(9 1) routing sp4_h_l_36 sp4_v_b_1 +(9 1) routing sp4_h_l_42 sp4_v_b_1 +(9 1) routing sp4_v_t_36 sp4_v_b_1 +(9 1) routing sp4_v_t_40 sp4_v_b_1 +(9 10) routing sp4_h_r_4 sp4_h_l_42 +(9 10) routing sp4_v_b_7 sp4_h_l_42 +(9 10) routing sp4_v_t_36 sp4_h_l_42 +(9 10) routing sp4_v_t_42 sp4_h_l_42 +(9 11) routing sp4_h_r_1 sp4_v_t_42 +(9 11) routing sp4_h_r_7 sp4_v_t_42 +(9 11) routing sp4_v_b_11 sp4_v_t_42 +(9 11) routing sp4_v_b_7 sp4_v_t_42 +(9 12) routing sp4_h_l_42 sp4_h_r_10 +(9 12) routing sp4_v_b_10 sp4_h_r_10 +(9 12) routing sp4_v_b_4 sp4_h_r_10 +(9 12) routing sp4_v_t_47 sp4_h_r_10 +(9 13) routing sp4_h_l_41 sp4_v_b_10 +(9 13) routing sp4_h_l_47 sp4_v_b_10 +(9 13) routing sp4_v_t_39 sp4_v_b_10 +(9 13) routing sp4_v_t_47 sp4_v_b_10 +(9 14) routing sp4_v_b_10 sp4_h_l_47 +(9 14) routing sp4_v_t_41 sp4_h_l_47 +(9 14) routing sp4_v_t_47 sp4_h_l_47 +(9 15) routing sp4_h_r_10 sp4_v_t_47 +(9 15) routing sp4_h_r_4 sp4_v_t_47 +(9 15) routing sp4_v_b_10 sp4_v_t_47 +(9 15) routing sp4_v_b_2 sp4_v_t_47 +(9 2) routing sp4_h_r_10 sp4_h_l_36 +(9 2) routing sp4_v_b_1 sp4_h_l_36 +(9 2) routing sp4_v_t_36 sp4_h_l_36 +(9 2) routing sp4_v_t_42 sp4_h_l_36 +(9 3) routing sp4_h_r_1 sp4_v_t_36 +(9 3) routing sp4_h_r_7 sp4_v_t_36 +(9 3) routing sp4_v_b_1 sp4_v_t_36 +(9 3) routing sp4_v_b_5 sp4_v_t_36 +(9 4) routing sp4_h_l_36 sp4_h_r_4 +(9 4) routing sp4_v_b_10 sp4_h_r_4 +(9 4) routing sp4_v_b_4 sp4_h_r_4 +(9 4) routing sp4_v_t_41 sp4_h_r_4 +(9 5) routing sp4_h_l_41 sp4_v_b_4 +(9 5) routing sp4_h_l_47 sp4_v_b_4 +(9 5) routing sp4_v_t_41 sp4_v_b_4 +(9 5) routing sp4_v_t_45 sp4_v_b_4 +(9 6) routing sp4_h_r_1 sp4_h_l_41 +(9 6) routing sp4_v_b_4 sp4_h_l_41 +(9 6) routing sp4_v_t_41 sp4_h_l_41 +(9 6) routing sp4_v_t_47 sp4_h_l_41 +(9 7) routing sp4_h_r_10 sp4_v_t_41 +(9 7) routing sp4_h_r_4 sp4_v_t_41 +(9 7) routing sp4_v_b_4 sp4_v_t_41 +(9 7) routing sp4_v_b_8 sp4_v_t_41 +(9 8) routing sp4_h_l_41 sp4_h_r_7 +(9 8) routing sp4_v_b_1 sp4_h_r_7 +(9 8) routing sp4_v_b_7 sp4_h_r_7 +(9 8) routing sp4_v_t_42 sp4_h_r_7 +(9 9) routing sp4_h_l_36 sp4_v_b_7 +(9 9) routing sp4_h_l_42 sp4_v_b_7 +(9 9) routing sp4_v_t_42 sp4_v_b_7 +(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt index d553dbf..65c15e3 100644 --- a/icefuzz/cached_ramb_5k.txt +++ b/icefuzz/cached_ramb_5k.txt @@ -1,27 +1,18 @@ (0 0) Negative Clock bit +(0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 -(0 10) routing glb_netwk_7 glb2local_2 -(0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 -(0 11) routing glb_netwk_5 glb2local_2 -(0 11) routing glb_netwk_7 glb2local_2 (0 12) routing glb_netwk_3 glb2local_3 -(0 12) routing glb_netwk_6 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 -(0 13) routing glb_netwk_5 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/RE -(0 14) routing glb_netwk_6 wire_bram/ram/RE (0 14) routing lc_trk_g2_4 wire_bram/ram/RE (0 14) routing lc_trk_g3_5 wire_bram/ram/RE -(0 15) routing glb_netwk_2 wire_bram/ram/RE -(0 15) routing glb_netwk_6 wire_bram/ram/RE (0 15) routing lc_trk_g1_5 wire_bram/ram/RE (0 15) routing lc_trk_g3_5 wire_bram/ram/RE (0 2) routing glb_netwk_2 wire_bram/ram/RCLK (0 2) routing glb_netwk_3 wire_bram/ram/RCLK -(0 2) routing glb_netwk_6 wire_bram/ram/RCLK (0 2) routing glb_netwk_7 wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/RCLK @@ -31,46 +22,22 @@ (0 3) routing glb_netwk_7 wire_bram/ram/RCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/RCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/RCLK -(0 4) routing glb_netwk_5 wire_bram/ram/RCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/RCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(0 6) routing glb_netwk_3 glb2local_0 -(0 6) routing glb_netwk_6 glb2local_0 -(0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 -(0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 -(0 7) routing glb_netwk_7 glb2local_0 -(0 8) routing glb_netwk_3 glb2local_1 -(0 8) routing glb_netwk_6 glb2local_1 -(0 8) routing glb_netwk_7 glb2local_1 -(0 9) routing glb_netwk_1 glb2local_1 -(0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 -(0 9) routing glb_netwk_7 glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 -(1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 -(1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_4 glb2local_3 -(1 13) routing glb_netwk_5 glb2local_3 -(1 13) routing glb_netwk_6 glb2local_3 -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE @@ -81,10 +48,8 @@ (1 15) routing lc_trk_g3_5 wire_bram/ram/RE (1 2) routing glb_netwk_4 wire_bram/ram/RCLK (1 2) routing glb_netwk_5 wire_bram/ram/RCLK -(1 2) routing glb_netwk_6 wire_bram/ram/RCLK (1 2) routing glb_netwk_7 wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE @@ -94,25 +59,10 @@ (1 5) routing lc_trk_g2_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 -(1 7) routing glb_netwk_6 glb2local_0 -(1 7) routing glb_netwk_7 glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 -(1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 -(1 9) routing glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 @@ -214,6 +164,7 @@ (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 +(11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 @@ -264,6 +215,7 @@ (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 +(12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 @@ -332,6 +284,7 @@ (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 +(13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 @@ -339,6 +292,7 @@ (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 (13 3) routing sp4_h_r_11 sp4_h_l_39 +(13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 @@ -442,13 +396,10 @@ (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_r_16 lc_trk_g1_0 -(14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 -(14 5) routing sp12_h_l_15 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 -(14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_h_r_16 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 @@ -463,7 +414,6 @@ (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_l_9 lc_trk_g1_4 -(14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_b_12 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 @@ -476,7 +426,6 @@ (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 -(14 9) routing sp4_h_r_24 lc_trk_g2_0 (14 9) routing sp4_h_r_40 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_b_32 lc_trk_g2_0 @@ -485,9 +434,7 @@ (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 -(15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_t_4 lc_trk_g0_1 -(15 1) routing bot_op_0 lc_trk_g0_0 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -499,9 +446,7 @@ (15 10) routing sp4_h_r_29 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 -(15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 -(15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_b_4 lc_trk_g2_4 (15 11) routing sp4_h_r_28 lc_trk_g2_4 @@ -516,8 +461,6 @@ (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_h_r_33 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 -(15 12) routing tnl_op_1 lc_trk_g3_1 -(15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_r_24 lc_trk_g3_0 @@ -525,7 +468,6 @@ (15 13) routing sp4_h_r_40 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 -(15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_r_29 lc_trk_g3_5 @@ -541,14 +483,11 @@ (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_b_44 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 -(15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 -(15 2) routing sp12_h_l_2 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_21 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 -(15 3) routing bot_op_4 lc_trk_g0_4 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_l_1 lc_trk_g0_4 @@ -564,44 +503,32 @@ (15 5) routing bot_op_0 lc_trk_g1_0 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 -(15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_16 lc_trk_g1_0 -(15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 -(15 6) routing sp12_h_l_2 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_21 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 -(15 7) routing bot_op_4 lc_trk_g1_4 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_l_1 lc_trk_g1_4 (15 7) routing sp4_h_l_9 lc_trk_g1_4 -(15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 -(15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_h_r_33 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 -(15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 -(15 9) routing sp4_h_r_24 lc_trk_g2_0 (15 9) routing sp4_h_r_32 lc_trk_g2_0 (15 9) routing sp4_h_r_40 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 -(15 9) routing tnr_op_0 lc_trk_g2_0 -(16 0) routing sp12_h_l_14 lc_trk_g0_1 -(16 0) routing sp12_h_r_9 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 -(16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 0) routing sp4_v_t_4 lc_trk_g0_1 @@ -619,7 +546,6 @@ (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 -(16 10) routing sp4_v_b_45 lc_trk_g2_5 (16 10) routing sp4_v_t_24 lc_trk_g2_5 (16 11) routing sp12_v_b_20 lc_trk_g2_4 (16 11) routing sp12_v_t_11 lc_trk_g2_4 @@ -661,8 +587,6 @@ (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_b_44 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 -(16 2) routing sp12_h_l_10 lc_trk_g0_5 -(16 2) routing sp12_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 @@ -678,23 +602,17 @@ (16 3) routing sp4_v_b_20 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 4) routing sp12_h_l_14 lc_trk_g1_1 -(16 4) routing sp12_h_r_9 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 4) routing sp4_v_t_4 lc_trk_g1_1 -(16 5) routing sp12_h_l_15 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 -(16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_16 lc_trk_g1_0 -(16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 -(16 6) routing sp12_h_l_10 lc_trk_g1_5 -(16 6) routing sp12_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 @@ -705,7 +623,6 @@ (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_l_1 lc_trk_g1_4 (16 7) routing sp4_h_l_9 lc_trk_g1_4 -(16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_12 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 @@ -719,7 +636,6 @@ (16 8) routing sp4_v_t_20 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_t_7 lc_trk_g2_0 -(16 9) routing sp4_h_r_24 lc_trk_g2_0 (16 9) routing sp4_h_r_32 lc_trk_g2_0 (16 9) routing sp4_h_r_40 lc_trk_g2_0 (16 9) routing sp4_v_b_32 lc_trk_g2_0 @@ -727,19 +643,15 @@ (16 9) routing sp4_v_t_13 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 @@ -763,10 +675,8 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 @@ -795,8 +705,6 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 @@ -811,7 +719,6 @@ (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 @@ -841,13 +748,9 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 @@ -856,7 +759,6 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 @@ -873,7 +775,6 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 @@ -885,12 +786,9 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 @@ -898,9 +796,6 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 @@ -910,14 +805,12 @@ (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 @@ -925,7 +818,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 @@ -937,13 +829,11 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 @@ -952,16 +842,13 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 -(18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 -(18 1) routing sp12_h_l_14 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 @@ -996,7 +883,6 @@ (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_t_20 lc_trk_g3_1 -(18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 @@ -1014,14 +900,11 @@ (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 -(18 2) routing sp12_h_l_2 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_h_r_21 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 -(18 3) routing sp12_h_l_2 lc_trk_g0_5 -(18 3) routing sp12_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 @@ -1042,27 +925,22 @@ (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 -(18 6) routing sp12_h_l_2 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_h_r_21 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 -(18 7) routing sp12_h_l_2 lc_trk_g1_5 -(18 7) routing sp12_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 -(18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_h_r_33 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 -(18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_t_14 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 @@ -1089,13 +967,11 @@ (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK @@ -1112,7 +988,6 @@ (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_r_3 lc_trk_g0_3 (21 0) routing sp4_h_l_6 lc_trk_g0_3 -(21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 @@ -1125,18 +1000,15 @@ (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_t_4 lc_trk_g2_7 -(21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_b_31 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 -(21 11) routing sp12_v_t_20 lc_trk_g2_7 (21 11) routing sp12_v_t_4 lc_trk_g2_7 (21 11) routing sp4_h_r_31 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_b_3 lc_trk_g3_3 @@ -1151,58 +1023,49 @@ (21 13) routing sp4_h_r_43 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_b_35 lc_trk_g3_3 -(21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_t_4 lc_trk_g3_7 (21 14) routing sp4_h_l_26 lc_trk_g3_7 -(21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_b_31 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_t_20 lc_trk_g3_7 (21 15) routing sp12_v_t_4 lc_trk_g3_7 (21 15) routing sp4_h_r_31 lc_trk_g3_7 -(21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 -(21 2) routing sp12_h_r_7 lc_trk_g0_7 (21 2) routing sp4_h_r_15 lc_trk_g0_7 (21 2) routing sp4_h_r_23 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_20 lc_trk_g0_7 -(21 3) routing sp12_h_r_7 lc_trk_g0_7 (21 3) routing sp4_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_t_2 lc_trk_g0_7 -(21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_r_3 lc_trk_g1_3 (21 4) routing sp4_h_l_6 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 -(21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp12_h_r_3 lc_trk_g1_3 (21 5) routing sp4_h_l_6 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 -(21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_r_7 lc_trk_g1_7 (21 6) routing sp4_h_r_15 lc_trk_g1_7 (21 6) routing sp4_h_r_23 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 -(21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_20 lc_trk_g1_7 (21 7) routing sp12_h_r_7 lc_trk_g1_7 (21 7) routing sp4_h_r_23 lc_trk_g1_7 @@ -1211,14 +1074,11 @@ (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 -(21 8) routing sp12_v_b_3 lc_trk_g2_3 -(21 8) routing sp4_h_l_22 lc_trk_g2_3 (21 8) routing sp4_h_r_43 lc_trk_g2_3 (21 8) routing sp4_v_b_27 lc_trk_g2_3 (21 8) routing sp4_v_b_35 lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_b_19 lc_trk_g2_3 -(21 9) routing sp12_v_b_3 lc_trk_g2_3 (21 9) routing sp4_h_l_14 lc_trk_g2_3 (21 9) routing sp4_h_r_43 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 @@ -1230,7 +1090,6 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 @@ -1238,11 +1097,9 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 @@ -1254,9 +1111,7 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 @@ -1264,8 +1119,6 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 @@ -1294,8 +1147,6 @@ (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 @@ -1310,7 +1161,6 @@ (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 @@ -1318,14 +1168,12 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 @@ -1336,7 +1184,6 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 @@ -1346,7 +1193,6 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1355,11 +1201,9 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 @@ -1368,7 +1212,6 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 @@ -1395,7 +1238,6 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 @@ -1409,26 +1251,19 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1451,17 +1286,14 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_l_6 lc_trk_g0_3 -(23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 0) routing sp4_v_t_6 lc_trk_g0_3 (23 1) routing sp12_h_l_17 lc_trk_g0_2 -(23 1) routing sp12_h_l_9 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 @@ -1469,8 +1301,6 @@ (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_t_12 lc_trk_g2_7 -(23 10) routing sp12_v_t_20 lc_trk_g2_7 -(23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_31 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_31 lc_trk_g2_7 @@ -1504,7 +1334,6 @@ (23 14) routing sp12_v_t_20 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_31 lc_trk_g3_7 -(23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_31 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 14) routing sp4_v_t_34 lc_trk_g3_7 @@ -1513,7 +1342,6 @@ (23 15) routing sp4_h_l_19 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 -(23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 15) routing sp4_v_t_19 lc_trk_g3_6 (23 15) routing sp4_v_t_27 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 @@ -1524,7 +1352,6 @@ (23 2) routing sp4_v_b_23 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 -(23 3) routing sp12_h_r_14 lc_trk_g0_6 (23 3) routing sp12_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_l_11 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 @@ -1557,17 +1384,12 @@ (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 (23 7) routing sp12_h_r_14 lc_trk_g1_6 -(23 7) routing sp12_h_r_22 lc_trk_g1_6 (23 7) routing sp4_h_l_11 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 -(23 7) routing sp4_v_b_14 lc_trk_g1_6 -(23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 7) routing sp4_v_t_11 lc_trk_g1_6 (23 8) routing sp12_v_b_19 lc_trk_g2_3 -(23 8) routing sp12_v_t_8 lc_trk_g2_3 (23 8) routing sp4_h_l_14 lc_trk_g2_3 -(23 8) routing sp4_h_l_22 lc_trk_g2_3 (23 8) routing sp4_h_r_43 lc_trk_g2_3 (23 8) routing sp4_v_b_27 lc_trk_g2_3 (23 8) routing sp4_v_b_35 lc_trk_g2_3 @@ -1583,10 +1405,8 @@ (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_r_3 lc_trk_g0_3 (24 0) routing sp4_h_l_6 lc_trk_g0_3 -(24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_t_6 lc_trk_g0_3 -(24 1) routing bot_op_2 lc_trk_g0_2 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_l_1 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 @@ -1595,12 +1415,9 @@ (24 1) routing sp4_v_t_7 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_t_4 lc_trk_g2_7 -(24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_31 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_t_34 lc_trk_g2_7 -(24 10) routing tnl_op_7 lc_trk_g2_7 -(24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_t_5 lc_trk_g2_6 (24 11) routing sp4_h_l_19 lc_trk_g2_6 @@ -1615,8 +1432,6 @@ (24 12) routing sp4_h_l_22 lc_trk_g3_3 (24 12) routing sp4_h_r_43 lc_trk_g3_3 (24 12) routing sp4_v_b_43 lc_trk_g3_3 -(24 12) routing tnl_op_3 lc_trk_g3_3 -(24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_t_1 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 @@ -1624,30 +1439,24 @@ (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 -(24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_t_4 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_31 lc_trk_g3_7 -(24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_t_34 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 -(24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_t_5 lc_trk_g3_6 (24 15) routing sp4_h_l_19 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 -(24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 -(24 2) routing sp12_h_r_7 lc_trk_g0_7 (24 2) routing sp4_h_r_15 lc_trk_g0_7 (24 2) routing sp4_h_r_23 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_b_23 lc_trk_g0_7 -(24 3) routing bot_op_6 lc_trk_g0_6 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_11 lc_trk_g0_6 @@ -1673,7 +1482,6 @@ (24 6) routing sp4_h_r_23 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_b_23 lc_trk_g1_7 -(24 7) routing bot_op_6 lc_trk_g1_6 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_11 lc_trk_g1_6 @@ -1681,9 +1489,7 @@ (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_t_11 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 -(24 8) routing sp12_v_b_3 lc_trk_g2_3 (24 8) routing sp4_h_l_14 lc_trk_g2_3 -(24 8) routing sp4_h_l_22 lc_trk_g2_3 (24 8) routing sp4_h_r_43 lc_trk_g2_3 (24 8) routing sp4_v_b_43 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 @@ -1695,7 +1501,6 @@ (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 -(24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_l_1 lc_trk_g0_2 @@ -1788,15 +1593,11 @@ (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_11 lc_trk_g1_6 (25 6) routing sp4_h_l_3 lc_trk_g1_6 -(25 6) routing sp4_v_b_14 lc_trk_g1_6 -(25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 -(25 7) routing sp12_h_r_22 lc_trk_g1_6 (25 7) routing sp4_h_l_11 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 -(25 7) routing sp4_v_b_14 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_t_1 lc_trk_g2_2 @@ -1941,11 +1742,8 @@ (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (27 1) routing lc_trk_g1_1 input0_0 @@ -1956,14 +1754,10 @@ (27 1) routing lc_trk_g3_3 input0_0 (27 1) routing lc_trk_g3_5 input0_0 (27 1) routing lc_trk_g3_7 input0_0 -(27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 @@ -1990,12 +1784,8 @@ (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 @@ -2006,12 +1796,9 @@ (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 @@ -2036,10 +1823,7 @@ (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 -(27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 @@ -2053,12 +1837,10 @@ (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (27 9) routing lc_trk_g1_1 input0_4 (27 9) routing lc_trk_g1_3 input0_4 @@ -2070,10 +1852,8 @@ (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (28 1) routing lc_trk_g2_0 input0_0 @@ -2084,14 +1864,10 @@ (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 -(28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 @@ -2119,11 +1895,8 @@ (28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 @@ -2133,13 +1906,10 @@ (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 @@ -2166,7 +1936,6 @@ (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -2180,13 +1949,11 @@ (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 -(28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (28 9) routing lc_trk_g2_0 input0_4 (28 9) routing lc_trk_g2_2 input0_4 @@ -2198,18 +1965,12 @@ (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 @@ -2232,18 +1993,11 @@ (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 @@ -2293,21 +2047,15 @@ (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 @@ -2325,21 +2073,16 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 @@ -2390,15 +2133,9 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -2421,20 +2158,15 @@ (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 @@ -2484,38 +2216,22 @@ (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 -(30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 @@ -2534,36 +2250,21 @@ (30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 @@ -2580,33 +2281,22 @@ (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 -(30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 -(30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 @@ -2615,89 +2305,58 @@ (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_10 -(31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_13 @@ -2705,40 +2364,25 @@ (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 @@ -2746,60 +2390,39 @@ (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 @@ -2821,16 +2444,10 @@ (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 @@ -2843,44 +2460,34 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 @@ -2888,57 +2495,37 @@ (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 -(33 11) routing lc_trk_g2_1 input2_5 (33 11) routing lc_trk_g2_3 input2_5 -(33 11) routing lc_trk_g2_5 input2_5 -(33 11) routing lc_trk_g2_7 input2_5 (33 11) routing lc_trk_g3_0 input2_5 -(33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 @@ -2952,14 +2539,10 @@ (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (33 15) routing lc_trk_g2_1 input2_7 (33 15) routing lc_trk_g2_3 input2_7 (33 15) routing lc_trk_g2_5 input2_7 -(33 15) routing lc_trk_g2_7 input2_7 (33 15) routing lc_trk_g3_0 input2_7 (33 15) routing lc_trk_g3_2 input2_7 (33 15) routing lc_trk_g3_4 input2_7 @@ -2969,13 +2552,10 @@ (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 @@ -2983,50 +2563,34 @@ (33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (34 11) routing lc_trk_g1_0 input2_5 -(34 11) routing lc_trk_g1_2 input2_5 (34 11) routing lc_trk_g1_4 input2_5 -(34 11) routing lc_trk_g1_6 input2_5 (34 11) routing lc_trk_g3_0 input2_5 -(34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 -(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 @@ -3037,12 +2601,6 @@ (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (34 15) routing lc_trk_g1_0 input2_7 (34 15) routing lc_trk_g1_2 input2_7 @@ -3052,15 +2610,11 @@ (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 -(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 @@ -3072,33 +2626,19 @@ (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(35 10) routing lc_trk_g0_5 input2_5 (35 10) routing lc_trk_g0_7 input2_5 (35 10) routing lc_trk_g1_4 input2_5 -(35 10) routing lc_trk_g1_6 input2_5 -(35 10) routing lc_trk_g2_5 input2_5 -(35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 (35 11) routing lc_trk_g0_3 input2_5 (35 11) routing lc_trk_g0_7 input2_5 -(35 11) routing lc_trk_g1_2 input2_5 -(35 11) routing lc_trk_g1_6 input2_5 (35 11) routing lc_trk_g2_3 input2_5 -(35 11) routing lc_trk_g2_7 input2_5 -(35 11) routing lc_trk_g3_2 input2_5 (35 11) routing lc_trk_g3_6 input2_5 (35 12) routing lc_trk_g0_4 input2_6 (35 12) routing lc_trk_g0_6 input2_6 @@ -3121,7 +2661,6 @@ (35 14) routing lc_trk_g1_4 input2_7 (35 14) routing lc_trk_g1_6 input2_7 (35 14) routing lc_trk_g2_5 input2_7 -(35 14) routing lc_trk_g2_7 input2_7 (35 14) routing lc_trk_g3_4 input2_7 (35 14) routing lc_trk_g3_6 input2_7 (35 15) routing lc_trk_g0_3 input2_7 @@ -3129,25 +2668,15 @@ (35 15) routing lc_trk_g1_2 input2_7 (35 15) routing lc_trk_g1_6 input2_7 (35 15) routing lc_trk_g2_3 input2_7 -(35 15) routing lc_trk_g2_7 input2_7 (35 15) routing lc_trk_g3_2 input2_7 (35 15) routing lc_trk_g3_6 input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 -(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 -(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 -(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 -(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 -(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 -(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 -(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 @@ -3166,20 +2695,15 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 -(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 -(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 -(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 -(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 -(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 @@ -3261,12 +2785,8 @@ (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 -(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 -(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 -(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 -(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 @@ -3285,7 +2805,6 @@ (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 -(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 @@ -3428,7 +2947,6 @@ (7 14) Column buffer control bit: MEMB_colbuf_cntl_7 (7 15) Column buffer control bit: MEMB_colbuf_cntl_6 (7 8) Column buffer control bit: MEMB_colbuf_cntl_1 -(7 9) Column buffer control bit: MEMB_colbuf_cntl_0 (8 0) routing sp4_h_l_36 sp4_h_r_1 (8 0) routing sp4_h_l_40 sp4_h_r_1 (8 0) routing sp4_v_b_1 sp4_h_r_1 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt index 48708fe..768ae76 100644 --- a/icefuzz/cached_ramt_5k.txt +++ b/icefuzz/cached_ramt_5k.txt @@ -1,18 +1,9 @@ (0 0) Negative Clock bit (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 -(0 10) routing glb_netwk_7 glb2local_2 -(0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 -(0 11) routing glb_netwk_7 glb2local_2 -(0 12) routing glb_netwk_3 glb2local_3 -(0 12) routing glb_netwk_6 glb2local_3 -(0 12) routing glb_netwk_7 glb2local_3 -(0 13) routing glb_netwk_1 glb2local_3 -(0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 -(0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/WE (0 14) routing glb_netwk_6 wire_bram/ram/WE (0 14) routing lc_trk_g2_4 wire_bram/ram/WE @@ -21,55 +12,31 @@ (0 15) routing lc_trk_g1_5 wire_bram/ram/WE (0 15) routing lc_trk_g3_5 wire_bram/ram/WE (0 2) routing glb_netwk_2 wire_bram/ram/WCLK -(0 2) routing glb_netwk_3 wire_bram/ram/WCLK -(0 2) routing glb_netwk_6 wire_bram/ram/WCLK (0 2) routing glb_netwk_7 wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 3) routing glb_netwk_1 wire_bram/ram/WCLK -(0 3) routing glb_netwk_3 wire_bram/ram/WCLK (0 3) routing glb_netwk_5 wire_bram/ram/WCLK (0 3) routing glb_netwk_7 wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/WCLK -(0 4) routing glb_netwk_5 wire_bram/ram/WCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/WCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(0 5) routing glb_netwk_3 wire_bram/ram/WCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 6) routing glb_netwk_3 glb2local_0 -(0 6) routing glb_netwk_6 glb2local_0 -(0 6) routing glb_netwk_7 glb2local_0 -(0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 -(0 7) routing glb_netwk_7 glb2local_0 -(0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 -(0 9) routing glb_netwk_1 glb2local_1 -(0 9) routing glb_netwk_3 glb2local_1 -(0 9) routing glb_netwk_5 glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 -(1 11) routing glb_netwk_7 glb2local_2 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 -(1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 -(1 13) routing glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_7 glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE @@ -82,11 +49,8 @@ (1 15) routing lc_trk_g3_5 wire_bram/ram/WE (1 2) routing glb_netwk_4 wire_bram/ram/WCLK (1 2) routing glb_netwk_5 wire_bram/ram/WCLK -(1 2) routing glb_netwk_6 wire_bram/ram/WCLK (1 2) routing glb_netwk_7 wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE @@ -95,23 +59,10 @@ (1 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 -(1 7) routing glb_netwk_6 glb2local_0 -(1 7) routing glb_netwk_7 glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_4 glb2local_1 -(1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 @@ -181,6 +132,7 @@ (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 +(11 1) routing sp4_h_l_39 sp4_h_r_2 (11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 @@ -221,6 +173,7 @@ (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 (11 5) routing sp4_h_l_40 sp4_h_r_5 +(11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 @@ -348,6 +301,7 @@ (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 +(13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 @@ -368,20 +322,16 @@ (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 -(14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 -(14 1) routing sp12_h_r_0 lc_trk_g0_0 -(14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 -(14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_t_3 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 @@ -397,31 +347,21 @@ (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 -(14 12) routing sp12_v_b_0 lc_trk_g3_0 -(14 12) routing sp4_h_l_21 lc_trk_g3_0 (14 12) routing sp4_h_l_29 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 12) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 -(14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 -(14 13) routing sp4_h_l_13 lc_trk_g3_0 (14 13) routing sp4_h_l_29 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 -(14 14) routing sp12_v_t_3 lc_trk_g3_4 -(14 14) routing sp4_h_r_36 lc_trk_g3_4 -(14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_28 lc_trk_g3_4 (14 14) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 -(14 15) routing sp12_v_t_19 lc_trk_g3_4 -(14 15) routing sp12_v_t_3 lc_trk_g3_4 (14 15) routing sp4_h_l_17 lc_trk_g3_4 -(14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 @@ -434,14 +374,11 @@ (14 2) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 -(14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_t_1 lc_trk_g0_4 -(14 3) routing top_op_4 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 -(14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_l_5 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 @@ -449,7 +386,6 @@ (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 -(14 5) routing sp12_h_r_16 lc_trk_g1_0 (14 5) routing sp4_h_l_5 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 @@ -463,34 +399,28 @@ (14 6) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 -(14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_t_1 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 -(14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_l_21 lc_trk_g2_0 (14 8) routing sp4_h_l_29 lc_trk_g2_0 (14 8) routing sp4_v_t_13 lc_trk_g2_0 (14 8) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 -(14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_l_13 lc_trk_g2_0 (14 9) routing sp4_h_l_29 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_t_21 lc_trk_g2_0 -(14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 -(15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_b_17 lc_trk_g0_1 (15 1) routing lft_op_0 lc_trk_g0_0 -(15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_l_5 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 @@ -498,12 +428,10 @@ (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_l_16 lc_trk_g2_5 -(15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 -(15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_t_3 lc_trk_g2_4 (15 11) routing sp4_h_l_17 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 @@ -511,18 +439,13 @@ (15 11) routing sp4_v_t_33 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 -(15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 -(15 12) routing sp4_h_l_20 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 -(15 13) routing sp12_v_b_0 lc_trk_g3_0 -(15 13) routing sp4_h_l_13 lc_trk_g3_0 -(15 13) routing sp4_h_l_21 lc_trk_g3_0 (15 13) routing sp4_h_l_29 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 @@ -531,15 +454,11 @@ (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_l_16 lc_trk_g3_5 (15 14) routing sp4_h_r_37 lc_trk_g3_5 -(15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 -(15 15) routing sp12_v_t_3 lc_trk_g3_4 (15 15) routing sp4_h_l_17 lc_trk_g3_4 -(15 15) routing sp4_h_r_36 lc_trk_g3_4 -(15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_t_33 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 @@ -555,14 +474,12 @@ (15 3) routing sp4_h_r_20 lc_trk_g0_4 (15 3) routing sp4_h_r_4 lc_trk_g0_4 (15 3) routing sp4_v_b_20 lc_trk_g0_4 -(15 3) routing top_op_4 lc_trk_g0_4 (15 4) routing lft_op_1 lc_trk_g1_1 (15 4) routing sp12_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_b_17 lc_trk_g1_1 -(15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_l_5 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 @@ -580,7 +497,6 @@ (15 7) routing sp4_h_r_20 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 -(15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_20 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 @@ -589,22 +505,17 @@ (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 -(15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_l_13 lc_trk_g2_0 (15 9) routing sp4_h_l_21 lc_trk_g2_0 (15 9) routing sp4_h_l_29 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 -(15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_6 lc_trk_g0_1 -(16 0) routing sp12_h_r_17 lc_trk_g0_1 -(16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_17 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 -(16 1) routing sp12_h_r_16 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_l_5 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -615,7 +526,6 @@ (16 10) routing sp12_v_b_21 lc_trk_g2_5 (16 10) routing sp12_v_t_10 lc_trk_g2_5 (16 10) routing sp4_h_l_16 lc_trk_g2_5 -(16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_37 lc_trk_g2_5 @@ -630,7 +540,6 @@ (16 11) routing sp4_v_t_33 lc_trk_g2_4 (16 12) routing sp12_v_b_17 lc_trk_g3_1 (16 12) routing sp12_v_b_9 lc_trk_g3_1 -(16 12) routing sp4_h_l_20 lc_trk_g3_1 (16 12) routing sp4_h_l_28 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_v_b_25 lc_trk_g3_1 @@ -638,8 +547,6 @@ (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 -(16 13) routing sp4_h_l_13 lc_trk_g3_0 -(16 13) routing sp4_h_l_21 lc_trk_g3_0 (16 13) routing sp4_h_l_29 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 @@ -648,19 +555,13 @@ (16 14) routing sp12_v_t_10 lc_trk_g3_5 (16 14) routing sp4_h_l_16 lc_trk_g3_5 (16 14) routing sp4_h_r_37 lc_trk_g3_5 -(16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_29 lc_trk_g3_5 (16 14) routing sp4_v_b_37 lc_trk_g3_5 (16 14) routing sp4_v_b_45 lc_trk_g3_5 -(16 15) routing sp12_v_b_12 lc_trk_g3_4 -(16 15) routing sp12_v_t_19 lc_trk_g3_4 (16 15) routing sp4_h_l_17 lc_trk_g3_4 -(16 15) routing sp4_h_r_36 lc_trk_g3_4 -(16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 15) routing sp4_v_t_33 lc_trk_g3_4 -(16 2) routing sp12_h_l_18 lc_trk_g0_5 (16 2) routing sp12_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_l_8 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 @@ -668,8 +569,6 @@ (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 -(16 3) routing sp12_h_r_12 lc_trk_g0_4 -(16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_12 lc_trk_g0_4 (16 3) routing sp4_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 @@ -684,7 +583,6 @@ (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_17 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 -(16 5) routing sp12_h_r_16 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_l_5 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 @@ -692,16 +590,12 @@ (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 -(16 6) routing sp12_h_l_18 lc_trk_g1_5 -(16 6) routing sp12_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_l_8 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 -(16 7) routing sp12_h_r_12 lc_trk_g1_4 -(16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_12 lc_trk_g1_4 (16 7) routing sp4_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 @@ -728,8 +622,6 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 @@ -739,8 +631,6 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 @@ -756,7 +646,6 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 @@ -766,7 +655,6 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 @@ -781,11 +669,9 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 @@ -797,11 +683,8 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 @@ -817,7 +700,6 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 @@ -827,12 +709,7 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 @@ -843,7 +720,6 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 @@ -857,8 +733,6 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 @@ -866,7 +740,6 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 @@ -881,9 +754,7 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 @@ -895,8 +766,6 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 @@ -909,8 +778,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 @@ -920,7 +787,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 @@ -936,7 +802,6 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 @@ -947,7 +812,6 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 @@ -958,15 +822,12 @@ (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 -(18 1) routing sp12_h_r_17 lc_trk_g0_1 -(18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 -(18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_b_37 lc_trk_g2_5 @@ -979,9 +840,7 @@ (18 11) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 -(18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 -(18 12) routing sp4_h_l_20 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 (18 12) routing sp4_v_b_25 lc_trk_g3_1 (18 12) routing sp4_v_b_33 lc_trk_g3_1 @@ -997,14 +856,12 @@ (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 (18 14) routing sp4_h_r_37 lc_trk_g3_5 -(18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_29 lc_trk_g3_5 (18 14) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_21 lc_trk_g3_5 (18 15) routing sp12_v_b_5 lc_trk_g3_5 (18 15) routing sp4_h_l_16 lc_trk_g3_5 -(18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 @@ -1016,7 +873,6 @@ (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 -(18 3) routing sp12_h_l_18 lc_trk_g0_5 (18 3) routing sp12_h_r_5 lc_trk_g0_5 (18 3) routing sp4_h_l_8 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 @@ -1044,14 +900,12 @@ (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 -(18 7) routing sp12_h_l_18 lc_trk_g1_5 (18 7) routing sp12_h_r_5 lc_trk_g1_5 (18 7) routing sp4_h_l_8 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 -(18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_20 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 @@ -1085,13 +939,10 @@ (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK @@ -1105,7 +956,6 @@ (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 lc_trk_g0_3 -(21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_l_0 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_h_r_19 lc_trk_g0_3 @@ -1113,15 +963,11 @@ (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_0 lc_trk_g0_3 -(21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp4_h_r_19 lc_trk_g0_3 -(21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 -(21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_b_7 lc_trk_g2_7 -(21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_t_18 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 @@ -1132,7 +978,6 @@ (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_t_0 lc_trk_g3_3 @@ -1151,28 +996,21 @@ (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_b_7 lc_trk_g3_7 -(21 14) routing sp4_h_l_26 lc_trk_g3_7 -(21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_t_18 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_b_23 lc_trk_g3_7 (21 15) routing sp12_v_b_7 lc_trk_g3_7 (21 15) routing sp4_h_l_18 lc_trk_g3_7 -(21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 -(21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 -(21 2) routing sp12_h_l_4 lc_trk_g0_7 (21 2) routing sp4_h_l_10 lc_trk_g0_7 (21 2) routing sp4_h_l_2 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 -(21 3) routing sp12_h_l_4 lc_trk_g0_7 -(21 3) routing sp12_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_l_10 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 @@ -1186,27 +1024,22 @@ (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_0 lc_trk_g1_3 -(21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp4_h_r_19 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 -(21 6) routing sp12_h_l_4 lc_trk_g1_7 (21 6) routing sp4_h_l_10 lc_trk_g1_7 (21 6) routing sp4_h_l_2 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 -(21 7) routing sp12_h_l_4 lc_trk_g1_7 -(21 7) routing sp12_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_l_10 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 -(21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_t_0 lc_trk_g2_3 (21 8) routing sp4_h_l_30 lc_trk_g2_3 (21 8) routing sp4_h_r_35 lc_trk_g2_3 @@ -1216,18 +1049,13 @@ (21 9) routing sp12_v_t_0 lc_trk_g2_3 (21 9) routing sp12_v_t_16 lc_trk_g2_3 (21 9) routing sp4_h_l_30 lc_trk_g2_3 -(21 9) routing sp4_h_r_27 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 @@ -1235,8 +1063,6 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 @@ -1246,21 +1072,17 @@ (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 @@ -1313,14 +1135,11 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 @@ -1328,7 +1147,6 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 @@ -1340,9 +1158,6 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1353,9 +1168,7 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 @@ -1363,12 +1176,9 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 @@ -1380,22 +1190,16 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 @@ -1406,25 +1210,19 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1446,18 +1244,12 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 -(23 0) routing sp12_h_l_16 lc_trk_g0_3 -(23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_19 lc_trk_g0_3 -(23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_19 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 -(23 1) routing sp12_h_r_10 lc_trk_g0_2 -(23 1) routing sp12_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_l_7 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 @@ -1467,7 +1259,6 @@ (23 10) routing sp12_v_b_23 lc_trk_g2_7 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp4_h_l_18 lc_trk_g2_7 -(23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_47 lc_trk_g2_7 (23 10) routing sp4_v_t_18 lc_trk_g2_7 @@ -1499,28 +1290,22 @@ (23 14) routing sp12_v_b_23 lc_trk_g3_7 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp4_h_l_18 lc_trk_g3_7 -(23 14) routing sp4_h_l_26 lc_trk_g3_7 -(23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_47 lc_trk_g3_7 (23 14) routing sp4_v_t_18 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_t_21 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 -(23 15) routing sp4_h_r_30 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_30 lc_trk_g3_6 (23 15) routing sp4_v_b_38 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 -(23 2) routing sp12_h_l_12 lc_trk_g0_7 -(23 2) routing sp12_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_l_10 lc_trk_g0_7 (23 2) routing sp4_h_l_2 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_10 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 -(23 3) routing sp12_h_l_13 lc_trk_g0_6 (23 3) routing sp12_h_l_21 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_22 lc_trk_g0_6 @@ -1528,8 +1313,6 @@ (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_22 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 -(23 4) routing sp12_h_l_16 lc_trk_g1_3 -(23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_19 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 @@ -1537,33 +1320,25 @@ (23 4) routing sp4_v_b_19 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 5) routing sp12_h_r_10 lc_trk_g1_2 -(23 5) routing sp12_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_l_7 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 -(23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 -(23 6) routing sp12_h_l_12 lc_trk_g1_7 -(23 6) routing sp12_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_l_10 lc_trk_g1_7 (23 6) routing sp4_h_l_2 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_10 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 -(23 7) routing sp12_h_l_13 lc_trk_g1_6 -(23 7) routing sp12_h_l_21 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_22 lc_trk_g1_6 -(23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_22 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 8) routing sp12_v_b_11 lc_trk_g2_3 (23 8) routing sp12_v_t_16 lc_trk_g2_3 (23 8) routing sp4_h_l_30 lc_trk_g2_3 -(23 8) routing sp4_h_r_27 lc_trk_g2_3 (23 8) routing sp4_h_r_35 lc_trk_g2_3 (23 8) routing sp4_v_t_14 lc_trk_g2_3 (23 8) routing sp4_v_t_22 lc_trk_g2_3 @@ -1576,11 +1351,9 @@ (23 9) routing sp4_v_b_26 lc_trk_g2_2 (23 9) routing sp4_v_t_23 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 -(24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_l_0 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_19 lc_trk_g0_3 -(24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_b_19 lc_trk_g0_3 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_r_2 lc_trk_g0_2 @@ -1588,14 +1361,10 @@ (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 -(24 1) routing top_op_2 lc_trk_g0_2 -(24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_b_7 lc_trk_g2_7 (24 10) routing sp4_h_l_18 lc_trk_g2_7 -(24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_b_47 lc_trk_g2_7 -(24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_b_6 lc_trk_g2_6 @@ -1624,32 +1393,25 @@ (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_b_7 lc_trk_g3_7 (24 14) routing sp4_h_l_18 lc_trk_g3_7 -(24 14) routing sp4_h_l_26 lc_trk_g3_7 -(24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_b_47 lc_trk_g3_7 -(24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_b_6 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 -(24 15) routing sp4_h_r_30 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 -(24 2) routing sp12_h_l_4 lc_trk_g0_7 (24 2) routing sp4_h_l_10 lc_trk_g0_7 (24 2) routing sp4_h_l_2 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_t_10 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 -(24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_3 lc_trk_g0_6 (24 3) routing sp4_h_r_22 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_b_22 lc_trk_g0_6 -(24 3) routing top_op_6 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_l_0 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 @@ -1660,11 +1422,8 @@ (24 5) routing sp12_h_r_2 lc_trk_g1_2 (24 5) routing sp4_h_l_7 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 -(24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 -(24 5) routing top_op_2 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 -(24 6) routing sp12_h_l_4 lc_trk_g1_7 (24 6) routing sp4_h_l_10 lc_trk_g1_7 (24 6) routing sp4_h_l_2 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 @@ -1673,13 +1432,9 @@ (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_22 lc_trk_g1_6 -(24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_b_22 lc_trk_g1_6 -(24 7) routing top_op_6 lc_trk_g1_6 -(24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_t_0 lc_trk_g2_3 (24 8) routing sp4_h_l_30 lc_trk_g2_3 -(24 8) routing sp4_h_r_27 lc_trk_g2_3 (24 8) routing sp4_h_r_35 lc_trk_g2_3 (24 8) routing sp4_v_t_30 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 @@ -1690,7 +1445,6 @@ (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 -(24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 @@ -1700,13 +1454,11 @@ (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 -(25 1) routing sp12_h_r_18 lc_trk_g0_2 (25 1) routing sp12_h_r_2 lc_trk_g0_2 (25 1) routing sp4_h_l_7 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 -(25 1) routing top_op_2 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_b_6 lc_trk_g2_6 @@ -1747,26 +1499,22 @@ (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_6 lc_trk_g3_6 (25 15) routing sp12_v_t_21 lc_trk_g3_6 -(25 15) routing sp4_h_r_30 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 -(25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_3 lc_trk_g0_6 (25 2) routing sp4_h_r_22 lc_trk_g0_6 (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_21 lc_trk_g0_6 -(25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp4_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_b_14 lc_trk_g0_6 -(25 3) routing top_op_6 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_r_2 lc_trk_g1_2 @@ -1775,13 +1523,10 @@ (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 -(25 5) routing sp12_h_r_18 lc_trk_g1_2 (25 5) routing sp12_h_r_2 lc_trk_g1_2 (25 5) routing sp4_h_l_7 lc_trk_g1_2 -(25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 -(25 5) routing top_op_2 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 @@ -1790,13 +1535,10 @@ (25 6) routing sp4_v_b_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 -(25 7) routing sp12_h_l_21 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp4_h_r_22 lc_trk_g1_6 -(25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 -(25 7) routing top_op_6 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_b_2 lc_trk_g2_2 @@ -1811,8 +1553,6 @@ (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_t_23 lc_trk_g2_2 -(25 9) routing tnl_op_2 lc_trk_g2_2 -(26 0) routing lc_trk_g0_4 input0_0 (26 0) routing lc_trk_g0_6 input0_0 (26 0) routing lc_trk_g1_5 input0_0 (26 0) routing lc_trk_g1_7 input0_0 @@ -1947,7 +1687,6 @@ (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 (27 1) routing lc_trk_g1_5 input0_0 @@ -1959,7 +1698,6 @@ (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 @@ -2005,9 +1743,7 @@ (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 @@ -2038,7 +1774,6 @@ (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2053,7 +1788,6 @@ (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_3 @@ -2075,7 +1809,6 @@ (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 (28 1) routing lc_trk_g2_4 input0_0 @@ -2132,7 +1865,6 @@ (28 15) routing lc_trk_g3_2 input0_7 (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 -(28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 @@ -2166,7 +1898,6 @@ (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2211,10 +1942,8 @@ (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 @@ -2229,13 +1958,11 @@ (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 @@ -2324,15 +2051,10 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 @@ -2390,15 +2112,12 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2423,9 +2142,7 @@ (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 @@ -2491,7 +2208,6 @@ (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_7 @@ -2499,19 +2215,15 @@ (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 @@ -2548,18 +2260,14 @@ (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 -(30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 @@ -2580,11 +2288,8 @@ (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 -(30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 @@ -2597,7 +2302,6 @@ (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_3 @@ -2605,63 +2309,40 @@ (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 -(31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 @@ -2669,17 +2350,12 @@ (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 @@ -2687,37 +2363,23 @@ (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_4 @@ -2732,75 +2394,45 @@ (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 @@ -2819,12 +2451,9 @@ (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 @@ -2849,14 +2478,8 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 @@ -2866,38 +2489,23 @@ (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 @@ -2908,17 +2516,12 @@ (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 -(33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 @@ -2928,18 +2531,13 @@ (33 11) routing lc_trk_g2_3 input2_5 (33 11) routing lc_trk_g2_5 input2_5 (33 11) routing lc_trk_g2_7 input2_5 -(33 11) routing lc_trk_g3_0 input2_5 (33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 -(33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 (33 13) routing lc_trk_g2_4 input2_6 @@ -2948,7 +2546,6 @@ (33 13) routing lc_trk_g3_3 input2_6 (33 13) routing lc_trk_g3_5 input2_6 (33 13) routing lc_trk_g3_7 input2_6 -(33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 @@ -2964,8 +2561,6 @@ (33 15) routing lc_trk_g3_2 input2_7 (33 15) routing lc_trk_g3_4 input2_7 (33 15) routing lc_trk_g3_6 input2_7 -(33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 @@ -2973,20 +2568,14 @@ (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_3 @@ -2997,37 +2586,24 @@ (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(34 11) routing lc_trk_g1_0 input2_5 -(34 11) routing lc_trk_g1_2 input2_5 -(34 11) routing lc_trk_g1_4 input2_5 -(34 11) routing lc_trk_g1_6 input2_5 -(34 11) routing lc_trk_g3_0 input2_5 (34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 -(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 (34 13) routing lc_trk_g1_5 input2_6 @@ -3037,7 +2613,6 @@ (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 @@ -3052,32 +2627,22 @@ (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 -(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 @@ -3086,16 +2651,11 @@ (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (35 10) routing lc_trk_g0_5 input2_5 (35 10) routing lc_trk_g0_7 input2_5 -(35 10) routing lc_trk_g1_4 input2_5 -(35 10) routing lc_trk_g1_6 input2_5 (35 10) routing lc_trk_g2_5 input2_5 (35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 -(35 11) routing lc_trk_g0_3 input2_5 (35 11) routing lc_trk_g0_7 input2_5 -(35 11) routing lc_trk_g1_2 input2_5 -(35 11) routing lc_trk_g1_6 input2_5 (35 11) routing lc_trk_g2_3 input2_5 (35 11) routing lc_trk_g2_7 input2_5 (35 11) routing lc_trk_g3_2 input2_5 @@ -3133,21 +2693,16 @@ (35 15) routing lc_trk_g3_2 input2_7 (35 15) routing lc_trk_g3_6 input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 -(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 -(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 -(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 @@ -3166,7 +2721,6 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 -(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 @@ -3260,7 +2814,6 @@ (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 -(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 @@ -3268,7 +2821,6 @@ (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 -(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 @@ -3277,7 +2829,6 @@ (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 -(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 @@ -3433,20 +2984,16 @@ (7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 (7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 diff --git a/icefuzz/database.py b/icefuzz/database.py index f8f3ccf..a0caca6 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -28,7 +28,7 @@ def read_database(filename, tile_type): line = re.sub(r"^Ram config bit:", "RamConfig", line) line = re.sub(r"^PLL config bit:", "PLL", line) line = re.sub(r"^Icegate Enable bit:", "Icegate", line) - line = re.sub(r"^MAC16 functional bit:", "DspConfig", line) + line = re.sub(r"^MAC16 functional bit:", "IpConfig", line) line = re.sub(r"^Hard IP config bit:", "IpConfig", line) line = line.split() @@ -57,14 +57,14 @@ def read_database(filename, tile_type): elif line[0] == "ColBufCtrl": line[1] = re.sub(r"B?IO(LEFT|RIGHT)_", "IO_", line[1]) line[1] = re.sub(r"IO_half_column_clock_enable_", "glb_netwk_", line[1]) - line[1] = re.sub(r"(LH|MEM[BT])_colbuf_cntl_", "glb_netwk_", line[1]) + line[1] = re.sub(r"(LH|MEM[BT]|MULT\d|IPCON)_colbuf_cntl_", "glb_netwk_", line[1]) if m.group(1) == "7": line[1] = re.sub(r"glb_netwk_", "8k_glb_netwk_", line[1]) elif m.group(1) in ["1", "2"]: line[1] = re.sub(r"glb_netwk_", "1k_glb_netwk_", line[1]) raw_db.append((bit, (line[0], line[1]))) elif line[0] == "Cascade": - match = re.match("(MULT\d|LH)_LC0(\d)_inmux02_5", line[1]) + match = re.match("LH_LC0(\d)_inmux02_5", line[1]) if match: raw_db.append((bit, ("buffer", "wire_logic_cluster/lc_%d/lout" % (int(match.group(1))-1), "input_2_%s" % match.group(1)))) else: @@ -90,11 +90,10 @@ def read_database(filename, tile_type): raw_db.append((bit, (line[0],))) elif line[0] == "Carry_In_Mux": continue - elif line[0] == "DspConfig": - line[1] = re.sub(r"MULT\d_bram_cbit_", "CBIT_", line[1]) elif line[0] == "IpConfig": line[1] = re.sub(r"MULT\d_bram_cbit_", "CBIT_", line[1]) #not a typo, sometimes IP config bits are in DSP tiles and use a MULT prefix... - line[1] = re.sub(r"IPCON_bram_cbit_", "CBIT_", line[1]) + line[1] = re.sub(r"IPCON_bram_cbit_", "CBIT_", line[1]) + raw_db.append((bit, (line[0], line[1]))) else: print("unsupported statement: %s: %s" % (bit, line)) assert False @@ -157,11 +156,11 @@ for device_class in ["5k", "8k"]: with open("database_ramt_%s.txt" % (device_class, ), "w") as f: for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class): print("\t".join(entry), file=f) -if device_class == "5k": - for dsp_idx in range(4): - with open("database_dsp%d_5k.txt" % (dsp_idx, ), "w") as f: - for entry in read_database("bitdata_dsp%d_5k.txt" % (dsp_idx, ), "dsp%d_5" % (dsp_idx, )): - print("\t".join(entry), file=f) - with open("database_ipcon.txt", "w") as f: - for entry in read_database("bitdata_ipcon.txt", "ipcon"): - print("\t".join(entry), file=f) \ No newline at end of file + +for dsp_idx in range(4): + with open("database_dsp%d_5k.txt" % (dsp_idx, ), "w") as f: + for entry in read_database("bitdata_dsp%d_5k.txt" % (dsp_idx, ), "dsp%d_5" % (dsp_idx, )): + print("\t".join(entry), file=f) +with open("database_ipcon_5k.txt", "w") as f: + for entry in read_database("bitdata_ipcon_5k.txt", "ipcon"): + print("\t".join(entry), file=f) \ No newline at end of file diff --git a/icefuzz/fuzzconfig.py b/icefuzz/fuzzconfig.py index a5c1e2c..a50cce5 100644 --- a/icefuzz/fuzzconfig.py +++ b/icefuzz/fuzzconfig.py @@ -7,6 +7,7 @@ device_class = os.getenv("ICEDEVICE") if device_class == "8k": num_ramb40 = 32 num_iobanks = 4 + num_dsp = 0 pins=""" A1 A2 A5 A6 A7 A9 A10 A11 A15 A16 @@ -32,6 +33,7 @@ if device_class == "8k": elif device_class == "384": num_ramb40 = 0 num_iobanks = 3 + num_dsp = 0 pins = """ A1 A2 A3 A4 A5 A6 A7 @@ -48,6 +50,7 @@ elif device_class == "384": elif device_class == "1k": num_ramb40 = 16 num_iobanks = 4 + num_dsp = 0 pins = """ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 @@ -60,7 +63,8 @@ elif device_class == "1k": elif device_class == "5k": num_ramb40 = 30 num_iobanks = 2 - + num_dsp = 8 + num_spram256ka = 4 #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. # Also add 14 15 16 17 which are constrained to SPI. #TODO(daveshah1): Add back I3C IO 23 which cause placement failures when assigned to @@ -73,7 +77,7 @@ elif device_class == "5k": #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. gpins = "20 35 37 44".split() - + led_pins = "39 40 41".split() def output_makefile(working_dir, fuzzname): with open(working_dir + "/Makefile", "w") as f: print("all: %s" % " ".join(["%s_%02d.bin" % (fuzzname, i) for i in range(num)]), file=f) diff --git a/icefuzz/glbcheck.py b/icefuzz/glbcheck.py index 49008ca..04a2580 100644 --- a/icefuzz/glbcheck.py +++ b/icefuzz/glbcheck.py @@ -6,26 +6,32 @@ asc_bits = set() glb_bits = set() # parsing .asc file -with open(argv[1]) as f: - current_tile = None - current_line = None - for line in f: - if line.startswith("."): - if line.find("_tile ") >= 0: - f = line.split() - current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) - current_line = 0 - else: - current_tile = None - current_line = None - continue - - if current_tile is not None: - for i in range(len(line)): - if line[i] == '1': - asc_bits.add("%s.%02d.%02d" % (current_tile, current_line, i)) - current_line += 1 +try: + with open(argv[1]) as f: + current_tile = None + current_line = None + for line in f: + if line.startswith("."): + if line.find("_tile ") >= 0: + f = line.split() + current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) + current_line = 0 + else: + current_tile = None + current_line = None + continue + if current_tile is not None: + for i in range(len(line)): + if line[i] == '1': + asc_bits.add("%s.%02d.%02d" % (current_tile, current_line, i)) + current_line += 1 +except FileNotFoundError: + print("ASC file doesn't exist, skipping glbcheck!.") + # The asc file may not exist for innocent reasons, such as + # the icecube router failing. So exit with code 0 to keep + # the fuzz Makefile happy + exit(0) # parsing .glb file with open(argv[2]) as f: current_tile = None diff --git a/icefuzz/make_dsp.py b/icefuzz/make_dsp.py new file mode 100755 index 0000000..e97f5c0 --- /dev/null +++ b/icefuzz/make_dsp.py @@ -0,0 +1,206 @@ +#!/usr/bin/env python3 + +from fuzzconfig import * +import numpy as np +import os + +device_class = os.getenv("ICEDEVICE") + +assert device_class == "5k" + +working_dir = "work_%s_dsp" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +def randbin(n): + return "".join([np.random.choice(["0", "1"]) for i in range(n)]) + +#Only certain combinations are allowed in icecube, list them here +#This is not a complete set, but enough to cover all bits except cbit13, which +#is not set in any allowed config (?) +allowed_configs = ["0010000010000001001110110", "1110000010000001001110110", "0010000010000001000000000", "1110000010000001000000000", + "0000000011000001111110110", "1100000011000001111110110", "0000000011000001110000110", "0010000101000010111111111", + "0000001001100100111111111", "0001001001100100111111111", "0001101001100100111111111", "0001111000101100000000000"] + +coverage = set() +for c in allowed_configs: + for i in range(25): + if c[i] == "1": + coverage.add(i) + +assert len(coverage) >= 24 + +#print(len(coverage)) +#print(coverage) + +for idx in range(num): + with open(working_dir + "/dsp_%02d.v" % idx, "w") as f: + glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)] + # TODO: ce should be on this list, but causes routing failures + glbs_choice = ["clk", "a", "b", "c", "d,", "ah", "bh", "ch", "dh", "irt", "irb", "ort", "orb", "olt", "olb", "ast", "asb", "oht", "ohb", "sei"] + print(""" + module top ( + input [%d:0] glb_pins, + input [%d:0] in_pins, + output [15:0] out_pins + ); + wire [%d:0] glb, glb_pins; + SB_GB gbufs [%d:0] ( + .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins), + .GLOBAL_BUFFER_OUTPUT(glb) + ); + """ % (len(glbs)-1, len(pins) - len(glbs) - 16 - 1, len(glbs)-1, len(glbs)-1), file=f) + bits = ["in_pins[%d]" % i for i in range(100)] + bits = list(np.random.permutation(bits)) + for i in range(num_dsp): + tmp = list(np.random.permutation(bits)) + bits_c = [tmp.pop() for k in range(16)] + bits_a = [tmp.pop() for k in range(16)] + bits_b = [tmp.pop() for k in range(16)] + bits_d = [tmp.pop() for k in range(16)] + bit_ce = tmp.pop() + bit_clk = tmp.pop() + bit_ahold = tmp.pop() + bit_bhold = tmp.pop() + bit_chold = tmp.pop() + bit_dhold = tmp.pop() + bit_irsttop = tmp.pop() + bit_irstbot = tmp.pop() + bit_orsttop = tmp.pop() + bit_orstbot = tmp.pop() + bit_oloadtop = tmp.pop() + bit_oloadbot = tmp.pop() + bit_addsubtop = tmp.pop() + bit_addsubbot = tmp.pop() + bit_oholdtop = tmp.pop() + bit_oholdbot = tmp.pop() + + aci_opts = ["1'b0"] + if i > 0 and i % 4 != 0: + aci_opts.append("out_%d[33]" % (i-1)); + sei_opts = ["1'b0"] + if i > 0 and i % 4 != 0: + sei_opts.append("out_%d[34]" % (i - 1)); + + bit_ci = tmp.pop() + bit_accumci = np.random.choice(aci_opts) + bit_signextin = np.random.choice(sei_opts) + + if len(glbs) != 0: + s = np.random.choice(glbs_choice) + glbs_choice.remove(s) + if s == "clk": bit_clk = glbs.pop() + if s == "a": bits_a[np.random.randint(len(bits_a))] = glbs.pop() + if s == "b": bits_b[np.random.randint(len(bits_b))] = glbs.pop() + if s == "c": bits_c[np.random.randint(len(bits_c))] = glbs.pop() + if s == "d": bits_d[np.random.randint(len(bits_d))] = glbs.pop() + if s == "ah": bit_ahold = glbs.pop() + if s == "bh": bit_bhold = glbs.pop() + if s == "ch": bit_chold = glbs.pop() + if s == "dh": bit_dhold = glbs.pop() + if s == "irt": bit_irsttop = glbs.pop() + if s == "irb": bit_irstbot = glbs.pop() + if s == "ort": bit_orsttop = glbs.pop() + if s == "orb": bit_orstbot = glbs.pop() + if s == "olt": bit_oloadtop = glbs.pop() + if s == "olb": bit_oloadbot = glbs.pop() + if s == "ast": bit_addsubtop = glbs.pop() + if s == "asb": bit_addsubbot = glbs.pop() + if s == "oht": bit_oholdtop = glbs.pop() + if s == "ohb": bit_oholdbot = glbs.pop() + if s == "ci": bit_ci = glbs.pop() + + + bits_a = "{%s}" % ", ".join(bits_a) + bits_b = "{%s}" % ", ".join(bits_b) + bits_c = "{%s}" % ", ".join(bits_c) + bits_d = "{%s}" % ", ".join(bits_d) + + negclk = randbin(1) + params = np.random.choice(allowed_configs) + params = params[::-1] + print(""" + wire [34:0] out_%d; + SB_MAC16 #( + .NEG_TRIGGER(1'b%s), + .C_REG(1'b%s), + .A_REG(1'b%s), + .B_REG(1'b%s), + .D_REG(1'b%s), + .TOP_8x8_MULT_REG(1'b%s), + .BOT_8x8_MULT_REG(1'b%s), + .PIPELINE_16x16_MULT_REG1(1'b%s), + .PIPELINE_16x16_MULT_REG2(1'b%s), + .TOPOUTPUT_SELECT(2'b%s), + .TOPADDSUB_LOWERINPUT(2'b%s), + .TOPADDSUB_UPPERINPUT(1'b%s), + .TOPADDSUB_CARRYSELECT(2'b%s), + .BOTOUTPUT_SELECT(2'b%s), + .BOTADDSUB_LOWERINPUT(2'b%s), + .BOTADDSUB_UPPERINPUT(1'b%s), + .BOTADDSUB_CARRYSELECT(2'b%s), + .MODE_8x8(1'b%s), + .A_SIGNED(1'b%s), + .B_SIGNED(1'b%s) + ) dsp_%d ( + .CLK(%s), + .CE(%s), + .C(%s), + .A(%s), + .B(%s), + .D(%s), + .AHOLD(%s), + .BHOLD(%s), + .CHOLD(%s), + .DHOLD(%s), + .IRSTTOP(%s), + .IRSTBOT(%s), + .ORSTTOP(%s), + .ORSTBOT(%s), + .OLOADTOP(%s), + .OLOADBOT(%s), + .ADDSUBTOP(%s), + .ADDSUBBOT(%s), + .OHOLDTOP(%s), + .OHOLDBOT(%s), + .CI(%s), + .ACCUMCI(%s), + .SIGNEXTIN(%s), + .O(out_%d[31:0]), + .CO(out_%d[32]), + .ACCUMCO(out_%d[33]), + .SIGNEXTOUT(out_%d[34]) + );""" + % ( + i, + negclk, + params[0], params[1], params[2], params[3], + params[4], params[5], params[6], params[7], + params[8:10][::-1], params[10:12][::-1], params[12], params[13:15][::-1], + params[15:17][::-1], params[17:19][::-1], params[19], params[20:22][::-1], + params[22], params[23], params[24], + i, + bit_clk, bit_ce, bits_c, bits_a, bits_b, bits_d, + bit_ahold, bit_bhold, bit_chold, bit_dhold, + bit_irsttop, bit_irstbot, bit_orsttop, bit_orstbot, + bit_oloadtop, bit_oloadbot, bit_addsubtop, bit_addsubbot, + bit_oholdtop, bit_oholdbot, + bit_ci, bit_accumci, bit_signextin, + i, i, i, i + ), file=f) + bits = list(np.random.permutation(bits)) + for k in range(33): + bits[k] = "out_%d[%d] ^ %s" % (i, k, bits[k]) + for k in range(16): + print("assign out_pins[%d] = out_%d[%d] ^ out_%d[%d];" % (k, i, np.random.randint(33), i, np.random.randint(33)), file=f) + print("endmodule", file=f) + with open(working_dir + "/dsp_%02d.pcf" % idx, "w") as f: + p = list(np.random.permutation(pins)) + for i in range(len(pins) - len(glbs) - 16): + print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) + for i in range(16): + print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) + + +output_makefile(working_dir, "dsp") diff --git a/icefuzz/make_upip.py b/icefuzz/make_upip.py new file mode 100755 index 0000000..be6c5e0 --- /dev/null +++ b/icefuzz/make_upip.py @@ -0,0 +1,218 @@ +#!/usr/bin/env python3 + +from fuzzconfig import * +import numpy as np +import os + +device_class = os.getenv("ICEDEVICE") + +assert device_class == "5k" + +working_dir = "work_%s_upip" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) +def randbin(n): + return "".join([np.random.choice(["0", "1"]) for i in range(n)]) +for idx in range(num): + with open(working_dir + "/upip_%02d.v" % idx, "w") as f: + glbs = ["glb[%d]" % i for i in range(np.random.randint(6)+1)] + + print(""" + module top ( + input [%d:0] glb_pins, + input [%d:0] in_pins, + output [15:0] out_pins, + output [%d:0] led_pins + ); + wire [%d:0] glb, glb_pins; + SB_GB gbufs [%d:0] ( + .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins), + .GLOBAL_BUFFER_OUTPUT(glb) + ); + """ % (len(glbs)-1, len(pins) - len(glbs) - 16 - 1, len(led_pins)-1, len(glbs)-1, len(glbs)-1), file=f) + bits = ["in_pins[%d]" % (i % (len(pins) - len(glbs) - 16 - 1)) for i in range(60)] + bits = list(np.random.permutation(bits)) + #Internal oscillators + tmp = ["in_pins[%d]" % i for i in range(len(pins) - len(glbs) - 16 - 1)] + tmp = list(np.random.permutation(tmp)) + for osc in ["LF", "HF"]: + bit_pu = tmp.pop() + bit_en = tmp.pop() + bit_clk = "clk_" + osc + glbs.append(bit_clk) + param = "" + if osc == "HF": #only HFOSC has a divider: + param = "#(.CLKHF_DIV(\"0b%s\"))" % randbin(2) + + route = np.random.choice(["", "/* synthesis ROUTE_THROUGH_FABRIC = 1 */"]) + + print(""" + SB_%sOSC %s osc_%s ( + .CLK%sPU(%s), + .CLK%sEN(%s), + .CLK%s(%s) + ) %s; + """ % ( + osc, param, osc, osc, bit_pu, + osc, bit_en, osc, bit_clk, route + ), file=f) + glbs_orig = list(glbs) + #256k SPRAM blocks + for i in range(num_spram256ka): + tmp = list(np.random.permutation(bits)) + + bits_addr = [tmp.pop() for k in range(14)] + bits_mask = [tmp.pop() for k in range(4)] + bits_wdata = [tmp.pop() for k in range(16)] + bit_wren = tmp.pop() + bit_cs = tmp.pop() + bit_clock = tmp.pop() + bit_standby = tmp.pop() + bit_sleep = tmp.pop() + bit_poweroff = tmp.pop() + + glbs_choice = ["clk", "a", "msk", "wd", "we", "cs", "stb", "slp", "po"] + + if len(glbs) != 0: + s = np.random.choice(glbs_choice) + glbs_choice.remove(s) + if s == "clk": bit_clock = glbs.pop() + if s == "a": bits_addr[np.random.randint(len(bits_addr))] = glbs.pop() + if s == "msk": bits_mask [np.random.randint(len(bits_mask ))] = glbs.pop() + if s == "wd": bits_wdata[np.random.randint(len(bits_wdata))] = glbs.pop() + if s == "we": bit_wren = glbs.pop() + if s == "cs": bit_cs = glbs.pop() + if s == "stb": bit_standby = glbs.pop() + if s == "slp": bit_sleep = glbs.pop() + if s == "po": bit_poweroff = glbs.pop() + bits_addr = "{%s}" % ", ".join(bits_addr) + bits_mask = "{%s}" % ", ".join(bits_mask) + bits_wdata = "{%s}" % ", ".join(bits_wdata) + + print(""" + wire [15:0] rdata_%d; + SB_SPRAM256KA spram_%d ( + .ADDRESS(%s), + .DATAIN(%s), + .MASKWREN(%s), + .WREN(%s), + .CHIPSELECT(%s), + .CLOCK(%s), + .STANDBY(%s), + .SLEEP(%s), + .POWEROFF(%s), + .DATAOUT(rdata_%d) + ); + """ % ( + i, i, + bits_addr, bits_wdata, bits_mask, bit_wren, + bit_cs, bit_clock, bit_standby, bit_sleep, + bit_poweroff, i + ), file=f) + bits = list(np.random.permutation(bits)) + if np.random.choice(["XOR", "MULT"]) == "MULT": + #stress routing at sides more with a multiply + print(""" + wire [31:0] mult_res_%d; + assign mult_res_%d = rdata_%d * %s; + """ % ( + i, i, i, ("{%s}" % ", ".join(bits[0:32])) + ), file=f) + for k in range(32): + bits[k] = "mult_res_%d[%d]" % (i, k) + else: + for k in range(16): + bits[k] = "rdata_%d[%d] ^ %s" % (i, k, bits[k]) + + # Internal PWM IP + tmp = list(np.random.permutation(bits)) + glbs = list(glbs_orig) + bit_cs = tmp.pop() + bit_clk = np.random.choice([glbs.pop(), tmp.pop()]) + bit_rst = np.random.choice([glbs.pop(), tmp.pop()]) + bit_den = tmp.pop() + bit_exe = tmp.pop() + + bits_dat = [tmp.pop() for k in range(8)] + bits_addr = [tmp.pop() for k in range(4)] + + print(""" + wire [2:0] pwm_out; + SB_LEDDA_IP ledda ( + .LEDDCS(%s), + .LEDDCLK(%s), + .LEDDDAT7(%s), + .LEDDDAT6(%s), + .LEDDDAT5(%s), + .LEDDDAT4(%s), + .LEDDDAT3(%s), + .LEDDDAT2(%s), + .LEDDDAT1(%s), + .LEDDDAT0(%s), + .LEDDADDR3(%s), + .LEDDADDR2(%s), + .LEDDADDR1(%s), + .LEDDADDR0(%s), + .LEDDDEN(%s), + .LEDDEXE(%s), + .LEDDRST(%s), + .PWMOUT0(pwm_out[0]), + .PWMOUT1(pwm_out[1]), + .PWMOUT2(pwm_out[2]) + ); + """ % ( + bit_cs, bit_clk, bits_dat[7], bits_dat[6], bits_dat[5], bits_dat[4], + bits_dat[3], bits_dat[2], bits_dat[1], bits_dat[0], bits_addr[3], + bits_addr[2], bits_addr[1], bits_addr[0], bit_den, bit_exe, bit_rst + ), file=f) + + bits.append("pwm_out[0]") + bits.append("pwm_out[1]") + bits.append("pwm_out[2]") + + # Constant current LED driver + current_choices = ["0b000000", "0b000001", "0b000011", "0b000111", "0b001111", "0b011111", "0b111111"] + current_modes = ["0b0", "0b1"] + + currents = [np.random.choice(current_choices) for i in range(3)] + + bit_curren = np.random.choice(bits) + bit_rgbleden = np.random.choice(bits) + bits_pwm = [np.random.choice([np.random.choice(bits), "pwm_out[%d]" % i]) for i in range(3)] + + print(""" + SB_RGBA_DRV #( + .CURRENT_MODE(\"%s\"), + .RGB0_CURRENT(\"%s\"), + .RGB1_CURRENT(\"%s\"), + .RGB2_CURRENT(\"%s\") + ) rgba_drv ( + .CURREN(%s), + .RGBLEDEN(%s), + .RGB0PWM(%s), + .RGB1PWM(%s), + .RGB2PWM(%s), + .RGB0(led_pins[0]), + .RGB1(led_pins[1]), + .RGB2(led_pins[2]) + ); + """ % ( + np.random.choice(current_modes), currents[0], currents[1], currents[2], + bit_curren, bit_rgbleden, bits_pwm[0], bits_pwm[1], bits_pwm[2] + ), file = f) + + # TODO: I2C and SPI + + print("assign out_pins = rdata_%d;" % i, file=f) + print("endmodule", file=f) + with open(working_dir + "/upip_%02d.pcf" % idx, "w") as f: + p = list(np.random.permutation(pins)) + for i in range(len(pins) - len(glbs) - 16): + print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) + for i in range(16): + print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) + for i in range(len(led_pins)): + print("set_io led_pins[%d] %s" % (i, led_pins[i]), file=f) + +output_makefile(working_dir, "upip") -- cgit v1.2.3 From 94aa596cb144cc47dc054377e1510fbb4effbfd8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 11 Nov 2017 11:26:43 +0000 Subject: Trace DSP routing --- icebox/icebox.py | 146 +- icebox/icebox_explain.py | 7 + icebox/icebox_vlog.py | 29 +- icebox/iceboxdb.py | 11086 +++++++++++++++++++++++++++++++++++---------- icefuzz/export.py | 4 +- 5 files changed, 8728 insertions(+), 2544 deletions(-) (limited to 'icefuzz') diff --git a/icebox/icebox.py b/icebox/icebox.py index fde97dc..f27d749 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -31,6 +31,8 @@ class iceconfig: self.io_tiles = dict() self.ramb_tiles = dict() self.ramt_tiles = dict() + self.dsp_tiles = [dict() for i in range(4)] + self.ipcon_tiles = dict() self.ram_data = dict() self.extra_bits = set() self.symbols = dict() @@ -96,7 +98,18 @@ class iceconfig: for x in range(1, self.max_x): self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)] self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)] - + for x in [0, self.max_x]: + for y in range(1, self.max_y): + if y in [5, 10, 15, 23]: + self.dsp_tiles[0][(x, y)] = ["0" * 54 for i in range(16)] + elif y in [6, 11, 16, 24]: + self.dsp_tiles[1][(x, y)] = ["0" * 54 for i in range(16)] + elif y in [7, 12, 17, 25]: + self.dsp_tiles[2][(x, y)] = ["0" * 54 for i in range(16)] + elif y in [8, 13, 18, 26]: + self.dsp_tiles[3][(x, y)] = ["0" * 54 for i in range(16)] + else: + self.ipcon_tiles[(x, y)] = ["0" * 54 for i in range(16)] def setup_empty_8k(self): self.clear() self.device = "8k" @@ -132,6 +145,9 @@ class iceconfig: if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)] if (x, y) in self.ramb_tiles: return self.ramb_tiles[(x, y)] if (x, y) in self.ramt_tiles: return self.ramt_tiles[(x, y)] + for i in range(4): + if (x, y) in self.dsp_tiles[i]: return self.dsp_tiles[i][(x, y)] + if (x, y) in self.ipcon_tiles: return self.ipcon_tiles[(x, y)] return None def pinloc_db(self): @@ -242,6 +258,12 @@ class iceconfig: if (x, y) in self.logic_tiles: return logictile_5k_db if (x, y) in self.ramb_tiles: return rambtile_5k_db if (x, y) in self.ramt_tiles: return ramttile_5k_db + if (x, y) in self.ipcon_tiles: return ipcon_5k_db + if (x, y) in self.dsp_tiles[0]: return dsp0_5k_db + if (x, y) in self.dsp_tiles[1]: return dsp1_5k_db + if (x, y) in self.dsp_tiles[2]: return dsp2_5k_db + if (x, y) in self.dsp_tiles[3]: return dsp3_5k_db + elif self.device == "8k": if (x, y) in self.logic_tiles: return logictile_8k_db if (x, y) in self.ramb_tiles: return rambtile_8k_db @@ -253,13 +275,24 @@ class iceconfig: assert False def tile_type(self, x, y): - if x == 0: return "IO" + if x == 0 and self.device != "5k": return "IO" if y == 0: return "IO" - if x == self.max_x: return "IO" + if x == self.max_x and self.device != "5k": return "IO" if y == self.max_y: return "IO" if (x, y) in self.ramb_tiles: return "RAMB" if (x, y) in self.ramt_tiles: return "RAMT" if (x, y) in self.logic_tiles: return "LOGIC" + if (x == 0 or x == self.max_x) and self.device == "5k": + if y in [5, 10, 15, 23]: + return "DSP0" + elif y in [6, 11, 16, 24]: + return "DSP1" + elif y in [7, 12, 17, 25]: + return "DSP2" + elif y in [8, 13, 18, 26]: + return "DSP3" + else: + return "IPCON" assert False def tile_pos(self, x, y): @@ -307,11 +340,17 @@ class iceconfig: return pos_has_net(self.tile_pos(x, y), netname) def tile_follow_net(self, x, y, direction, netname): - if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname) - if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname) - if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname) - if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname) - return pos_follow_net(self.tile_pos(x, y), direction, netname) + if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname, self.device) + if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname, self.device) + if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname, self.device) + if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname, self.device) + if self.device == "5k": + if y == 1 and x in (0, self.max_x) and direction == 'b': return pos_follow_net(self.tile_pos(x, y), "B", netname, self.device) + if y == self.max_y-1 and x in (0, self.max_x) and direction == 't': return pos_follow_net(self.tile_pos(x, y), "T", netname, self.device) + if x == 1 and y in (0, self.max_y) and direction == 'l': return pos_follow_net(self.tile_pos(x, y), "L", netname, self.device) + if x == self.max_x-1 and y in (0, self.max_y) and direction == 'r': return pos_follow_net(self.tile_pos(x, y), "R", netname, self.device) + + return pos_follow_net(self.tile_pos(x, y), direction, netname, self.device) def follow_funcnet(self, x, y, func): neighbours = set() @@ -340,6 +379,9 @@ class iceconfig: if npos == "x": if (nx, ny) in self.logic_tiles: return (nx, ny, "lutff_%d/out" % func) + for i in range(4): + if (nx, ny) in self.dsp_tiles[i]: #TODO: check this + return (nx, ny, "mult/O_%d" % (i * 8 + func)) if (nx, ny) in self.ramb_tiles: if self.device == "1k": return (nx, ny, "ram/RDATA_%d" % func) @@ -423,12 +465,12 @@ class iceconfig: neighbours.add((nx, ny, netname)) match = re.match(r"sp4_r_v_b_(\d+)", netname) - if match and 0 < x < self.max_x-1: + if match and ((0 < x < self.max_x-1) or (self.device == "5k")): neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1)))) #print('\tafter r_v_b', neighbours) match = re.match(r"sp4_v_[bt]_(\d+)", netname) - if match and 1 < x < self.max_x: + if match and (1 < x < self.max_x or ((self.device == "5k") and (x > 0))): n = sp4v_normalize(netname, "b") if n is not None: n = n.replace("sp4_", "sp4_r_") @@ -459,9 +501,19 @@ class iceconfig: if s[0] in (0, self.max_x) and s[1] in (0, self.max_y): if re.match("span4_(vert|horz)_[lrtb]_\d+$", n): + vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") - + + if self.device == "5k": + m = re.match("span4_vert_([lrtb])_(\d+)$", vert_net) + assert m + vert_net = "sp4_v_%s_%d" % (m.group(1), int(m.group(2)) + 28) + + m = re.match("span4_horz_([lrtb])_(\d+)$", horz_net) + assert m + horz_net = "span4_horz_%s_%d" % (m.group(1), int(m.group(2)) - 28) + if s[0] == 0 and s[1] == 0: if direction == "l": s = (0, 1, vert_net) if direction == "b": s = (1, 0, horz_net) @@ -470,9 +522,18 @@ class iceconfig: if direction == "r": s = (self.max_x, self.max_y-1, vert_net) if direction == "t": s = (self.max_x-1, self.max_y, horz_net) - vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") - horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") - + vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_").replace("_h_", "_v_") + horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_").replace("_v_", "_h_") + + if self.device == "5k": + m = re.match("(span4_vert|sp4_v)_([lrtb])_(\d+)$", vert_net) + assert m + vert_net = "sp4_v_%s_%d" % (m.group(2), int(m.group(3)) + 28) + + m = re.match("(span4_horz|sp4_h)_([lrtb])_(\d+)$", horz_net) + assert m + horz_net = "span4_horz_%s_%d" % (m.group(2), int(m.group(3)) - 28) + if s[0] == 0 and s[1] == self.max_y: if direction == "l": s = (0, self.max_y-1, vert_net) if direction == "t": s = (1, self.max_y, horz_net) @@ -566,7 +627,22 @@ class iceconfig: add_seed_segments(idx, tile, ramttile_8k_db) else: assert False - + + for idx, tile in self.dsp_tiles[0].items(): + if self.device == "5k": + add_seed_segments(idx, tile, dsp0_5k_db) + for idx, tile in self.dsp_tiles[1].items(): + if self.device == "5k": + add_seed_segments(idx, tile, dsp1_5k_db) + for idx, tile in self.dsp_tiles[2].items(): + if self.device == "5k": + add_seed_segments(idx, tile, dsp2_5k_db) + for idx, tile in self.dsp_tiles[3].items(): + if self.device == "5k": + add_seed_segments(idx, tile, dsp3_5k_db) + for idx, tile in self.ipcon_tiles.items(): + if self.device == "5k": + add_seed_segments(idx, tile, ipcon_5k_db) for padin, pio in enumerate(self.padin_pio_db()): s1 = (pio[0], pio[1], "padin_%d" % pio[2]) s2 = (pio[0], pio[1], "glb_netwk_%d" % padin) @@ -661,7 +737,7 @@ class iceconfig: expected_data_lines -= 1 continue assert expected_data_lines <= 0 - if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data", ".ipconn_tile", ".dsp1_tile", ".dsp2_tile", ".dsp3_tile", ".dsp4_tile"): + if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data", ".ipcon_tile", ".dsp0_tile", ".dsp1_tile", ".dsp2_tile", ".dsp3_tile"): current_data = list() expected_data_lines = 16 self.max_x = max(self.max_x, int(line[1])) @@ -678,6 +754,13 @@ class iceconfig: if line[0] == ".ramt_tile": self.ramt_tiles[(int(line[1]), int(line[2]))] = current_data continue + if line[0] == ".ipcon_tile": + self.ipcon_tiles[(int(line[1]), int(line[2]))] = current_data + continue + match = re.match(r".dsp(\d)_tile", line[0]) + if match: + self.dsp_tiles[int(match.group(1))][(int(line[1]), int(line[2]))] = current_data + continue if line[0] == ".ram_data": self.ram_data[(int(line[1]), int(line[2]))] = current_data continue @@ -862,6 +945,8 @@ def netname_normalize(netname, edge="", ramb=False, ramt=False, ramb_8k=False, r netname = netname.replace("lc_", "lutff_") netname = netname.replace("wire_logic_cluster/", "") netname = netname.replace("wire_io_cluster/", "") + netname = netname.replace("wire_mult/", "") + netname = netname.replace("wire_con_box/", "") netname = netname.replace("wire_bram/", "") if (ramb or ramt or ramb_8k or ramt_8k) and netname.startswith("input"): match = re.match(r"input(\d)_(\d)", netname) @@ -890,13 +975,13 @@ def pos_has_net(pos, netname): if re.search(r"_vert_[bt]_\d+$", netname): return False return True -def pos_follow_net(pos, direction, netname): - if pos == "x": +def pos_follow_net(pos, direction, netname, device): + if pos == "x" or ((pos in ("l", "r")) and (device == "5k")): m = re.match("sp4_h_[lr]_(\d+)$", netname) if m and direction in ("l", "L"): n = sp4h_normalize(netname, "l") if n is not None: - if direction == "l": + if direction == "l" or device == "5k": n = re.sub("_l_", "_r_", n) n = sp4h_normalize(n) else: @@ -906,7 +991,7 @@ def pos_follow_net(pos, direction, netname): if m and direction in ("r", "R"): n = sp4h_normalize(netname, "r") if n is not None: - if direction == "r": + if direction == "r" or device == "5k": n = re.sub("_r_", "_l_", n) n = sp4h_normalize(n) else: @@ -916,6 +1001,8 @@ def pos_follow_net(pos, direction, netname): m = re.match("sp4_v_[tb]_(\d+)$", netname) if m and direction in ("t", "T"): + if device == "5k" and direction == "T" and pos in ("l", "r"): + return re.sub("sp4_v_", "span4_vert_", netname) n = sp4v_normalize(netname, "t") if n is not None: if direction == "t": @@ -926,6 +1013,8 @@ def pos_follow_net(pos, direction, netname): n = re.sub("sp4_v_", "span4_vert_", n) return n if m and direction in ("b", "B"): + if device == "5k" and direction == "B" and pos in ("l", "r"): + return re.sub("sp4_v_", "span4_vert_", netname) n = sp4v_normalize(netname, "b") if n is not None: if direction == "b": @@ -940,7 +1029,7 @@ def pos_follow_net(pos, direction, netname): if m and direction in ("l", "L"): n = sp12h_normalize(netname, "l") if n is not None: - if direction == "l": + if direction == "l" or device == "5k": n = re.sub("_l_", "_r_", n) n = sp12h_normalize(n) else: @@ -950,7 +1039,7 @@ def pos_follow_net(pos, direction, netname): if m and direction in ("r", "R"): n = sp12h_normalize(netname, "r") if n is not None: - if direction == "r": + if direction == "r" or device == "5k": n = re.sub("_r_", "_l_", n) n = sp12h_normalize(n) else: @@ -980,7 +1069,7 @@ def pos_follow_net(pos, direction, netname): n = re.sub("sp12_v_", "span12_vert_", n) return n - if pos in ("l", "r" ): + if (pos in ("l", "r" )) and (device != "5k"): m = re.match("span4_vert_([bt])_(\d+)$", netname) if m: case, idx = direction + m.group(1), int(m.group(2)) @@ -997,6 +1086,8 @@ def pos_follow_net(pos, direction, netname): m = re.match("span4_horz_([rl])_(\d+)$", netname) if m: case, idx = direction + m.group(1), int(m.group(2)) + if direction == "L" or direction == "R": + return netname if case == "ll": return "span4_horz_r_%d" % idx if case == "lr" and idx >= 4: @@ -4179,6 +4270,13 @@ ramttile_5k_db = parse_db(iceboxdb.database_ramt_5k_txt, "5k") rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, "8k") ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, "8k") +ipcon_5k_db = parse_db(iceboxdb.database_ipcon_5k_txt, "5k") +dsp0_5k_db = parse_db(iceboxdb.database_dsp0_5k_txt, "5k") +dsp1_5k_db = parse_db(iceboxdb.database_dsp1_5k_txt, "5k") +dsp2_5k_db = parse_db(iceboxdb.database_dsp2_5k_txt, "5k") +dsp3_5k_db = parse_db(iceboxdb.database_dsp3_5k_txt, "5k") + + iotile_l_db = list() iotile_r_db = list() iotile_t_db = list() @@ -4232,7 +4330,7 @@ iotile_b_5k_db.append([["B15[14]"], "IoCtrl", "padeb_test_0"]) iotile_b_5k_db.append([["B6[15]"], "IoCtrl", "cf_bit_35"]) iotile_b_5k_db.append([["B12[15]"], "IoCtrl", "cf_bit_39"]) -for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db]: +for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db, dsp0_5k_db, dsp1_5k_db, dsp2_5k_db, dsp3_5k_db, ipcon_5k_db]: for entry in db: if entry[1] in ("buffer", "routing"): entry[2] = netname_normalize(entry[2], diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py index 50cce09..3b9875f 100755 --- a/icebox/icebox_explain.py +++ b/icebox/icebox_explain.py @@ -166,6 +166,13 @@ for idx in ic.ramb_tiles: for idx in ic.ramt_tiles: print_tile(".ramt_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramt_tiles[idx], ic.tile_db(idx[0], idx[1])) +for i in range(4): + for idx in ic.dsp_tiles[i]: + print_tile(".dsp%d_tile %d %d" % (i, idx[0], idx[1]), ic, idx[0], idx[1], ic.dsp_tiles[i][idx], ic.tile_db(idx[0], idx[1])) + +for idx in ic.ipcon_tiles: + print_tile(".ipcon_tile %d %d" % idx, ic, idx[0], idx[1], ic.ipcon_tiles[idx], ic.tile_db(idx[0], idx[1])) + for bit in ic.extra_bits: print() print(".extra_bit %d %d %d" % bit) diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py index 1b19d10..8f6bf7c 100755 --- a/icebox/icebox_vlog.py +++ b/icebox/icebox_vlog.py @@ -136,6 +136,7 @@ text_wires = list() text_ports = list() luts_queue = set() +special_5k_queue = set() text_func = list() failed_drivers_check = list() @@ -315,7 +316,11 @@ for segs in sorted(ic.group_segments(extra_connections=extra_connections, extra_ match = re.match("lutff_(\d+)/", s[2]) if match: - luts_queue.add((s[0], s[1], int(match.group(1)))) + #IpCon and DSP tiles look like logic tiles, but aren't. + if ic.device == "5k" and (s[0] == 0 or s[0] == ic.max_x): + special_5k_queue.add((s[0], s[1])) + else: + luts_queue.add((s[0], s[1], int(match.group(1)))) nets[n] = segs @@ -752,6 +757,28 @@ for tile in ic.ramb_tiles: text_func.append(");") text_func.append("") +for i in range(4): + for tile in ic.dsp_tiles[i]: + if tile in special_5k_queue: + #TODO: print config + x = tile[0] + y = tile[1] + net_clk = seg_to_net((x, y, "lutff_global/clk"), "1'b0") + net_sr = seg_to_net((x, y, "lutff_global/s_r"), "1'b0") + #TEMP: for tracing only + text_func.append("/* DSP%d %2d %2d */ assign dsp%d_%d_%d_clk = %s;" % (i, x, y, i, x, y, net_clk)) + text_func.append("/* DSP%d %2d %2d */ assign dsp%d_%d_%d_sr = %s;" % (i, x, y, i, x, y, net_sr)) + for j in range(7): + net_in0 = seg_to_net((x, y, "lutff_%d/in_0" % j), "1'b0") + net_in1 = seg_to_net((x, y, "lutff_%d/in_1" % j), "1'b0") + net_in2 = seg_to_net((x, y, "lutff_%d/in_2" % j), "1'b0") + net_in3 = seg_to_net((x, y, "lutff_%d/in_3" % j), "1'b0") + #TODO: cin, cout + text_func.append("/* DSP%d %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_0 = %s;" % (i, x, y, j, i, x, y, j, net_in0)) + text_func.append("/* DSP%d %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_1 = %s;" % (i, x, y, j, i, x, y, j, net_in1)) + text_func.append("/* DSP%d %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_2 = %s;" % (i, x, y, j, i, x, y, j, net_in2)) + text_func.append("/* DSP%d %2d %2d %d*/ assign dsp%d_%d_%d_in_%d_3 = %s;" % (i, x, y, j, i, x, y, j, net_in3)) + wire_to_reg = set() lut_assigns = list() const_assigns = list() diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index 6da43c9..a8b6990 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -5329,7 +5329,15 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ -database_ramb_5k_txt = """ +database_ipcon_5k_txt = """ +B0[50] Cascade IPCON_LC00_inmux02_5 +B2[50] Cascade IPCON_LC01_inmux02_5 +B4[50] Cascade IPCON_LC02_inmux02_5 +B6[50] Cascade IPCON_LC03_inmux02_5 +B8[50] Cascade IPCON_LC04_inmux02_5 +B10[50] Cascade IPCON_LC05_inmux02_5 +B12[50] Cascade IPCON_LC06_inmux02_5 +B14[50] Cascade IPCON_LC07_inmux02_5 B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 @@ -5338,8 +5346,22 @@ B13[7] ColBufCtrl 8k_glb_netwk_4 B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 -B0[0] NegClk -B1[7] RamConfig PowerUp +B1[7] IpConfig CBIT_0 +B0[7] IpConfig CBIT_1 +B3[7] IpConfig CBIT_2 +B2[7] IpConfig CBIT_3 +B5[7] IpConfig CBIT_4 +B4[7] IpConfig CBIT_5 +B7[7] IpConfig CBIT_6 +B6[7] IpConfig CBIT_7 +B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43] LC_0 +B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43] LC_1 +B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43] LC_2 +B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43] LC_3 +B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43] LC_4 +B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43] LC_5 +B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43] LC_6 +B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43] LC_7 B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 @@ -5372,489 +5394,439 @@ B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 -!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 !B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 -!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 +B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer bot_op_1 lc_trk_g1_1 !B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer bot_op_3 lc_trk_g0_3 !B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 !B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 -!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 +B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer bot_op_5 lc_trk_g1_5 !B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer bot_op_7 lc_trk_g0_7 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 clk +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 clk !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 -!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK -B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK -!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 clk +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 clk B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 -B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 clk !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 -!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK -B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 clk !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 -!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK -B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 clk B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 -B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK -B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 clk B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 -B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK -!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 -!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 -!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 -!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 -!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 -!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK -!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8 -!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 -!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 -!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 -!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 -!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 -!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 -!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 -!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 -!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 -!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 -!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 -!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 -!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE -!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 -!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 -!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 -!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 -!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 -!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 -!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 -B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 -B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 -B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 -B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 -B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 -B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 -!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE -!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 -B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 -B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 -B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 -B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 -B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 -B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 -B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 -B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 -B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 -B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 -B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 -B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 -B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 -!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 -B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 -B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 -B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 -B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 -B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 -B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 -B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 -!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 -!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 -!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 -!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 -!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 -!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 -!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 -!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 -!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 -!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 -!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 -!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 -!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 -!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK -B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 -!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 -!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 -!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 -!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 -!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 -!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 -!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 -!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 -!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 -!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 -!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 -!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 -!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 -!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE -B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 -B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 -B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 -B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 -B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 -B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 -B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 -B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 -B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 -B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 -B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 -B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 -B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 -B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 -!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE -B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 -B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 -B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 -B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 -B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 -B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 -B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 -B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 -B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 -B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 -B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 -B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 -B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 -B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 -B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 -!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 -!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 -!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 -!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 -!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 -!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 -B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK -!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 -!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 -!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 -!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 -!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 -!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 -!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 -!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 -!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 -!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 -!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 -!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 -!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 -!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 -B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE -!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 -!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 -!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 -!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 -!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 -!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 -!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 -!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 -B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 -B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 -B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 -B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 -B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 -B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 -B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE -!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 -B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 -B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 -B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 -B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 -B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 -B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 -B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 -B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 -B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 -B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 -B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 -B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 -B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 -!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 -B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 -B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 -B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 -B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 -B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 -B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 -B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 -!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 -!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 -!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 -!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 -!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 -!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 -!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 -!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 -!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 -!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 -!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 -!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 -!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 -B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK -B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8 -!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 -!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 -!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 -!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 -!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 -!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 -!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 -!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 -!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 -!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 -!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 -!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 -!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 -B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE -B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8 -B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 -B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 -B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 -B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 -B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 -B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 -B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 -B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 -B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 -B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 -B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 -B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 -B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 -B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE -B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 -B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 -B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 -B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 -B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 -B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 -B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 -B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 -B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 -B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 -B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 -B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 -B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 -B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 -B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 clk +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_con_box/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_con_box/lc_1/in_1 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 wire_con_box/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_con_box/lc_3/in_1 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 wire_con_box/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_con_box/lc_5/in_1 +!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 wire_con_box/lc_6/in_0 +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_con_box/lc_7/in_1 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_con_box/lc_0/in_1 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 wire_con_box/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_con_box/lc_2/in_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 wire_con_box/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_con_box/lc_4/in_1 +!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 wire_con_box/lc_5/in_0 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_con_box/lc_6/in_1 +!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 wire_con_box/lc_7/in_0 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_con_box/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_con_box/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_con_box/lc_1/in_3 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 wire_con_box/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_con_box/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_con_box/lc_3/in_3 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 wire_con_box/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_con_box/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_con_box/lc_5/in_3 +!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 wire_con_box/lc_6/in_0 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_con_box/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_con_box/lc_7/in_3 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_con_box/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_con_box/lc_0/in_3 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 wire_con_box/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_con_box/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_con_box/lc_2/in_3 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 wire_con_box/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_con_box/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_con_box/lc_4/in_3 +!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 wire_con_box/lc_5/in_0 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_con_box/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_con_box/lc_6/in_3 +!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 wire_con_box/lc_7/in_0 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_con_box/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_con_box/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_con_box/lc_1/in_3 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 wire_con_box/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_con_box/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_con_box/lc_3/in_3 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 wire_con_box/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_con_box/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_con_box/lc_5/in_3 +B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 wire_con_box/lc_6/in_0 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_con_box/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_con_box/lc_7/in_3 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_con_box/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_con_box/lc_0/in_3 +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 wire_con_box/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_con_box/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_con_box/lc_2/in_3 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 wire_con_box/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_con_box/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_con_box/lc_4/in_3 +B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 wire_con_box/lc_5/in_0 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_con_box/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_con_box/lc_6/in_3 +B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 wire_con_box/lc_7/in_0 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_con_box/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_con_box/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_con_box/lc_1/in_3 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 wire_con_box/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_con_box/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_con_box/lc_3/in_3 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 wire_con_box/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_con_box/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_con_box/lc_5/in_3 +B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 wire_con_box/lc_6/in_0 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_con_box/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_con_box/lc_7/in_3 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_con_box/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_con_box/lc_0/in_3 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 wire_con_box/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_con_box/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_con_box/lc_2/in_3 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 wire_con_box/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_con_box/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_con_box/lc_4/in_3 +B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 wire_con_box/lc_5/in_0 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_con_box/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_con_box/lc_6/in_3 +B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 wire_con_box/lc_7/in_0 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_con_box/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_con_box/lc_0/in_3 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 wire_con_box/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_con_box/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_con_box/lc_2/in_3 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 wire_con_box/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_con_box/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_con_box/lc_4/in_3 +!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 wire_con_box/lc_5/in_0 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_con_box/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_con_box/lc_6/in_3 +!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 wire_con_box/lc_7/in_0 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 clk +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_con_box/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_con_box/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_con_box/lc_1/in_3 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 wire_con_box/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_con_box/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_con_box/lc_3/in_3 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 wire_con_box/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_con_box/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_con_box/lc_5/in_3 +!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 wire_con_box/lc_6/in_0 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_con_box/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_con_box/lc_7/in_3 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_con_box/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_con_box/lc_0/in_3 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 wire_con_box/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_con_box/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_con_box/lc_2/in_3 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 wire_con_box/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_con_box/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_con_box/lc_4/in_3 +!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 wire_con_box/lc_5/in_0 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_con_box/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_con_box/lc_6/in_3 +!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 wire_con_box/lc_7/in_0 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_con_box/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_con_box/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_con_box/lc_1/in_3 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 wire_con_box/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_con_box/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_con_box/lc_3/in_3 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 wire_con_box/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_con_box/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_con_box/lc_5/in_3 +!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 wire_con_box/lc_6/in_0 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_con_box/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_con_box/lc_7/in_3 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_con_box/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_con_box/lc_0/in_3 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 wire_con_box/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_con_box/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_con_box/lc_2/in_3 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 wire_con_box/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_con_box/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_con_box/lc_4/in_3 +B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 wire_con_box/lc_5/in_0 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_con_box/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_con_box/lc_6/in_3 +B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 wire_con_box/lc_7/in_0 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_con_box/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_con_box/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_con_box/lc_1/in_3 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 wire_con_box/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_con_box/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_con_box/lc_3/in_3 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 wire_con_box/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_con_box/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_con_box/lc_5/in_3 +B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 wire_con_box/lc_6/in_0 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_con_box/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_con_box/lc_7/in_3 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_con_box/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_con_box/lc_0/in_3 +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 wire_con_box/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_con_box/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_con_box/lc_2/in_3 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 wire_con_box/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_con_box/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_con_box/lc_4/in_3 +B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 wire_con_box/lc_5/in_0 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_con_box/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_con_box/lc_6/in_3 +B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 wire_con_box/lc_7/in_0 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_con_box/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_con_box/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_con_box/lc_1/in_3 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 wire_con_box/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_con_box/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_con_box/lc_3/in_3 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 wire_con_box/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_con_box/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_con_box/lc_5/in_3 +B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 wire_con_box/lc_6/in_0 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_con_box/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_con_box/lc_7/in_3 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 clk +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_con_box/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_con_box/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_con_box/lc_1/in_3 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 wire_con_box/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_con_box/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_con_box/lc_3/in_3 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 wire_con_box/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_con_box/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_con_box/lc_5/in_3 +!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 wire_con_box/lc_6/in_0 +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_con_box/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_con_box/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_con_box/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_con_box/lc_0/in_3 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 wire_con_box/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_con_box/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_con_box/lc_2/in_3 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 wire_con_box/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_con_box/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_con_box/lc_4/in_3 +!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 wire_con_box/lc_5/in_0 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_con_box/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_con_box/lc_6/in_3 +!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 wire_con_box/lc_7/in_0 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_con_box/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_con_box/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_con_box/lc_1/in_3 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 wire_con_box/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_con_box/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_con_box/lc_3/in_3 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 wire_con_box/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_con_box/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_con_box/lc_5/in_3 +!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 wire_con_box/lc_6/in_0 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_con_box/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_con_box/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_con_box/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_con_box/lc_0/in_3 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 wire_con_box/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_con_box/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_con_box/lc_2/in_3 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 wire_con_box/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_con_box/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_con_box/lc_4/in_3 +!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 wire_con_box/lc_5/in_0 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_con_box/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_con_box/lc_6/in_3 +!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 wire_con_box/lc_7/in_0 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_con_box/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_con_box/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_con_box/lc_1/in_3 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 wire_con_box/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_con_box/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_con_box/lc_3/in_3 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 wire_con_box/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_con_box/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_con_box/lc_5/in_3 +B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 wire_con_box/lc_6/in_0 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_con_box/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_con_box/lc_7/in_3 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_con_box/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_con_box/lc_0/in_3 +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 wire_con_box/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_con_box/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_con_box/lc_2/in_3 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 wire_con_box/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_con_box/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_con_box/lc_4/in_3 +B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 wire_con_box/lc_5/in_0 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_con_box/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_con_box/lc_6/in_3 +B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 wire_con_box/lc_7/in_0 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_con_box/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_con_box/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_con_box/lc_1/in_3 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 wire_con_box/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_con_box/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_con_box/lc_3/in_3 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 wire_con_box/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_con_box/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_con_box/lc_5/in_3 +B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 wire_con_box/lc_6/in_0 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_con_box/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_con_box/lc_7/in_3 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_con_box/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_con_box/lc_0/in_3 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 wire_con_box/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_con_box/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_con_box/lc_2/in_3 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 wire_con_box/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_con_box/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_con_box/lc_4/in_3 +B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 wire_con_box/lc_5/in_0 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_con_box/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_con_box/lc_6/in_3 +B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 wire_con_box/lc_7/in_0 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_con_box/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_con_box/lc_0/in_3 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 wire_con_box/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_con_box/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_con_box/lc_2/in_3 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 wire_con_box/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_con_box/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_con_box/lc_4/in_3 +!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 wire_con_box/lc_5/in_0 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_con_box/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_con_box/lc_6/in_3 +!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 wire_con_box/lc_7/in_0 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 clk +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_con_box/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_con_box/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_con_box/lc_1/in_3 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 wire_con_box/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_con_box/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_con_box/lc_3/in_3 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 wire_con_box/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_con_box/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_con_box/lc_5/in_3 +!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 wire_con_box/lc_6/in_0 +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_con_box/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_con_box/lc_7/in_3 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_con_box/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_con_box/lc_0/in_3 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 wire_con_box/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_con_box/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_con_box/lc_2/in_3 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 wire_con_box/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_con_box/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_con_box/lc_4/in_3 +!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 wire_con_box/lc_5/in_0 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_con_box/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_con_box/lc_6/in_3 +!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 wire_con_box/lc_7/in_0 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_con_box/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_con_box/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_con_box/lc_1/in_3 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 wire_con_box/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_con_box/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_con_box/lc_3/in_3 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 wire_con_box/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_con_box/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_con_box/lc_5/in_3 +!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 wire_con_box/lc_6/in_0 +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_con_box/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_con_box/lc_7/in_3 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_con_box/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_con_box/lc_0/in_3 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 wire_con_box/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_con_box/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_con_box/lc_2/in_3 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 wire_con_box/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_con_box/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_con_box/lc_4/in_3 +B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 wire_con_box/lc_5/in_0 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_con_box/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_con_box/lc_6/in_3 +B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 wire_con_box/lc_7/in_0 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_con_box/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_con_box/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_con_box/lc_1/in_3 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 wire_con_box/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_con_box/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_con_box/lc_3/in_3 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 wire_con_box/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_con_box/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_con_box/lc_5/in_3 +B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 wire_con_box/lc_6/in_0 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_con_box/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_con_box/lc_7/in_3 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_con_box/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_con_box/lc_0/in_3 +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 wire_con_box/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_con_box/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_con_box/lc_2/in_3 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 wire_con_box/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_con_box/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_con_box/lc_4/in_3 +B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 wire_con_box/lc_5/in_0 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_con_box/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_con_box/lc_6/in_3 +B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 wire_con_box/lc_7/in_0 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_con_box/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_con_box/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_con_box/lc_1/in_3 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 wire_con_box/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_con_box/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_con_box/lc_3/in_3 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 wire_con_box/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_con_box/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_con_box/lc_5/in_3 +B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 wire_con_box/lc_6/in_0 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_con_box/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_con_box/lc_7/in_3 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 @@ -5887,33 +5859,136 @@ B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer slf_op_0 lc_trk_g2_0 +B0[47] buffer slf_op_0 sp12_h_l_7 +B0[51] buffer slf_op_0 sp12_v_b_0 +B0[52] buffer slf_op_0 sp12_v_b_16 +B1[47] buffer slf_op_0 sp4_h_l_21 +B1[46] buffer slf_op_0 sp4_h_r_0 +B0[46] buffer slf_op_0 sp4_h_r_16 +B1[52] buffer slf_op_0 sp4_r_v_b_1 +B0[53] buffer slf_op_0 sp4_r_v_b_17 +B1[53] buffer slf_op_0 sp4_r_v_b_33 +B0[48] buffer slf_op_0 sp4_v_b_0 +B1[51] buffer slf_op_0 sp4_v_t_21 +B1[48] buffer slf_op_0 sp4_v_t_5 +!B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer slf_op_1 lc_trk_g3_1 +B2[47] buffer slf_op_1 sp12_h_l_9 +B2[51] buffer slf_op_1 sp12_v_t_1 +B2[52] buffer slf_op_1 sp12_v_t_17 +B2[46] buffer slf_op_1 sp4_h_l_7 +B3[46] buffer slf_op_1 sp4_h_r_2 +B3[47] buffer slf_op_1 sp4_h_r_34 +B2[53] buffer slf_op_1 sp4_r_v_b_19 +B3[52] buffer slf_op_1 sp4_r_v_b_3 +B3[53] buffer slf_op_1 sp4_r_v_b_35 +B3[48] buffer slf_op_1 sp4_v_b_18 +B2[48] buffer slf_op_1 sp4_v_b_2 +B3[51] buffer slf_op_1 sp4_v_t_23 +B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer slf_op_2 lc_trk_g3_2 +B4[47] buffer slf_op_2 sp12_h_l_11 +B4[52] buffer slf_op_2 sp12_v_b_20 +B4[51] buffer slf_op_2 sp12_v_b_4 +B4[46] buffer slf_op_2 sp4_h_r_20 +B5[47] buffer slf_op_2 sp4_h_r_36 +B5[46] buffer slf_op_2 sp4_h_r_4 +B4[53] buffer slf_op_2 sp4_r_v_b_21 +B5[53] buffer slf_op_2 sp4_r_v_b_37 +B5[52] buffer slf_op_2 sp4_r_v_b_5 +B5[51] buffer slf_op_2 sp4_v_b_36 +B4[48] buffer slf_op_2 sp4_v_b_4 +B5[48] buffer slf_op_2 sp4_v_t_9 +B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer slf_op_3 lc_trk_g0_3 +B6[47] buffer slf_op_3 sp12_h_r_14 +B6[51] buffer slf_op_3 sp12_v_b_6 +B6[52] buffer slf_op_3 sp12_v_t_21 +B6[46] buffer slf_op_3 sp4_h_l_11 +B7[47] buffer slf_op_3 sp4_h_r_38 +B7[46] buffer slf_op_3 sp4_h_r_6 +B6[53] buffer slf_op_3 sp4_r_v_b_23 +B7[53] buffer slf_op_3 sp4_r_v_b_39 +B7[52] buffer slf_op_3 sp4_r_v_b_7 +B7[48] buffer slf_op_3 sp4_v_b_22 +B6[48] buffer slf_op_3 sp4_v_b_6 +B7[51] buffer slf_op_3 sp4_v_t_27 +B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer slf_op_4 lc_trk_g3_4 +B8[48] buffer slf_op_4 sp12_h_l_15 +B8[47] buffer slf_op_4 sp12_h_r_0 +B8[52] buffer slf_op_4 sp12_v_t_7 +B9[47] buffer slf_op_4 sp4_h_l_29 +B8[46] buffer slf_op_4 sp4_h_r_24 +B9[46] buffer slf_op_4 sp4_h_r_8 +B8[53] buffer slf_op_4 sp4_r_v_b_25 +B9[53] buffer slf_op_4 sp4_r_v_b_41 +B9[52] buffer slf_op_4 sp4_r_v_b_9 +B8[51] buffer slf_op_4 sp4_v_b_40 +B9[48] buffer slf_op_4 sp4_v_b_8 +B9[51] buffer slf_op_4 sp4_v_t_13 +B10[47] buffer slf_op_5 sp12_h_l_1 +B10[48] buffer slf_op_5 sp12_h_l_17 +B10[52] buffer slf_op_5 sp12_v_b_10 +B11[46] buffer slf_op_5 sp4_h_r_10 +B10[46] buffer slf_op_5 sp4_h_r_26 +B11[47] buffer slf_op_5 sp4_h_r_42 +B11[52] buffer slf_op_5 sp4_r_v_b_11 +B10[53] buffer slf_op_5 sp4_r_v_b_27 +B11[53] buffer slf_op_5 sp4_r_v_b_43 +B11[48] buffer slf_op_5 sp4_v_b_10 +B11[51] buffer slf_op_5 sp4_v_t_15 +B10[51] buffer slf_op_5 sp4_v_t_31 +B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer slf_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer slf_op_6 lc_trk_g1_6 +B12[48] buffer slf_op_6 sp12_h_r_20 +B12[47] buffer slf_op_6 sp12_h_r_4 +B12[52] buffer slf_op_6 sp12_v_b_12 +B13[46] buffer slf_op_6 sp4_h_l_1 +B13[47] buffer slf_op_6 sp4_h_l_33 +B12[46] buffer slf_op_6 sp4_h_r_28 +B13[52] buffer slf_op_6 sp4_r_v_b_13 +B12[53] buffer slf_op_6 sp4_r_v_b_29 +B13[53] buffer slf_op_6 sp4_r_v_b_45 +B13[48] buffer slf_op_6 sp4_v_b_12 +B13[51] buffer slf_op_6 sp4_v_t_17 +B12[51] buffer slf_op_6 sp4_v_t_33 +B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer slf_op_7 lc_trk_g2_7 +B14[47] buffer slf_op_7 sp12_h_l_5 +B14[48] buffer slf_op_7 sp12_h_r_22 +B14[52] buffer slf_op_7 sp12_v_b_14 +B14[46] buffer slf_op_7 sp4_h_l_19 +B15[46] buffer slf_op_7 sp4_h_l_3 +B15[47] buffer slf_op_7 sp4_h_l_35 +B15[52] buffer slf_op_7 sp4_r_v_b_15 +B14[53] buffer slf_op_7 sp4_r_v_b_31 +B15[53] buffer slf_op_7 sp4_r_v_b_47 +B14[51] buffer slf_op_7 sp4_v_b_46 +B15[51] buffer slf_op_7 sp4_v_t_19 +B15[48] buffer slf_op_7 sp4_v_t_3 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 B12[19] buffer sp12_h_l_1 sp4_h_r_13 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_l_11 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_l_11 lc_trk_g1_4 +B4[2] buffer sp12_h_l_11 sp4_h_l_7 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 -!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 -B8[2] buffer sp12_h_l_15 sp4_h_l_9 +B8[2] buffer sp12_h_l_15 sp4_h_r_20 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 -B10[2] buffer sp12_h_l_17 sp4_h_r_21 -B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 +B10[2] buffer sp12_h_l_17 sp4_h_l_8 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 -B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 -B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 -B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 -B14[19] buffer sp12_h_l_5 sp4_h_r_15 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_7 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_7 lc_trk_g1_0 +B0[2] buffer sp12_h_l_7 sp4_h_r_16 !B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 B3[1] buffer sp12_h_l_9 sp4_h_r_17 @@ -5924,12 +5999,11 @@ B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 -!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 -!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 -B4[2] buffer sp12_h_r_12 sp4_h_r_18 !B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 -B6[2] buffer sp12_h_r_14 sp4_h_l_6 +B6[2] buffer sp12_h_r_14 sp4_h_r_19 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_l_11 @@ -5937,14 +6011,16 @@ B12[2] buffer sp12_h_r_20 sp4_h_l_11 !B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 -B14[2] buffer sp12_h_r_22 sp4_h_r_23 +B14[2] buffer sp12_h_r_22 sp4_h_l_10 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_r_4 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_r_4 lc_trk_g1_4 +B15[19] buffer sp12_h_r_4 sp4_h_l_3 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 -!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 -!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 -B0[2] buffer sp12_h_r_8 sp4_h_r_16 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 @@ -5954,83 +6030,93 @@ B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_b_12 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 -!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 -B7[19] buffer sp12_v_b_13 sp4_v_t_7 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 -!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 B8[19] buffer sp12_v_b_19 sp4_v_t_8 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_b_23 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 -B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B0[19] buffer sp12_v_b_3 sp4_v_t_0 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 -B3[19] buffer sp12_v_b_5 sp4_v_b_14 -!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +B3[19] buffer sp12_v_b_5 sp4_v_t_3 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 -B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B5[19] buffer sp12_v_b_9 sp4_v_t_5 B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 -!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 -!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_b_18 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_t_6 !B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 -B9[19] buffer sp12_v_t_14 sp4_v_b_20 -!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 -B11[19] buffer sp12_v_t_18 sp4_v_t_11 -!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 -B10[19] buffer sp12_v_t_20 sp4_v_b_23 +B9[19] buffer sp12_v_t_14 sp4_v_t_9 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 -B2[19] buffer sp12_v_t_4 sp4_v_t_2 -B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 +B2[19] buffer sp12_v_t_4 sp4_v_b_15 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 -!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 -B4[19] buffer sp12_v_t_8 sp4_v_t_4 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 -!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 -!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 -B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 -B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 -B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 -B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 -B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_33 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_33 lc_trk_g3_4 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_34 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_34 lc_trk_g3_7 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_35 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_35 lc_trk_g3_6 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 @@ -6041,58 +6127,48 @@ B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 -B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 -B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 -B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 -B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_26 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_26 lc_trk_g3_2 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 -B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 -B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 -B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_r_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_r_38 lc_trk_g3_6 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 -B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 -B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 -B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 -B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 -B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 -B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 @@ -6173,46 +6249,36 @@ B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 -!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 -B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 -!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 -!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_b_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_b_15 lc_trk_g1_7 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 -!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 -!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 -!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 -B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 -B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 -B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 -B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 -B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 -B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 -B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_36 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_36 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_b_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_b_39 lc_trk_g3_7 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 -!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 -!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 @@ -6227,166 +6293,76 @@ B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 -!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_t_0 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_t_0 lc_trk_g1_5 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_t_12 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_t_12 lc_trk_g3_1 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_17 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_17 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 -B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 -!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 -B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 -B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 -B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_t_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_t_3 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 !B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 -B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_t_5 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_t_5 lc_trk_g1_0 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 -!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_t_9 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_t_9 lc_trk_g1_4 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 -!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 -!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 -!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 -!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 -!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 -!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 -B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 -B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 -B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 -B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 -B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 -B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 -B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 -B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 -B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 -B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 -B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 -B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 -B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 -B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 -B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 -B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 -B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 -B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 -B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 -B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 -B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 -B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 -B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 -B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 -B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 -B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 -B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 -B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 -B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 -B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 -B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 -B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 -B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 -B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 -B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 -B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 -B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 -B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 -B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 -B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 -B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 -B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4 -B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 -B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 -B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 -B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 -B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 -B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 -B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 -B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 -B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 -B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 -B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 -B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 -B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 -B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 -B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 -B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 -B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 -B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 -B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 -B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 -B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 -B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 -B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 -B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 -B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 -B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 -B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 -B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0 -B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 -B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 -B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 -B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 -B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 -B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 -B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 -B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 -B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 -B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 -B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 -B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 -B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 -B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 -B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 -B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 -B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 -B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 -B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 -B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 -B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 -B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 -B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 -B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 -B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 -B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 +!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer top_op_1 lc_trk_g0_1 +!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 +!B4[21],B4[22],!B4[23],B4[24],B5[21] buffer top_op_3 lc_trk_g1_3 +B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer top_op_5 lc_trk_g1_5 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],B2[24],B3[21] buffer top_op_7 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],B6[24],B7[21] buffer top_op_7 lc_trk_g1_7 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 @@ -6396,16 +6372,15 @@ B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 -B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 -!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 -B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 @@ -6425,14 +6400,12 @@ B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 -!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 !B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 -B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 !B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 @@ -6502,7 +6475,6 @@ B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 -B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 !B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 @@ -6516,7 +6488,6 @@ B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 -B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 !B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 @@ -6530,8 +6501,6 @@ B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 -!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 -B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 @@ -6545,34 +6514,28 @@ B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 -!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 -B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 -!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 -B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 -!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 -!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 !B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 -!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 -!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 !B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 @@ -6746,8 +6709,7 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ -database_ramt_5k_txt = """ -B9[7] ColBufCtrl 8k_glb_netwk_0 +database_ramb_5k_txt = """ B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 B10[7] ColBufCtrl 8k_glb_netwk_3 @@ -6756,14 +6718,7 @@ B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[0] NegClk -B5[7] RamCascade CBIT_4 -B4[7] RamCascade CBIT_5 -B7[7] RamCascade CBIT_6 -B6[7] RamCascade CBIT_7 -B1[7] RamConfig CBIT_0 -B0[7] RamConfig CBIT_1 -B3[7] RamConfig CBIT_2 -B2[7] RamConfig CBIT_3 +B1[7] RamConfig PowerUp B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 @@ -6787,7 +6742,6 @@ B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 @@ -6795,482 +6749,383 @@ B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 +!B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK -!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 -!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 -!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 -!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 -!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK -B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK -B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 -B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B12[0],B12[1],B13[0] buffer glb_netwk_1 glb2local_3 +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 -B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 -B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK -!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE -!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 -!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +B12[0],B12[1],B13[0] buffer glb_netwk_3 glb2local_3 +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 -!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 -!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK -B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE -!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 -!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 -!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 -!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 -!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK -B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE -B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 -B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE +B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 -B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 -B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK -B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE -B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 -B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 -B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 -B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 -!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK -!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 -!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 -!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 -!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE -!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 !B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 -!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 -B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 -!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 -!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 -B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 -B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 -B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 -!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 -B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 -!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 -!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 -!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK -B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 -!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 -!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 -!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 -!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE -B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 -B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 -B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 -B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 -!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 -B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 -B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 -B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 -B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 -!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 -B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK -!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 -!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 -!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 -!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 -B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE -!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 -!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 -B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 -!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 -B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 -B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 -B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 -B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 -!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 -B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 -B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 -B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 !B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 -!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 -!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6 -B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK -B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 -!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 -!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 -!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 -B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE -B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 -B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 -B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 -B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 -B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 -B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 -B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 -B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 @@ -7303,204 +7158,180 @@ B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 -B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 -B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 +B12[19] buffer sp12_h_l_1 sp4_h_r_13 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 -!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 -B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +B8[2] buffer sp12_h_l_15 sp4_h_l_9 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 -!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 -!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 -B14[2] buffer sp12_h_l_21 sp4_h_l_10 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 -B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 -B14[19] buffer sp12_h_l_5 sp4_h_l_2 -!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 -B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 -!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 -B3[1] buffer sp12_h_r_10 sp4_h_r_17 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 -B4[2] buffer sp12_h_r_12 sp4_h_l_7 -!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 -!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 -!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 -B8[2] buffer sp12_h_r_16 sp4_h_r_20 -!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 -!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 -B10[2] buffer sp12_h_r_18 sp4_h_l_8 -B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 -B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 -B12[19] buffer sp12_h_r_2 sp4_h_r_13 +B4[2] buffer sp12_h_r_12 sp4_h_r_18 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_l_6 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 -B12[2] buffer sp12_h_r_20 sp4_h_r_22 -!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 -B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +B14[2] buffer sp12_h_r_22 sp4_h_r_23 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 -B0[2] buffer sp12_h_r_8 sp4_h_l_5 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 -B1[19] buffer sp12_v_b_1 sp4_v_t_1 -!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 -B4[19] buffer sp12_v_b_11 sp4_v_b_17 -!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 -!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +B1[19] buffer sp12_v_b_1 sp4_v_b_12 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 +B7[19] buffer sp12_v_b_13 sp4_v_t_7 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 -!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 -B9[19] buffer sp12_v_b_17 sp4_v_b_20 -B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 -!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 -B11[19] buffer sp12_v_b_21 sp4_v_b_22 -!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 -B10[19] buffer sp12_v_b_23 sp4_v_t_10 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_t_8 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 +B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 -B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 -B2[19] buffer sp12_v_b_7 sp4_v_t_2 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 B5[19] buffer sp12_v_b_9 sp4_v_b_16 -B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 -B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 -B0[19] buffer sp12_v_t_0 sp4_v_b_13 -!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 -B7[19] buffer sp12_v_t_10 sp4_v_t_7 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 -B6[19] buffer sp12_v_t_12 sp4_v_b_19 -!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 -B8[19] buffer sp12_v_t_16 sp4_v_t_8 -!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 -!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 -!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 -B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 -B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +B6[19] buffer sp12_v_t_12 sp4_v_t_6 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 +B11[19] buffer sp12_v_t_18 sp4_v_t_11 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 +B10[19] buffer sp12_v_t_20 sp4_v_b_23 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 -!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 -B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 -!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 -!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 -B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 -!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 -!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 -!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 -B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 -B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 -B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 -B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 -B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 -B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 -B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 -B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 -B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 -B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 -B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 -B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 -!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 -B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 -B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 -B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 -B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 -B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 -B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 -B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 -!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 -!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 -B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 -!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 @@ -7508,7 +7339,6 @@ B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 @@ -7516,8 +7346,6 @@ B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 -B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 -B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 @@ -7587,90 +7415,86 @@ B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 -B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 -!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 -!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 -!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 -B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 -B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 -!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 -!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 -B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 -B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 -!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 -B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 -B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 -!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 -!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 -B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 -B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 -B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 -B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 -B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 -B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 -!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 -!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 @@ -7678,193 +7502,156 @@ B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 -!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 -!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 -!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 -!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 -!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 -!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 -!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 -!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 -!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 -!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 -!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 -!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 -B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 -B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 -B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 -B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 -B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 -B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 -B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 -B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 -B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 -B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 -B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 -B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 -B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 -B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 -B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 -B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 -B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 -B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 -B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 -B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 -B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 -B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 -B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 -B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 -B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 -B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 -B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 -B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 -B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 -B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 -B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 -B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 -B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 -B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 -B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 -B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 -B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 -B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 -B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 -B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 -B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 -B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 -B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 -B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 -B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 -B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 -B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 -B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13 -B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 -B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 -B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 -B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 -B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 -B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 -B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 -B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 -B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 -B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 -B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 -B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 -B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 -B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 -B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 -B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 -B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 -B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4 -B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 -B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 -B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 -B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 -B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 -B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 -B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 -B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 -B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 -B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 -B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 -B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 -B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 -B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 -B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 -B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 -B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 -B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 -B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 -B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 -B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 -B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 -B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 -B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 -B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 -B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 -B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 -B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 -B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 -B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 -!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 -!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 -!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 -!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 -!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 -!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 -B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 -B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 -B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 -B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 -B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 -B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 -!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 -B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 -B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 -!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 -B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 -B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 -B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 -B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 -B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 -B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 -B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 -B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 -B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 -!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 -!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 -B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 -B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 -B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 -!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 -!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 -B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 -!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 -B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 -B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 -!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 -B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 -!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 -!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 -B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 -B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 -B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 -!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 -B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 -B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 -B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 -!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 -B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 -!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 -!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 -B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 -!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 -B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 -B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 -!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 -!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 +B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 +B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 +B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 +B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 +B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 +B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 +B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 +B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 +B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 +B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 +B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 +B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 +B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 +B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 +B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 +B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 +B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 +B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 +B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 +B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 +B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 +B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 +B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 +B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 +B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 +B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 +B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 +B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 +B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 +B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4 +B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 +B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 +B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 +B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 +B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 +B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 +B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 +B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 +B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 +B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 +B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 +B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 +B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 +B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 +B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 +B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 +B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 +B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 +B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 +B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 +B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 +B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 +B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0 +B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 +B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 +B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 +B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 +B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 +B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 +B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 +B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 +B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 +B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 +B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 +B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 +B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 +B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 +B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 +B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 +B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 +B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 +B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 +B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 +B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 +B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 @@ -7888,6 +7675,7 @@ B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 !B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 @@ -8167,7 +7955,7 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ -database_ramb_8k_txt = """ +database_ramt_5k_txt = """ B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 @@ -8177,7 +7965,14 @@ B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[0] NegClk -B1[7] RamConfig PowerUp +B5[7] RamCascade CBIT_4 +B4[7] RamCascade CBIT_5 +B7[7] RamCascade CBIT_6 +B6[7] RamCascade CBIT_7 +B1[7] RamConfig CBIT_0 +B0[7] RamConfig CBIT_1 +B3[7] RamConfig CBIT_2 +B2[7] RamConfig CBIT_3 B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 @@ -8210,505 +8005,400 @@ B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 -!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 -!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 -!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 -!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 -!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 -!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 -!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 -!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK -!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/RE -!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 -!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 -!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 -!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 -!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK -!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/RCLKE -B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 -B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 -B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 -B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 -B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK -!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 -B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 -B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 -B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK -!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/RCLKE -!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 -!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 -!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 -!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK -B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 -!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 -!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 -!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK -B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE -B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 -B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK +B8[0],B8[1],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 -B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 -B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK -B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE -B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 -B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 -B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 -B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 -B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK -B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/RCLKE +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 -!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK -!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 -!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 -!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 -!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE -!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 -!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 -B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 -B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 -!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE -!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 -B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 -B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 -!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 -B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 -!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 -!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 -!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 -!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK -B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 -!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 -!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 -!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 -!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE -B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 -B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 -B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 -B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 -!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE -B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 -B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 -B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 -B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 -B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 -!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 -B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK -!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 -!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 -!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 -B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE -!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 -!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 -B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 -B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE -!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 -B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 -B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 -!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 -B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 -!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 -!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 -!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 -B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK -B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 -!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 -!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 -B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE -B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 -B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 -B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 -B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE -B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 -B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 -B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 -B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 -B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 -B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 @@ -8720,230 +8410,176 @@ B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 -B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 -B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 -B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 -B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 -B12[19] buffer sp12_h_l_1 sp4_h_r_13 -!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 -!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 -!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 -!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 -!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 -B8[2] buffer sp12_h_l_15 sp4_h_l_9 -!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 -!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 -B10[2] buffer sp12_h_l_17 sp4_h_r_21 -B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 -!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 -B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 -B14[19] buffer sp12_h_l_5 sp4_h_r_15 -!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 -B3[1] buffer sp12_h_l_9 sp4_h_r_17 -B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 -B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 -!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 -!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 -!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 -B4[2] buffer sp12_h_r_12 sp4_h_r_18 -!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 -B6[2] buffer sp12_h_r_14 sp4_h_l_6 -!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 -!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 -B12[2] buffer sp12_h_r_20 sp4_h_l_11 -!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 -!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 -B14[2] buffer sp12_h_r_22 sp4_h_r_23 -B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 -B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 +B3[1] buffer sp12_h_r_10 sp4_h_r_17 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +B8[2] buffer sp12_h_r_16 sp4_h_r_20 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 +B10[2] buffer sp12_h_r_18 sp4_h_l_8 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +B12[2] buffer sp12_h_r_20 sp4_h_r_22 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 -B0[2] buffer sp12_h_r_8 sp4_h_r_16 -!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 -B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 -B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B0[2] buffer sp12_h_r_8 sp4_h_l_5 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 -B1[19] buffer sp12_v_b_1 sp4_v_b_12 -!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 -!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 -B7[19] buffer sp12_v_b_13 sp4_v_t_7 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 -!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 -!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 -B8[19] buffer sp12_v_b_19 sp4_v_t_8 -!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 -!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 -B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 -B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 -B0[19] buffer sp12_v_b_3 sp4_v_b_13 -B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 -B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 +B9[19] buffer sp12_v_b_17 sp4_v_b_20 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 +B2[19] buffer sp12_v_b_7 sp4_v_t_2 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 B5[19] buffer sp12_v_b_9 sp4_v_b_16 -B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 -!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 -!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_t_7 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 -B6[19] buffer sp12_v_t_12 sp4_v_t_6 -!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 -B9[19] buffer sp12_v_t_14 sp4_v_b_20 -!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 -B11[19] buffer sp12_v_t_18 sp4_v_t_11 -!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 -B10[19] buffer sp12_v_t_20 sp4_v_b_23 -B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 -B2[19] buffer sp12_v_t_4 sp4_v_t_2 -B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 +B8[19] buffer sp12_v_t_16 sp4_v_t_8 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 -!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 -B4[19] buffer sp12_v_t_8 sp4_v_t_4 -B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 -B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 -B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 -!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 -!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 -B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 -B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 -B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 -B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 -B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 -B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 -B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 -B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 -B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 -B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 -B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 -B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 -!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 -!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 -!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 -!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 -B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 -!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 -!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 -B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 -B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 -B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 -B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 -B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 -B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 -B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 -B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 -B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 -B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 @@ -9018,52 +8654,52 @@ B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 -B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 -B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 -!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 -!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 -B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 -B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 -B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 -B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 -B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 -B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 -!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 -!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 @@ -9074,43 +8710,41 @@ B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 -!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 -B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 -B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 -!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 -!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 -B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 -!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 -B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 -!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 -!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 -!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 -!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 @@ -9120,8 +8754,6 @@ B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 -!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 @@ -9138,102 +8770,93 @@ B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 -B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 -B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 -B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 -B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 -B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 -B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 -B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 -B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 -B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 -B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 -B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 -B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 -B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 -B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 -B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 -B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 -B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 -B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 -B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 -B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 -B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 -B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 -B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 -B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 -B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 -B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 -B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 -B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 -B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 -B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 -B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 -B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 -B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 -B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 -B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 -B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 -B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 -B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 -B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 -B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 -B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 -B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4 -B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 -B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 -B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 -B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 -B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 -B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 -B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 -B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 -B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 -B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 -B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 -B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 -B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 -B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 -B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 -B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 -B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 -B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 -B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 -B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 -B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 -B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 -B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 -B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 -B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 -B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 -B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 -B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0 -B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 -B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 -B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 -B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 -B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 -B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 -B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 -B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 -B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 -B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 -B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 -B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 -B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 -B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 -B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 -B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 -B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 -B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 -B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 -B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 -B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 -B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 -B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 -B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 -B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 -B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 +B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 +B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 +B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 +B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 +B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 +B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 +B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 +B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 +B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 +B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 +B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 +B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 +B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 +B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 +B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 +B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 +B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 +B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 +B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 +B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 +B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 +B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 +B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 +B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 +B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 +B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 +B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 +B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 +B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 +B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 +B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 +B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 +B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 +B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 +B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 +B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 +B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 +B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 +B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 +B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 +B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 +B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 +B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13 +B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 +B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 +B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 +B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 +B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 +B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 +B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 +B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 +B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 +B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 +B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 +B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 +B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 +B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 +B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 +B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 +B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 +B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4 +B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 +B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 +B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 +B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 +B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 +B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 +B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 +B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 +B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 +B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 +B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 +B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 +B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 +B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 +B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 +B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 +B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 +B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 +B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 +B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 +B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 +B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 +B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 +B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 @@ -9595,7 +9218,7 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ -database_ramt_8k_txt = """ +database_ramb_8k_txt = """ B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 @@ -9605,14 +9228,7 @@ B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[0] NegClk -B5[7] RamCascade CBIT_4 -B4[7] RamCascade CBIT_5 -B7[7] RamCascade CBIT_6 -B6[7] RamCascade CBIT_7 -B1[7] RamConfig CBIT_0 -B0[7] RamConfig CBIT_1 -B3[7] RamConfig CBIT_2 -B2[7] RamConfig CBIT_3 +B1[7] RamConfig PowerUp B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 @@ -9645,6 +9261,10 @@ B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 +!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 @@ -9653,496 +9273,6979 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 -!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK -!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/WE +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/RE !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 -!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK -!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/WCLKE +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK +!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 -B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK -!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 -B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK -!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK +!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/RCLKE !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 -!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK -B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 -!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK -B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 -B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK -B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 -B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK -B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/WCLKE +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK +B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/RCLKE !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 -!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK -!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 !B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 -!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 -!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 -!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE -!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 !B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 -!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 -B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 -!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 -!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 -B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 -B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 -!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 -B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 -!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 -!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 -!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK -B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 !B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 -!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 -!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 -!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE -B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 -B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 -B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 -B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 -!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 -B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 -B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 -B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 -!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 -B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK -!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 -!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 -!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 -B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE -!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 -!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 -B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 -!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 -B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 -B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 -B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 -!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 -B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 !B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 -!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 -!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6 -B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK -B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 -!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 -!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 -B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE -B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 -B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 -B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 -B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 -B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 -B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 -B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 -B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 -B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 +B12[19] buffer sp12_h_l_1 sp4_h_r_13 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 +B8[2] buffer sp12_h_l_15 sp4_h_l_9 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +B4[2] buffer sp12_h_r_12 sp4_h_r_18 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_l_6 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 +B14[2] buffer sp12_h_r_22 sp4_h_r_23 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_b_12 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 +B7[19] buffer sp12_v_b_13 sp4_v_t_7 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_t_8 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 +B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_t_6 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 +B11[19] buffer sp12_v_t_18 sp4_v_t_11 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 +B10[19] buffer sp12_v_t_20 sp4_v_b_23 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 +B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 +B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 +B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 +B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 +B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 +B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 +B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 +B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 +B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 +B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 +B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 +B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 +B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 +B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 +B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 +B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 +B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 +B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 +B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 +B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 +B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 +B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 +B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 +B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 +B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 +B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 +B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 +B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 +B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 +B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 +B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 +B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 +B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 +B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 +B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 +B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 +B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 +B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4 +B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 +B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 +B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 +B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 +B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 +B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 +B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 +B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 +B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 +B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 +B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 +B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 +B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 +B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 +B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 +B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 +B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 +B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 +B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 +B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 +B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 +B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 +B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 +B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 +B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 +B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0 +B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 +B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 +B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 +B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 +B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 +B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 +B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 +B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 +B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 +B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 +B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 +B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 +B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 +B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 +B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 +B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 +B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 +B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 +B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 +B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 +B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 +B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 +B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 +B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 +B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 +B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 +B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_ramt_8k_txt = """ +B9[7] ColBufCtrl 8k_glb_netwk_0 +B8[7] ColBufCtrl 8k_glb_netwk_1 +B11[7] ColBufCtrl 8k_glb_netwk_2 +B10[7] ColBufCtrl 8k_glb_netwk_3 +B13[7] ColBufCtrl 8k_glb_netwk_4 +B12[7] ColBufCtrl 8k_glb_netwk_5 +B15[7] ColBufCtrl 8k_glb_netwk_6 +B14[7] ColBufCtrl 8k_glb_netwk_7 +B0[0] NegClk +B5[7] RamCascade CBIT_4 +B4[7] RamCascade CBIT_5 +B7[7] RamCascade CBIT_6 +B6[7] RamCascade CBIT_7 +B1[7] RamConfig CBIT_0 +B0[7] RamConfig CBIT_1 +B3[7] RamConfig CBIT_2 +B2[7] RamConfig CBIT_3 +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/WE +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK +!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/WCLKE +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK +!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK +B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/WCLKE +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 +!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 +!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 +!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 +!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 +!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 +!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 +!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 +!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 +!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 +!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 +B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 +B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 +B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 +B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 +B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 +B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 +B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 +B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 +B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 +B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 +B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 +B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 +!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 +!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 +!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 +!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 +!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 +!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 +!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 +!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 +!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 +!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 +!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 +B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 +B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 +B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 +B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 +B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 +B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 +B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 +B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 +B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 +B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 +B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 +!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 +!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 +!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 +!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 +!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 +!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 +!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 +!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 +!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 +!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 +!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 +B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 +B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 +B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 +B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 +B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 +B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 +B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 +B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 +B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 +B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 +!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 +!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 +!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 +!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 +!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 +!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 +!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 +!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 +!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 +!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 +!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 +B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 +B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 +B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 +B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 +B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 +B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 +B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 +B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 +B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 +B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 +B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 +B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 +B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 +B3[1] buffer sp12_h_r_10 sp4_h_r_17 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 +B8[2] buffer sp12_h_r_16 sp4_h_r_20 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 +B10[2] buffer sp12_h_r_18 sp4_h_l_8 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 +B12[2] buffer sp12_h_r_20 sp4_h_r_22 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B0[2] buffer sp12_h_r_8 sp4_h_l_5 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 +B9[19] buffer sp12_v_b_17 sp4_v_b_20 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 +B2[19] buffer sp12_v_b_7 sp4_v_t_2 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_t_7 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 +B8[19] buffer sp12_v_t_16 sp4_v_t_8 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +!B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 +!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 +!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 +B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 +B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 +B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 +B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 +B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 +B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 +B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 +B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 +B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 +B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 +B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 +B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 +B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 +B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 +B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 +B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 +B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 +B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 +B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 +B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 +B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 +B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 +B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 +B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 +B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 +B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 +B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 +B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 +B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 +B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 +B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 +B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 +B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 +B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 +B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 +B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 +B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 +B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 +B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 +B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 +B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 +B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 +B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 +B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 +B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13 +B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 +B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 +B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 +B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 +B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 +B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 +B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 +B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 +B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 +B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 +B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 +B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 +B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 +B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 +B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 +B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 +B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 +B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4 +B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 +B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 +B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 +B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 +B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 +B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 +B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 +B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 +B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 +B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 +B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 +B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 +B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 +B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 +B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 +B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 +B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 +B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 +B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 +B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 +B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 +B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 +B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 +B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 +B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 +B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 +B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 +B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 +B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_dsp0_5k_txt = """ +B0[50] Cascade MULT0_LC00_inmux02_5 +B2[50] Cascade MULT0_LC01_inmux02_5 +B4[50] Cascade MULT0_LC02_inmux02_5 +B6[50] Cascade MULT0_LC03_inmux02_5 +B8[50] Cascade MULT0_LC04_inmux02_5 +B10[50] Cascade MULT0_LC05_inmux02_5 +B12[50] Cascade MULT0_LC06_inmux02_5 +B14[50] Cascade MULT0_LC07_inmux02_5 +B9[7] ColBufCtrl 8k_glb_netwk_0 +B8[7] ColBufCtrl 8k_glb_netwk_1 +B11[7] ColBufCtrl 8k_glb_netwk_2 +B10[7] ColBufCtrl 8k_glb_netwk_3 +B13[7] ColBufCtrl 8k_glb_netwk_4 +B12[7] ColBufCtrl 8k_glb_netwk_5 +B15[7] ColBufCtrl 8k_glb_netwk_6 +B14[7] ColBufCtrl 8k_glb_netwk_7 +B1[7] IpConfig CBIT_0 +B0[7] IpConfig CBIT_1 +B3[7] IpConfig CBIT_2 +B2[7] IpConfig CBIT_3 +B5[7] IpConfig CBIT_4 +B4[7] IpConfig CBIT_5 +B7[7] IpConfig CBIT_6 +B6[7] IpConfig CBIT_7 +B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43] LC_0 +B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43] LC_1 +B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43] LC_2 +B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43] LC_3 +B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43] LC_4 +B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43] LC_5 +B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43] LC_6 +B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43] LC_7 +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_mult/lc_1/in_1 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_mult/lc_3/in_1 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 wire_mult/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_mult/lc_5/in_1 +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_mult/lc_7/in_1 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_mult/lc_0/in_1 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_mult/lc_2/in_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_mult/lc_4/in_1 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_mult/lc_6/in_1 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_mult/lc_1/in_3 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_mult/lc_3/in_3 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 wire_mult/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_mult/lc_0/in_3 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_mult/lc_2/in_3 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_mult/lc_1/in_3 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_mult/lc_3/in_3 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 wire_mult/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_mult/lc_7/in_3 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_mult/lc_7/s_r +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_mult/lc_0/in_3 +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_mult/lc_2/in_3 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_mult/lc_1/in_3 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_mult/lc_3/in_3 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 wire_mult/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_mult/lc_0/in_3 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_mult/lc_2/in_3 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_mult/lc_6/in_3 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_mult/lc_0/in_3 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_mult/lc_2/in_3 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_mult/lc_1/in_3 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_mult/lc_3/in_3 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 wire_mult/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_mult/lc_0/in_3 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_mult/lc_2/in_3 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_mult/lc_1/in_3 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_mult/lc_3/in_3 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 wire_mult/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_mult/lc_0/in_3 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_mult/lc_2/in_3 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_mult/lc_1/in_3 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_mult/lc_3/in_3 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 wire_mult/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_mult/lc_7/in_3 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_mult/lc_7/s_r +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_mult/lc_0/in_3 +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_mult/lc_2/in_3 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_mult/lc_1/in_3 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_mult/lc_3/in_3 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 wire_mult/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_mult/lc_7/in_3 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_mult/lc_1/in_3 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_mult/lc_3/in_3 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 wire_mult/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_mult/lc_0/in_3 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_mult/lc_2/in_3 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_mult/lc_6/in_3 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_mult/lc_1/in_3 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_mult/lc_3/in_3 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 wire_mult/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_mult/lc_0/in_3 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_mult/lc_2/in_3 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_mult/lc_1/in_3 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_mult/lc_3/in_3 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 wire_mult/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_mult/lc_7/in_3 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_mult/lc_7/s_r +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_mult/lc_0/in_3 +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_mult/lc_2/in_3 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_mult/lc_1/in_3 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_mult/lc_3/in_3 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 wire_mult/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_mult/lc_0/in_3 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_mult/lc_2/in_3 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_mult/lc_6/in_3 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_mult/lc_0/in_3 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_mult/lc_2/in_3 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_mult/lc_1/in_3 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_mult/lc_3/in_3 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 wire_mult/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_mult/lc_0/in_3 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_mult/lc_2/in_3 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_mult/lc_1/in_3 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_mult/lc_3/in_3 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 wire_mult/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_mult/lc_0/in_3 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_mult/lc_2/in_3 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_mult/lc_1/in_3 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_mult/lc_3/in_3 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 wire_mult/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_mult/lc_7/in_3 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_mult/lc_7/s_r +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_mult/lc_0/in_3 +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_mult/lc_2/in_3 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_mult/lc_1/in_3 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_mult/lc_3/in_3 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 wire_mult/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_mult/lc_7/in_3 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 +B12[19] buffer sp12_h_l_1 sp4_h_l_0 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 +B8[2] buffer sp12_h_l_15 sp4_h_r_20 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B10[2] buffer sp12_h_l_17 sp4_h_l_8 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_l_19 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_l_19 lc_trk_g1_4 +B12[2] buffer sp12_h_l_19 sp4_h_l_11 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_7 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_7 lc_trk_g1_0 +B0[2] buffer sp12_h_l_7 sp4_h_l_5 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_r_19 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 +B14[2] buffer sp12_h_r_22 sp4_h_l_10 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_t_8 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_t_11 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 +B2[19] buffer sp12_v_b_7 sp4_v_t_2 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_8 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_8 lc_trk_g3_0 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_b_18 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_t_6 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_t_13 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_t_13 lc_trk_g3_6 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_15 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_15 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_l_0 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_l_0 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_l_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_l_23 lc_trk_g3_2 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_l_24 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_l_24 lc_trk_g3_5 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_31 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_31 lc_trk_g3_2 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_l_32 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_l_32 lc_trk_g3_5 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_33 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_33 lc_trk_g3_4 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_35 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_35 lc_trk_g3_6 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_26 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_26 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_r_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_r_38 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_r_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_r_41 lc_trk_g3_1 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_24 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_24 lc_trk_g3_0 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_36 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_36 lc_trk_g3_4 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_b_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_b_39 lc_trk_g3_7 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_t_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_t_28 lc_trk_g3_1 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +B0[47] buffer wire_mult/mult/O_0 sp12_h_l_7 +B0[51] buffer wire_mult/mult/O_0 sp12_v_b_0 +B0[52] buffer wire_mult/mult/O_0 sp12_v_t_15 +B0[46] buffer wire_mult/mult/O_0 sp4_h_l_5 +B1[46] buffer wire_mult/mult/O_0 sp4_h_r_0 +B1[47] buffer wire_mult/mult/O_0 sp4_h_r_32 +B1[52] buffer wire_mult/mult/O_0 sp4_r_v_b_1 +B0[53] buffer wire_mult/mult/O_0 sp4_r_v_b_17 +B1[53] buffer wire_mult/mult/O_0 sp4_r_v_b_33 +B0[48] buffer wire_mult/mult/O_0 sp4_v_b_0 +B1[48] buffer wire_mult/mult/O_0 sp4_v_b_16 +B1[51] buffer wire_mult/mult/O_0 sp4_v_t_21 +B2[47] buffer wire_mult/mult/O_1 sp12_h_l_9 +B2[51] buffer wire_mult/mult/O_1 sp12_v_b_2 +B2[52] buffer wire_mult/mult/O_1 sp12_v_t_17 +B3[47] buffer wire_mult/mult/O_1 sp4_h_l_23 +B2[46] buffer wire_mult/mult/O_1 sp4_h_l_7 +B3[46] buffer wire_mult/mult/O_1 sp4_h_r_2 +B2[53] buffer wire_mult/mult/O_1 sp4_r_v_b_19 +B3[52] buffer wire_mult/mult/O_1 sp4_r_v_b_3 +B3[53] buffer wire_mult/mult/O_1 sp4_r_v_b_35 +B3[48] buffer wire_mult/mult/O_1 sp4_v_b_18 +B2[48] buffer wire_mult/mult/O_1 sp4_v_b_2 +B3[51] buffer wire_mult/mult/O_1 sp4_v_t_23 +B4[47] buffer wire_mult/mult/O_2 sp12_h_r_12 +B4[52] buffer wire_mult/mult/O_2 sp12_v_b_20 +B4[51] buffer wire_mult/mult/O_2 sp12_v_b_4 +B4[46] buffer wire_mult/mult/O_2 sp4_h_r_20 +B5[47] buffer wire_mult/mult/O_2 sp4_h_r_36 +B5[46] buffer wire_mult/mult/O_2 sp4_h_r_4 +B4[53] buffer wire_mult/mult/O_2 sp4_r_v_b_21 +B5[53] buffer wire_mult/mult/O_2 sp4_r_v_b_37 +B5[52] buffer wire_mult/mult/O_2 sp4_r_v_b_5 +B5[48] buffer wire_mult/mult/O_2 sp4_v_b_20 +B5[51] buffer wire_mult/mult/O_2 sp4_v_b_36 +B4[48] buffer wire_mult/mult/O_2 sp4_v_b_4 +B6[47] buffer wire_mult/mult/O_3 sp12_h_r_14 +B6[51] buffer wire_mult/mult/O_3 sp12_v_b_6 +B6[52] buffer wire_mult/mult/O_3 sp12_v_t_21 +B6[46] buffer wire_mult/mult/O_3 sp4_h_l_11 +B7[47] buffer wire_mult/mult/O_3 sp4_h_r_38 +B7[46] buffer wire_mult/mult/O_3 sp4_h_r_6 +B6[53] buffer wire_mult/mult/O_3 sp4_r_v_b_23 +B7[53] buffer wire_mult/mult/O_3 sp4_r_v_b_39 +B7[52] buffer wire_mult/mult/O_3 sp4_r_v_b_7 +B7[51] buffer wire_mult/mult/O_3 sp4_v_b_38 +B6[48] buffer wire_mult/mult/O_3 sp4_v_b_6 +B7[48] buffer wire_mult/mult/O_3 sp4_v_t_11 +B8[48] buffer wire_mult/mult/O_4 sp12_h_l_15 +B8[47] buffer wire_mult/mult/O_4 sp12_h_r_0 +B8[52] buffer wire_mult/mult/O_4 sp12_v_b_8 +B8[46] buffer wire_mult/mult/O_4 sp4_h_l_13 +B9[47] buffer wire_mult/mult/O_4 sp4_h_l_29 +B9[46] buffer wire_mult/mult/O_4 sp4_h_r_8 +B8[53] buffer wire_mult/mult/O_4 sp4_r_v_b_25 +B9[53] buffer wire_mult/mult/O_4 sp4_r_v_b_41 +B9[52] buffer wire_mult/mult/O_4 sp4_r_v_b_9 +B9[51] buffer wire_mult/mult/O_4 sp4_v_b_24 +B9[48] buffer wire_mult/mult/O_4 sp4_v_b_8 +B8[51] buffer wire_mult/mult/O_4 sp4_v_t_29 +B10[47] buffer wire_mult/mult/O_5 sp12_h_l_1 +B10[48] buffer wire_mult/mult/O_5 sp12_h_l_17 +B10[52] buffer wire_mult/mult/O_5 sp12_v_b_10 +B11[47] buffer wire_mult/mult/O_5 sp4_h_l_31 +B11[46] buffer wire_mult/mult/O_5 sp4_h_r_10 +B10[46] buffer wire_mult/mult/O_5 sp4_h_r_26 +B11[52] buffer wire_mult/mult/O_5 sp4_r_v_b_11 +B10[53] buffer wire_mult/mult/O_5 sp4_r_v_b_27 +B11[53] buffer wire_mult/mult/O_5 sp4_r_v_b_43 +B11[48] buffer wire_mult/mult/O_5 sp4_v_b_10 +B11[51] buffer wire_mult/mult/O_5 sp4_v_t_15 +B10[51] buffer wire_mult/mult/O_5 sp4_v_t_31 +B12[48] buffer wire_mult/mult/O_6 sp12_h_l_19 +B12[47] buffer wire_mult/mult/O_6 sp12_h_l_3 +B12[52] buffer wire_mult/mult/O_6 sp12_v_t_11 +B12[46] buffer wire_mult/mult/O_6 sp4_h_l_17 +B13[47] buffer wire_mult/mult/O_6 sp4_h_l_33 +B13[46] buffer wire_mult/mult/O_6 sp4_h_r_12 +B13[52] buffer wire_mult/mult/O_6 sp4_r_v_b_13 +B12[53] buffer wire_mult/mult/O_6 sp4_r_v_b_29 +B13[53] buffer wire_mult/mult/O_6 sp4_r_v_b_45 +B13[51] buffer wire_mult/mult/O_6 sp4_v_b_28 +B12[51] buffer wire_mult/mult/O_6 sp4_v_b_44 +B13[48] buffer wire_mult/mult/O_6 sp4_v_t_1 +B14[47] buffer wire_mult/mult/O_7 sp12_h_l_5 +B14[48] buffer wire_mult/mult/O_7 sp12_h_r_22 +B14[52] buffer wire_mult/mult/O_7 sp12_v_t_13 +B15[46] buffer wire_mult/mult/O_7 sp4_h_l_3 +B15[47] buffer wire_mult/mult/O_7 sp4_h_l_35 +B14[46] buffer wire_mult/mult/O_7 sp4_h_r_30 +B15[52] buffer wire_mult/mult/O_7 sp4_r_v_b_15 +B14[53] buffer wire_mult/mult/O_7 sp4_r_v_b_31 +B15[53] buffer wire_mult/mult/O_7 sp4_r_v_b_47 +B15[48] buffer wire_mult/mult/O_7 sp4_v_b_14 +B15[51] buffer wire_mult/mult/O_7 sp4_v_b_30 +B14[51] buffer wire_mult/mult/O_7 sp4_v_b_46 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_dsp1_5k_txt = """ +B0[50] Cascade MULT1_LC00_inmux02_5 +B2[50] Cascade MULT1_LC01_inmux02_5 +B4[50] Cascade MULT1_LC02_inmux02_5 +B6[50] Cascade MULT1_LC03_inmux02_5 +B8[50] Cascade MULT1_LC04_inmux02_5 +B10[50] Cascade MULT1_LC05_inmux02_5 +B12[50] Cascade MULT1_LC06_inmux02_5 +B14[50] Cascade MULT1_LC07_inmux02_5 +B1[7] IpConfig CBIT_0 +B0[7] IpConfig CBIT_1 +B3[7] IpConfig CBIT_2 +B2[7] IpConfig CBIT_3 +B5[7] IpConfig CBIT_4 +B7[7] IpConfig CBIT_6 +B6[7] IpConfig CBIT_7 +B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43] LC_0 +B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43] LC_1 +B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43] LC_2 +B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43] LC_3 +B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43] LC_4 +B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43] LC_5 +B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43] LC_6 +B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43] LC_7 +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_mult/lc_1/in_1 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_mult/lc_3/in_1 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_mult/lc_5/in_1 +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_mult/lc_7/in_1 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_mult/lc_0/in_1 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_mult/lc_2/in_1 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_mult/lc_4/in_1 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_mult/lc_6/in_1 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_mult/lc_1/in_3 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_mult/lc_0/in_3 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_mult/lc_2/in_3 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_mult/lc_1/in_3 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_mult/lc_7/in_3 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_mult/lc_7/s_r +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_mult/lc_0/in_3 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_mult/lc_2/in_3 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_mult/lc_1/in_3 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_mult/lc_0/in_3 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_mult/lc_2/in_3 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_mult/lc_6/in_3 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_mult/lc_7/in_3 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_mult/lc_7/s_r +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_mult/lc_7/in_3 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_mult/lc_6/in_3 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_mult/lc_7/in_3 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_mult/lc_7/s_r +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_mult/lc_6/in_3 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_mult/lc_7/in_3 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_mult/lc_7/s_r +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_mult/lc_7/in_3 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_l_11 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_l_11 lc_trk_g1_4 +B4[2] buffer sp12_h_l_11 sp4_h_l_7 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 +B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 +B8[2] buffer sp12_h_l_15 sp4_h_l_9 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_l_19 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_l_19 lc_trk_g1_4 +B12[2] buffer sp12_h_l_19 sp4_h_l_11 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_l_4 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 +B10[2] buffer sp12_h_r_18 sp4_h_r_21 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_l_0 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 +B14[2] buffer sp12_h_r_22 sp4_h_l_10 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_b_12 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_b_15 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_b_15 lc_trk_g3_7 +B6[19] buffer sp12_v_b_15 sp4_v_b_19 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_b_21 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_t_11 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 +B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_t_3 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_8 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_8 lc_trk_g3_0 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_t_7 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_t_13 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_t_13 lc_trk_g3_6 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_t_9 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_15 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_15 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_l_0 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_l_0 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_31 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_31 lc_trk_g3_2 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_l_32 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_l_32 lc_trk_g3_5 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_34 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_34 lc_trk_g3_7 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_l_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_l_4 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_26 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_26 lc_trk_g3_2 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_b_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_b_21 lc_trk_g1_5 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_24 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_24 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_b_42 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_b_42 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_t_12 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_t_12 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_17 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_17 lc_trk_g3_4 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_t_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_t_28 lc_trk_g3_1 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_t_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_t_3 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_t_35 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_t_35 lc_trk_g3_6 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_t_9 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_t_9 lc_trk_g1_4 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +B4[47] buffer wire_mult/mult/O_10 sp12_h_l_11 +B4[52] buffer wire_mult/mult/O_10 sp12_v_t_19 +B4[51] buffer wire_mult/mult/O_10 sp12_v_t_3 +B4[46] buffer wire_mult/mult/O_10 sp4_h_l_9 +B5[47] buffer wire_mult/mult/O_10 sp4_h_r_36 +B5[46] buffer wire_mult/mult/O_10 sp4_h_r_4 +B4[53] buffer wire_mult/mult/O_10 sp4_r_v_b_21 +B5[53] buffer wire_mult/mult/O_10 sp4_r_v_b_37 +B5[52] buffer wire_mult/mult/O_10 sp4_r_v_b_5 +B4[48] buffer wire_mult/mult/O_10 sp4_v_b_4 +B5[51] buffer wire_mult/mult/O_10 sp4_v_t_25 +B5[48] buffer wire_mult/mult/O_10 sp4_v_t_9 +B6[47] buffer wire_mult/mult/O_11 sp12_h_l_13 +B6[51] buffer wire_mult/mult/O_11 sp12_v_b_6 +B6[52] buffer wire_mult/mult/O_11 sp12_v_t_21 +B6[46] buffer wire_mult/mult/O_11 sp4_h_l_11 +B7[47] buffer wire_mult/mult/O_11 sp4_h_l_27 +B7[46] buffer wire_mult/mult/O_11 sp4_h_r_6 +B6[53] buffer wire_mult/mult/O_11 sp4_r_v_b_23 +B7[53] buffer wire_mult/mult/O_11 sp4_r_v_b_39 +B7[52] buffer wire_mult/mult/O_11 sp4_r_v_b_7 +B7[51] buffer wire_mult/mult/O_11 sp4_v_b_38 +B6[48] buffer wire_mult/mult/O_11 sp4_v_b_6 +B7[48] buffer wire_mult/mult/O_11 sp4_v_t_11 +B8[48] buffer wire_mult/mult/O_12 sp12_h_l_15 +B8[47] buffer wire_mult/mult/O_12 sp12_h_r_0 +B8[52] buffer wire_mult/mult/O_12 sp12_v_b_8 +B8[46] buffer wire_mult/mult/O_12 sp4_h_r_24 +B9[47] buffer wire_mult/mult/O_12 sp4_h_r_40 +B9[46] buffer wire_mult/mult/O_12 sp4_h_r_8 +B8[53] buffer wire_mult/mult/O_12 sp4_r_v_b_25 +B9[53] buffer wire_mult/mult/O_12 sp4_r_v_b_41 +B9[52] buffer wire_mult/mult/O_12 sp4_r_v_b_9 +B9[51] buffer wire_mult/mult/O_12 sp4_v_b_24 +B9[48] buffer wire_mult/mult/O_12 sp4_v_b_8 +B8[51] buffer wire_mult/mult/O_12 sp4_v_t_29 +B10[48] buffer wire_mult/mult/O_13 sp12_h_r_18 +B10[47] buffer wire_mult/mult/O_13 sp12_h_r_2 +B10[52] buffer wire_mult/mult/O_13 sp12_v_t_9 +B11[47] buffer wire_mult/mult/O_13 sp4_h_l_31 +B11[46] buffer wire_mult/mult/O_13 sp4_h_r_10 +B10[46] buffer wire_mult/mult/O_13 sp4_h_r_26 +B11[52] buffer wire_mult/mult/O_13 sp4_r_v_b_11 +B10[53] buffer wire_mult/mult/O_13 sp4_r_v_b_27 +B11[53] buffer wire_mult/mult/O_13 sp4_r_v_b_43 +B11[48] buffer wire_mult/mult/O_13 sp4_v_b_10 +B11[51] buffer wire_mult/mult/O_13 sp4_v_b_26 +B10[51] buffer wire_mult/mult/O_13 sp4_v_b_42 +B12[48] buffer wire_mult/mult/O_14 sp12_h_l_19 +B12[47] buffer wire_mult/mult/O_14 sp12_h_l_3 +B12[52] buffer wire_mult/mult/O_14 sp12_v_b_12 +B12[46] buffer wire_mult/mult/O_14 sp4_h_l_17 +B13[46] buffer wire_mult/mult/O_14 sp4_h_r_12 +B13[47] buffer wire_mult/mult/O_14 sp4_h_r_44 +B13[52] buffer wire_mult/mult/O_14 sp4_r_v_b_13 +B12[53] buffer wire_mult/mult/O_14 sp4_r_v_b_29 +B13[53] buffer wire_mult/mult/O_14 sp4_r_v_b_45 +B13[48] buffer wire_mult/mult/O_14 sp4_v_b_12 +B13[51] buffer wire_mult/mult/O_14 sp4_v_t_17 +B12[51] buffer wire_mult/mult/O_14 sp4_v_t_33 +B14[47] buffer wire_mult/mult/O_15 sp12_h_l_5 +B14[48] buffer wire_mult/mult/O_15 sp12_h_r_22 +B14[52] buffer wire_mult/mult/O_15 sp12_v_t_13 +B15[46] buffer wire_mult/mult/O_15 sp4_h_l_3 +B14[46] buffer wire_mult/mult/O_15 sp4_h_r_30 +B15[47] buffer wire_mult/mult/O_15 sp4_h_r_46 +B15[52] buffer wire_mult/mult/O_15 sp4_r_v_b_15 +B14[53] buffer wire_mult/mult/O_15 sp4_r_v_b_31 +B15[53] buffer wire_mult/mult/O_15 sp4_r_v_b_47 +B15[51] buffer wire_mult/mult/O_15 sp4_v_b_30 +B15[48] buffer wire_mult/mult/O_15 sp4_v_t_3 +B14[51] buffer wire_mult/mult/O_15 sp4_v_t_35 +B0[47] buffer wire_mult/mult/O_8 sp12_h_r_8 +B0[51] buffer wire_mult/mult/O_8 sp12_v_b_0 +B0[52] buffer wire_mult/mult/O_8 sp12_v_t_15 +B1[47] buffer wire_mult/mult/O_8 sp4_h_l_21 +B1[46] buffer wire_mult/mult/O_8 sp4_h_r_0 +B0[46] buffer wire_mult/mult/O_8 sp4_h_r_16 +B1[52] buffer wire_mult/mult/O_8 sp4_r_v_b_1 +B0[53] buffer wire_mult/mult/O_8 sp4_r_v_b_17 +B1[53] buffer wire_mult/mult/O_8 sp4_r_v_b_33 +B0[48] buffer wire_mult/mult/O_8 sp4_v_b_0 +B1[48] buffer wire_mult/mult/O_8 sp4_v_b_16 +B1[51] buffer wire_mult/mult/O_8 sp4_v_t_21 +B2[47] buffer wire_mult/mult/O_9 sp12_h_l_9 +B2[51] buffer wire_mult/mult/O_9 sp12_v_b_2 +B2[52] buffer wire_mult/mult/O_9 sp12_v_t_17 +B2[46] buffer wire_mult/mult/O_9 sp4_h_l_7 +B3[46] buffer wire_mult/mult/O_9 sp4_h_r_2 +B3[47] buffer wire_mult/mult/O_9 sp4_h_r_34 +B2[53] buffer wire_mult/mult/O_9 sp4_r_v_b_19 +B3[52] buffer wire_mult/mult/O_9 sp4_r_v_b_3 +B3[53] buffer wire_mult/mult/O_9 sp4_r_v_b_35 +B2[48] buffer wire_mult/mult/O_9 sp4_v_b_2 +B3[51] buffer wire_mult/mult/O_9 sp4_v_t_23 +B3[48] buffer wire_mult/mult/O_9 sp4_v_t_7 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_dsp2_5k_txt = """ +B0[50] Cascade MULT2_LC00_inmux02_5 +B2[50] Cascade MULT2_LC01_inmux02_5 +B4[50] Cascade MULT2_LC02_inmux02_5 +B6[50] Cascade MULT2_LC03_inmux02_5 +B8[50] Cascade MULT2_LC04_inmux02_5 +B10[50] Cascade MULT2_LC05_inmux02_5 +B12[50] Cascade MULT2_LC06_inmux02_5 +B14[50] Cascade MULT2_LC07_inmux02_5 +B1[7] IpConfig CBIT_0 +B0[7] IpConfig CBIT_1 +B3[7] IpConfig CBIT_2 +B2[7] IpConfig CBIT_3 +B5[7] IpConfig CBIT_4 +B4[7] IpConfig CBIT_5 +B7[7] IpConfig CBIT_6 +B6[7] IpConfig CBIT_7 +B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43] LC_0 +B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43] LC_1 +B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43] LC_2 +B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43] LC_3 +B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43] LC_4 +B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43] LC_5 +B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43] LC_6 +B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43] LC_7 +B0[0] NegClk +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_mult/lc_7/clk +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_mult/lc_7/clk +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_mult/lc_7/clk +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_mult/lc_7/clk +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_mult/lc_7/clk +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_mult/lc_7/clk +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_mult/lc_7/clk +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_mult/lc_7/clk +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_mult/lc_1/in_1 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_mult/lc_3/in_1 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_mult/lc_5/in_1 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_mult/lc_7/clk +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_mult/lc_7/in_1 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_mult/lc_0/in_1 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_mult/lc_2/in_1 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_mult/lc_4/in_1 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_mult/lc_6/in_1 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_mult/lc_1/in_3 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_mult/lc_5/in_3 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_mult/lc_7/cen +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_mult/lc_0/in_3 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_mult/lc_2/in_3 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_mult/lc_1/in_3 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_mult/lc_7/in_3 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_mult/lc_7/s_r +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_mult/lc_0/in_3 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_mult/lc_2/in_3 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_mult/lc_1/in_3 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_mult/lc_0/in_3 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_mult/lc_2/in_3 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_mult/lc_6/in_3 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_mult/lc_5/in_3 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_mult/lc_7/clk +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_mult/lc_5/in_3 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_mult/lc_7/cen +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_mult/lc_7/in_3 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_mult/lc_7/s_r +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_mult/lc_0/in_3 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_mult/lc_2/in_3 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_mult/lc_1/in_3 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_mult/lc_7/in_3 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_mult/lc_5/in_3 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_mult/lc_7/clk +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_mult/lc_6/in_3 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_mult/lc_5/in_3 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_mult/lc_7/cen +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_mult/lc_7/in_3 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_mult/lc_7/s_r +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_mult/lc_1/in_3 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_mult/lc_0/in_3 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_mult/lc_2/in_3 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_mult/lc_6/in_3 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_mult/lc_5/in_3 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_mult/lc_7/clk +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_mult/lc_5/in_3 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_mult/lc_7/cen +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_mult/lc_7/in_3 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_mult/lc_7/s_r +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_mult/lc_0/in_3 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_mult/lc_2/in_3 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_mult/lc_1/in_3 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_mult/lc_7/in_3 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_l_11 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_l_11 lc_trk_g1_4 +B4[2] buffer sp12_h_l_11 sp4_h_r_18 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 +B6[2] buffer sp12_h_l_13 sp4_h_l_6 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 +B14[2] buffer sp12_h_l_21 sp4_h_r_23 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_l_8 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_l_8 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_r_15 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_r_15 lc_trk_g1_7 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 +B8[2] buffer sp12_h_r_16 sp4_h_l_9 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 +B10[2] buffer sp12_h_r_18 sp4_h_r_21 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_r_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_r_19 lc_trk_g1_3 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_l_0 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 +B12[2] buffer sp12_h_r_20 sp4_h_r_22 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_r_4 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_r_4 lc_trk_g1_4 +B15[19] buffer sp12_h_r_4 sp4_h_l_3 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_r_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_r_6 lc_trk_g1_6 +B14[19] buffer sp12_h_r_6 sp4_h_r_15 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 +B7[19] buffer sp12_v_b_13 sp4_v_b_18 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_b_23 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 +B0[19] buffer sp12_v_b_3 sp4_v_t_0 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_8 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_8 lc_trk_g3_0 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 +B8[19] buffer sp12_v_t_16 sp4_v_t_8 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 +B11[19] buffer sp12_v_t_18 sp4_v_t_11 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_l_0 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_l_0 lc_trk_g1_5 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_l_12 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_l_12 lc_trk_g3_1 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_l_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_l_23 lc_trk_g3_2 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_l_24 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_l_24 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_33 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_33 lc_trk_g3_4 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_34 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_34 lc_trk_g3_7 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_36 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_36 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_t_0 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_t_0 lc_trk_g1_5 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_t_16 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_t_16 lc_trk_g3_5 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_17 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_17 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_t_35 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_t_35 lc_trk_g3_6 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +B0[47] buffer wire_mult/mult/O_16 sp12_h_r_8 +B0[51] buffer wire_mult/mult/O_16 sp12_v_b_0 +B0[52] buffer wire_mult/mult/O_16 sp12_v_b_16 +B1[46] buffer wire_mult/mult/O_16 sp4_h_r_0 +B0[46] buffer wire_mult/mult/O_16 sp4_h_r_16 +B1[47] buffer wire_mult/mult/O_16 sp4_h_r_32 +B1[52] buffer wire_mult/mult/O_16 sp4_r_v_b_1 +B0[53] buffer wire_mult/mult/O_16 sp4_r_v_b_17 +B1[53] buffer wire_mult/mult/O_16 sp4_r_v_b_33 +B0[48] buffer wire_mult/mult/O_16 sp4_v_b_0 +B1[48] buffer wire_mult/mult/O_16 sp4_v_b_16 +B1[51] buffer wire_mult/mult/O_16 sp4_v_b_32 +B2[47] buffer wire_mult/mult/O_17 sp12_h_l_9 +B2[52] buffer wire_mult/mult/O_17 sp12_v_b_18 +B2[51] buffer wire_mult/mult/O_17 sp12_v_b_2 +B3[47] buffer wire_mult/mult/O_17 sp4_h_l_23 +B2[46] buffer wire_mult/mult/O_17 sp4_h_r_18 +B3[46] buffer wire_mult/mult/O_17 sp4_h_r_2 +B2[53] buffer wire_mult/mult/O_17 sp4_r_v_b_19 +B3[52] buffer wire_mult/mult/O_17 sp4_r_v_b_3 +B3[53] buffer wire_mult/mult/O_17 sp4_r_v_b_35 +B3[48] buffer wire_mult/mult/O_17 sp4_v_b_18 +B2[48] buffer wire_mult/mult/O_17 sp4_v_b_2 +B3[51] buffer wire_mult/mult/O_17 sp4_v_t_23 +B4[47] buffer wire_mult/mult/O_18 sp12_h_l_11 +B4[52] buffer wire_mult/mult/O_18 sp12_v_t_19 +B4[51] buffer wire_mult/mult/O_18 sp12_v_t_3 +B4[46] buffer wire_mult/mult/O_18 sp4_h_l_9 +B5[47] buffer wire_mult/mult/O_18 sp4_h_r_36 +B5[46] buffer wire_mult/mult/O_18 sp4_h_r_4 +B4[53] buffer wire_mult/mult/O_18 sp4_r_v_b_21 +B5[53] buffer wire_mult/mult/O_18 sp4_r_v_b_37 +B5[52] buffer wire_mult/mult/O_18 sp4_r_v_b_5 +B5[48] buffer wire_mult/mult/O_18 sp4_v_b_20 +B5[51] buffer wire_mult/mult/O_18 sp4_v_b_36 +B4[48] buffer wire_mult/mult/O_18 sp4_v_b_4 +B6[47] buffer wire_mult/mult/O_19 sp12_h_l_13 +B6[52] buffer wire_mult/mult/O_19 sp12_v_b_22 +B6[51] buffer wire_mult/mult/O_19 sp12_v_t_5 +B7[47] buffer wire_mult/mult/O_19 sp4_h_l_27 +B6[46] buffer wire_mult/mult/O_19 sp4_h_r_22 +B7[46] buffer wire_mult/mult/O_19 sp4_h_r_6 +B6[53] buffer wire_mult/mult/O_19 sp4_r_v_b_23 +B7[53] buffer wire_mult/mult/O_19 sp4_r_v_b_39 +B7[52] buffer wire_mult/mult/O_19 sp4_r_v_b_7 +B7[51] buffer wire_mult/mult/O_19 sp4_v_b_38 +B6[48] buffer wire_mult/mult/O_19 sp4_v_b_6 +B7[48] buffer wire_mult/mult/O_19 sp4_v_t_11 +B8[47] buffer wire_mult/mult/O_20 sp12_h_r_0 +B8[48] buffer wire_mult/mult/O_20 sp12_h_r_16 +B8[52] buffer wire_mult/mult/O_20 sp12_v_b_8 +B8[46] buffer wire_mult/mult/O_20 sp4_h_l_13 +B9[47] buffer wire_mult/mult/O_20 sp4_h_r_40 +B9[46] buffer wire_mult/mult/O_20 sp4_h_r_8 +B8[53] buffer wire_mult/mult/O_20 sp4_r_v_b_25 +B9[53] buffer wire_mult/mult/O_20 sp4_r_v_b_41 +B9[52] buffer wire_mult/mult/O_20 sp4_r_v_b_9 +B9[48] buffer wire_mult/mult/O_20 sp4_v_b_8 +B9[51] buffer wire_mult/mult/O_20 sp4_v_t_13 +B8[51] buffer wire_mult/mult/O_20 sp4_v_t_29 +B10[48] buffer wire_mult/mult/O_21 sp12_h_r_18 +B10[47] buffer wire_mult/mult/O_21 sp12_h_r_2 +B10[52] buffer wire_mult/mult/O_21 sp12_v_t_9 +B10[46] buffer wire_mult/mult/O_21 sp4_h_l_15 +B11[46] buffer wire_mult/mult/O_21 sp4_h_r_10 +B11[47] buffer wire_mult/mult/O_21 sp4_h_r_42 +B11[52] buffer wire_mult/mult/O_21 sp4_r_v_b_11 +B10[53] buffer wire_mult/mult/O_21 sp4_r_v_b_27 +B11[53] buffer wire_mult/mult/O_21 sp4_r_v_b_43 +B11[48] buffer wire_mult/mult/O_21 sp4_v_b_10 +B11[51] buffer wire_mult/mult/O_21 sp4_v_t_15 +B10[51] buffer wire_mult/mult/O_21 sp4_v_t_31 +B12[48] buffer wire_mult/mult/O_22 sp12_h_r_20 +B12[47] buffer wire_mult/mult/O_22 sp12_h_r_4 +B12[52] buffer wire_mult/mult/O_22 sp12_v_b_12 +B12[46] buffer wire_mult/mult/O_22 sp4_h_l_17 +B13[47] buffer wire_mult/mult/O_22 sp4_h_l_33 +B13[46] buffer wire_mult/mult/O_22 sp4_h_r_12 +B13[52] buffer wire_mult/mult/O_22 sp4_r_v_b_13 +B12[53] buffer wire_mult/mult/O_22 sp4_r_v_b_29 +B13[53] buffer wire_mult/mult/O_22 sp4_r_v_b_45 +B13[48] buffer wire_mult/mult/O_22 sp4_v_t_1 +B13[51] buffer wire_mult/mult/O_22 sp4_v_t_17 +B12[51] buffer wire_mult/mult/O_22 sp4_v_t_33 +B14[48] buffer wire_mult/mult/O_23 sp12_h_l_21 +B14[47] buffer wire_mult/mult/O_23 sp12_h_r_6 +B14[52] buffer wire_mult/mult/O_23 sp12_v_b_14 +B15[46] buffer wire_mult/mult/O_23 sp4_h_l_3 +B14[46] buffer wire_mult/mult/O_23 sp4_h_r_30 +B15[47] buffer wire_mult/mult/O_23 sp4_h_r_46 +B15[52] buffer wire_mult/mult/O_23 sp4_r_v_b_15 +B14[53] buffer wire_mult/mult/O_23 sp4_r_v_b_31 +B15[53] buffer wire_mult/mult/O_23 sp4_r_v_b_47 +B15[48] buffer wire_mult/mult/O_23 sp4_v_b_14 +B15[51] buffer wire_mult/mult/O_23 sp4_v_t_19 +B14[51] buffer wire_mult/mult/O_23 sp4_v_t_35 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_dsp3_5k_txt = """ +B0[50] Cascade MULT3_LC00_inmux02_5 +B2[50] Cascade MULT3_LC01_inmux02_5 +B4[50] Cascade MULT3_LC02_inmux02_5 +B6[50] Cascade MULT3_LC03_inmux02_5 +B8[50] Cascade MULT3_LC04_inmux02_5 +B10[50] Cascade MULT3_LC05_inmux02_5 +B12[50] Cascade MULT3_LC06_inmux02_5 +B14[50] Cascade MULT3_LC07_inmux02_5 +B9[7] ColBufCtrl 8k_glb_netwk_0 +B8[7] ColBufCtrl 8k_glb_netwk_1 +B11[7] ColBufCtrl 8k_glb_netwk_2 +B10[7] ColBufCtrl 8k_glb_netwk_3 +B13[7] ColBufCtrl 8k_glb_netwk_4 +B12[7] ColBufCtrl 8k_glb_netwk_5 +B15[7] ColBufCtrl 8k_glb_netwk_6 +B14[7] ColBufCtrl 8k_glb_netwk_7 +B1[7] IpConfig CBIT_0 +B0[36],B0[37],B0[42],B0[43],B1[36],B1[37],B1[42],B1[43] LC_0 +B2[36],B2[37],B2[42],B2[43],B3[36],B3[37],B3[42],B3[43] LC_1 +B4[36],B4[37],B4[42],B4[43],B5[36],B5[37],B5[42],B5[43] LC_2 +B6[36],B6[37],B6[42],B6[43],B7[36],B7[37],B7[42],B7[43] LC_3 +B8[36],B8[37],B8[42],B8[43],B9[36],B9[37],B9[42],B9[43] LC_4 +B10[36],B10[37],B10[42],B10[43],B11[36],B11[37],B11[42],B11[43] LC_5 +B12[36],B12[37],B12[42],B12[43],B13[36],B13[37],B13[42],B13[43] LC_6 +B14[36],B14[37],B14[42],B14[43],B15[36],B15[37],B15[42],B15[43] LC_7 +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_mult/lc_7/s_r +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_mult/lc_7/s_r +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_mult/lc_1/in_1 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_mult/lc_3/in_1 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_mult/lc_5/in_1 +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_mult/lc_7/in_1 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_mult/lc_0/in_1 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_mult/lc_2/in_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_mult/lc_4/in_1 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_mult/lc_6/in_1 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_mult/lc_1/in_3 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_mult/lc_0/in_3 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_mult/lc_2/in_3 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_mult/lc_1/in_3 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_mult/lc_7/in_3 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_mult/lc_7/s_r +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_mult/lc_0/in_3 +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_mult/lc_2/in_3 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_mult/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_mult/lc_1/in_3 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 wire_mult/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_mult/lc_3/in_3 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_mult/lc_5/in_3 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_mult/lc_7/in_3 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_mult/lc_0/in_3 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 wire_mult/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_mult/lc_2/in_3 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 wire_mult/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_mult/lc_4/in_3 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_mult/lc_6/in_3 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_mult/lc_0/in_3 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_mult/lc_2/in_3 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_mult/lc_1/in_3 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_mult/lc_0/in_3 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_mult/lc_2/in_3 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_mult/lc_1/in_3 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_mult/lc_7/in_3 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_mult/lc_0/in_3 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_mult/lc_2/in_3 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_mult/lc_1/in_3 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_mult/lc_7/in_3 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_mult/lc_7/s_r +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_mult/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_mult/lc_0/in_3 +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 wire_mult/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_mult/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_mult/lc_2/in_3 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 wire_mult/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_mult/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_mult/lc_4/in_3 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_mult/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_mult/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_mult/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_mult/lc_1/in_3 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 wire_mult/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_mult/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_mult/lc_3/in_3 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_mult/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_mult/lc_5/in_3 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_mult/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_mult/lc_7/in_3 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_mult/lc_1/in_3 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_mult/lc_0/in_3 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_mult/lc_2/in_3 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_mult/lc_6/in_3 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_mult/lc_1/in_3 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_mult/lc_0/in_3 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_mult/lc_2/in_3 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_mult/lc_6/in_3 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_mult/lc_1/in_3 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_mult/lc_7/in_3 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_mult/lc_7/s_r +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_mult/lc_0/in_3 +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_mult/lc_2/in_3 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_mult/lc_6/in_3 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_mult/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_mult/lc_1/in_3 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 wire_mult/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_mult/lc_3/in_3 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_mult/lc_5/in_3 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_mult/lc_7/in_3 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_mult/lc_0/in_3 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 wire_mult/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_mult/lc_2/in_3 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 wire_mult/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_mult/lc_4/in_3 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_mult/lc_6/in_3 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_mult/lc_0/in_3 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_mult/lc_2/in_3 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_mult/lc_6/in_3 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_mult/lc_1/in_3 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_mult/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_mult/lc_0/in_3 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_mult/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_mult/lc_2/in_3 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_mult/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_mult/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_mult/lc_6/in_3 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_mult/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_mult/lc_1/in_3 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_mult/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_mult/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_mult/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_mult/lc_7/in_3 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_mult/lc_0/in_3 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_mult/lc_2/in_3 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_mult/lc_6/in_3 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_mult/lc_1/in_3 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_mult/lc_7/in_3 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_mult/lc_7/s_r +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_mult/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_mult/lc_0/in_3 +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 wire_mult/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_mult/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_mult/lc_2/in_3 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 wire_mult/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_mult/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_mult/lc_4/in_3 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_mult/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_mult/lc_6/in_3 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_mult/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_mult/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_mult/lc_1/in_3 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 wire_mult/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_mult/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_mult/lc_3/in_3 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_mult/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_mult/lc_5/in_3 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_mult/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_mult/lc_7/in_3 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 -B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 @@ -10155,7 +16258,6 @@ B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 -B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 @@ -10167,160 +16269,156 @@ B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 -!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 -!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 -B6[2] buffer sp12_h_l_13 sp4_h_r_19 -!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 -!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 -!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 -B14[2] buffer sp12_h_l_21 sp4_h_l_10 -B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 -B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 -B15[19] buffer sp12_h_l_3 sp4_h_l_3 -B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_l_11 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_l_11 lc_trk_g1_4 +B4[2] buffer sp12_h_l_11 sp4_h_l_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 -B14[19] buffer sp12_h_l_5 sp4_h_l_2 -!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_l_8 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_l_8 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_r_12 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 -!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 -B3[1] buffer sp12_h_r_10 sp4_h_r_17 -!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 -!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 -!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 -B4[2] buffer sp12_h_r_12 sp4_h_l_7 -!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_l_6 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_r_15 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_r_15 lc_trk_g1_7 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 B8[2] buffer sp12_h_r_16 sp4_h_r_20 -!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 -!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 -B10[2] buffer sp12_h_r_18 sp4_h_l_8 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_r_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_r_19 lc_trk_g1_3 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 -B12[19] buffer sp12_h_r_2 sp4_h_r_13 +B12[19] buffer sp12_h_r_2 sp4_h_l_0 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 -B12[2] buffer sp12_h_r_20 sp4_h_r_22 -!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 +B14[2] buffer sp12_h_r_22 sp4_h_r_23 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_r_4 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_r_4 lc_trk_g1_4 +B15[19] buffer sp12_h_r_4 sp4_h_l_3 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_l_5 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_t_1 -!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 -B4[19] buffer sp12_v_b_11 sp4_v_b_17 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 !B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 -!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 -B9[19] buffer sp12_v_b_17 sp4_v_b_20 -B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 B11[19] buffer sp12_v_b_21 sp4_v_b_22 -!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 -B10[19] buffer sp12_v_b_23 sp4_v_t_10 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 -B2[19] buffer sp12_v_b_7 sp4_v_t_2 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 -B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B5[19] buffer sp12_v_b_9 sp4_v_t_5 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 -B0[19] buffer sp12_v_t_0 sp4_v_b_13 +B0[19] buffer sp12_v_t_0 sp4_v_t_0 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 !B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 -B7[19] buffer sp12_v_t_10 sp4_v_t_7 +B7[19] buffer sp12_v_t_10 sp4_v_b_18 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_t_13 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_t_13 lc_trk_g3_6 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 B8[19] buffer sp12_v_t_16 sp4_v_t_8 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 -!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 -!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 +B10[19] buffer sp12_v_t_20 sp4_v_t_10 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 +B2[19] buffer sp12_v_t_4 sp4_v_b_15 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 +B4[19] buffer sp12_v_t_8 sp4_v_b_17 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 -B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_l_0 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_l_0 lc_trk_g1_5 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 -B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 -B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 -B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 -B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 -B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 -B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 -B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 -B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 -B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_l_24 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_l_24 lc_trk_g3_5 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_25 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_25 lc_trk_g3_4 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_33 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_33 lc_trk_g3_4 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 -B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 @@ -10331,40 +16429,44 @@ B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 -B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 -B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 -B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 -B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 -B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 -B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 -B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_r_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_r_41 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 -B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 -B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 @@ -10449,14 +16551,14 @@ B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 -!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 -!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 -!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_b_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_b_15 lc_trk_g1_7 B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 @@ -10465,36 +16567,34 @@ B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 !B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 -!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 -!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 -B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 -!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 -B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_b_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_b_39 lc_trk_g3_7 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 -!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 -!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 -B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 -!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 @@ -10505,36 +16605,38 @@ B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_t_0 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_t_0 lc_trk_g1_5 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_t_12 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_t_12 lc_trk_g3_1 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 -B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 -B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 -B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 -B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 -B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 -B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_t_16 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_t_16 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 -B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 -!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 -!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 -!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_t_32 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_t_32 lc_trk_g3_5 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_t_5 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_t_5 lc_trk_g1_0 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 @@ -10569,110 +16671,102 @@ B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 -!B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 -!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 -!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 -!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 -!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 -!B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 -!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 -!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 -B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 -B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 -B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 -B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 -B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 -B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 -B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 -B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 -B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 -B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 -B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 -B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 -B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 -B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 -B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 -B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 -B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 -B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 -B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 -B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 -B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 -B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 -B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 -B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 -B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 -B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 -B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 -B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 -B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 -B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 -B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 -B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 -B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 -B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 -B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 -B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 -B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 -B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 -B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 -B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 -B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 -B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 -B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 -B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 -B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 -B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 -B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 -B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13 -B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 -B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 -B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 -B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 -B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 -B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 -B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 -B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 -B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 -B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 -B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 -B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 -B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 -B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 -B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 -B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 -B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 -B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4 -B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 -B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 -B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 -B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 -B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 -B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 -B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 -B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 -B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 -B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 -B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 -B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 -B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 -B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 -B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 -B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 -B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 -B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 -B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 -B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 -B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 -B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 -B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 -B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 -B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 -B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 -B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 -B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 -B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 -B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 +B0[47] buffer wire_mult/mult/O_24 sp12_h_r_8 +B0[51] buffer wire_mult/mult/O_24 sp12_v_b_0 +B0[52] buffer wire_mult/mult/O_24 sp12_v_b_16 +B0[46] buffer wire_mult/mult/O_24 sp4_h_l_5 +B1[46] buffer wire_mult/mult/O_24 sp4_h_r_0 +B1[47] buffer wire_mult/mult/O_24 sp4_h_r_32 +B1[52] buffer wire_mult/mult/O_24 sp4_r_v_b_1 +B0[53] buffer wire_mult/mult/O_24 sp4_r_v_b_17 +B1[53] buffer wire_mult/mult/O_24 sp4_r_v_b_33 +B0[48] buffer wire_mult/mult/O_24 sp4_v_b_0 +B1[51] buffer wire_mult/mult/O_24 sp4_v_b_32 +B1[48] buffer wire_mult/mult/O_24 sp4_v_t_5 +B2[47] buffer wire_mult/mult/O_25 sp12_h_l_9 +B2[51] buffer wire_mult/mult/O_25 sp12_v_t_1 +B2[52] buffer wire_mult/mult/O_25 sp12_v_t_17 +B2[46] buffer wire_mult/mult/O_25 sp4_h_l_7 +B3[46] buffer wire_mult/mult/O_25 sp4_h_r_2 +B3[47] buffer wire_mult/mult/O_25 sp4_h_r_34 +B2[53] buffer wire_mult/mult/O_25 sp4_r_v_b_19 +B3[52] buffer wire_mult/mult/O_25 sp4_r_v_b_3 +B3[53] buffer wire_mult/mult/O_25 sp4_r_v_b_35 +B3[48] buffer wire_mult/mult/O_25 sp4_v_b_18 +B2[48] buffer wire_mult/mult/O_25 sp4_v_b_2 +B3[51] buffer wire_mult/mult/O_25 sp4_v_t_23 +B4[47] buffer wire_mult/mult/O_26 sp12_h_l_11 +B4[52] buffer wire_mult/mult/O_26 sp12_v_b_20 +B4[51] buffer wire_mult/mult/O_26 sp12_v_t_3 +B5[47] buffer wire_mult/mult/O_26 sp4_h_l_25 +B4[46] buffer wire_mult/mult/O_26 sp4_h_r_20 +B5[46] buffer wire_mult/mult/O_26 sp4_h_r_4 +B4[53] buffer wire_mult/mult/O_26 sp4_r_v_b_21 +B5[53] buffer wire_mult/mult/O_26 sp4_r_v_b_37 +B5[52] buffer wire_mult/mult/O_26 sp4_r_v_b_5 +B5[48] buffer wire_mult/mult/O_26 sp4_v_b_20 +B4[48] buffer wire_mult/mult/O_26 sp4_v_b_4 +B5[51] buffer wire_mult/mult/O_26 sp4_v_t_25 +B6[47] buffer wire_mult/mult/O_27 sp12_h_r_14 +B6[52] buffer wire_mult/mult/O_27 sp12_v_b_22 +B6[51] buffer wire_mult/mult/O_27 sp12_v_b_6 +B6[46] buffer wire_mult/mult/O_27 sp4_h_l_11 +B7[47] buffer wire_mult/mult/O_27 sp4_h_l_27 +B7[46] buffer wire_mult/mult/O_27 sp4_h_r_6 +B6[53] buffer wire_mult/mult/O_27 sp4_r_v_b_23 +B7[53] buffer wire_mult/mult/O_27 sp4_r_v_b_39 +B7[52] buffer wire_mult/mult/O_27 sp4_r_v_b_7 +B7[48] buffer wire_mult/mult/O_27 sp4_v_b_22 +B6[48] buffer wire_mult/mult/O_27 sp4_v_b_6 +B7[51] buffer wire_mult/mult/O_27 sp4_v_t_27 +B8[47] buffer wire_mult/mult/O_28 sp12_h_r_0 +B8[48] buffer wire_mult/mult/O_28 sp12_h_r_16 +B8[52] buffer wire_mult/mult/O_28 sp12_v_t_7 +B8[46] buffer wire_mult/mult/O_28 sp4_h_l_13 +B9[47] buffer wire_mult/mult/O_28 sp4_h_r_40 +B9[46] buffer wire_mult/mult/O_28 sp4_h_r_8 +B8[53] buffer wire_mult/mult/O_28 sp4_r_v_b_25 +B9[53] buffer wire_mult/mult/O_28 sp4_r_v_b_41 +B9[52] buffer wire_mult/mult/O_28 sp4_r_v_b_9 +B9[48] buffer wire_mult/mult/O_28 sp4_v_b_8 +B9[51] buffer wire_mult/mult/O_28 sp4_v_t_13 +B8[51] buffer wire_mult/mult/O_28 sp4_v_t_29 +B10[48] buffer wire_mult/mult/O_29 sp12_h_l_17 +B10[47] buffer wire_mult/mult/O_29 sp12_h_r_2 +B10[52] buffer wire_mult/mult/O_29 sp12_v_t_9 +B10[46] buffer wire_mult/mult/O_29 sp4_h_l_15 +B11[46] buffer wire_mult/mult/O_29 sp4_h_r_10 +B11[47] buffer wire_mult/mult/O_29 sp4_h_r_42 +B11[52] buffer wire_mult/mult/O_29 sp4_r_v_b_11 +B10[53] buffer wire_mult/mult/O_29 sp4_r_v_b_27 +B11[53] buffer wire_mult/mult/O_29 sp4_r_v_b_43 +B11[48] buffer wire_mult/mult/O_29 sp4_v_b_10 +B11[51] buffer wire_mult/mult/O_29 sp4_v_b_26 +B10[51] buffer wire_mult/mult/O_29 sp4_v_t_31 +B12[48] buffer wire_mult/mult/O_30 sp12_h_r_20 +B12[47] buffer wire_mult/mult/O_30 sp12_h_r_4 +B12[52] buffer wire_mult/mult/O_30 sp12_v_b_12 +B12[46] buffer wire_mult/mult/O_30 sp4_h_l_17 +B13[47] buffer wire_mult/mult/O_30 sp4_h_l_33 +B13[46] buffer wire_mult/mult/O_30 sp4_h_r_12 +B13[52] buffer wire_mult/mult/O_30 sp4_r_v_b_13 +B12[53] buffer wire_mult/mult/O_30 sp4_r_v_b_29 +B13[53] buffer wire_mult/mult/O_30 sp4_r_v_b_45 +B13[51] buffer wire_mult/mult/O_30 sp4_v_b_28 +B12[51] buffer wire_mult/mult/O_30 sp4_v_b_44 +B13[48] buffer wire_mult/mult/O_30 sp4_v_t_1 +B14[47] buffer wire_mult/mult/O_31 sp12_h_l_5 +B14[48] buffer wire_mult/mult/O_31 sp12_h_r_22 +B14[52] buffer wire_mult/mult/O_31 sp12_v_t_13 +B15[46] buffer wire_mult/mult/O_31 sp4_h_l_3 +B14[46] buffer wire_mult/mult/O_31 sp4_h_r_30 +B15[47] buffer wire_mult/mult/O_31 sp4_h_r_46 +B15[52] buffer wire_mult/mult/O_31 sp4_r_v_b_15 +B14[53] buffer wire_mult/mult/O_31 sp4_r_v_b_31 +B15[53] buffer wire_mult/mult/O_31 sp4_r_v_b_47 +B15[48] buffer wire_mult/mult/O_31 sp4_v_b_14 +B14[51] buffer wire_mult/mult/O_31 sp4_v_b_46 +B15[51] buffer wire_mult/mult/O_31 sp4_v_t_19 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 @@ -10682,45 +16776,33 @@ B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 -B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 -!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 -B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B10[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 -B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 -!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 -!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 !B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 -!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 -B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 !B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 -!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 -!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 -B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 -B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 -!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 -B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 !B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 @@ -10733,36 +16815,26 @@ B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 !B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 -B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 !B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 !B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 !B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 -!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 -B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 !B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 -!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 -!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 -B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 -B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 !B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 -!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 !B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 -B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 -!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 !B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 !B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 @@ -10774,9 +16846,6 @@ B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 !B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 !B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 -!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 -B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 -!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 !B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 @@ -10789,7 +16858,6 @@ B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 -!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 !B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 @@ -10802,9 +16870,6 @@ B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 -B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 -B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 -!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 !B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 @@ -10816,8 +16881,6 @@ B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 -!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 -B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 @@ -10830,9 +16893,6 @@ B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 !B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 -B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 -!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 -B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 @@ -10844,9 +16904,6 @@ B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 -!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 -B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 -!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 @@ -10858,11 +16915,7 @@ B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 -B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 -!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 -!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 -!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 @@ -10949,7 +17002,6 @@ B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 !B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 -B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 !B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 !B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 @@ -10958,7 +17010,6 @@ B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 -B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 !B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 !B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 @@ -11006,7 +17057,6 @@ B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 !B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 -B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 !B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 !B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 diff --git a/icefuzz/export.py b/icefuzz/export.py index 52625f2..0aae954 100644 --- a/icefuzz/export.py +++ b/icefuzz/export.py @@ -4,10 +4,12 @@ import os device_class = os.getenv("ICEDEVICE") with open("../icebox/iceboxdb.py", "w") as f: - files = [ "database_io", "database_logic", "database_ramb", "database_ramt"] + files = [ "database_io", "database_logic", "database_ramb", "database_ramt", "database_ipcon_5k"] for device_class in ["5k", "8k"]: files.append("database_ramb_" + device_class) files.append("database_ramt_" + device_class) + for i in range(4): + files.append("database_dsp%d_5k" % i) for i in files: print('%s_txt = """' % i, file=f) with open("%s.txt" % i, "r") as fi: -- cgit v1.2.3 From 64e3c1a9cd81e61d9a3b163c9e9f9390fa4c5c21 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 13 Nov 2017 16:15:16 +0000 Subject: Figure out DSP config bits for all locs --- docs/ultraplus.html | 45 +++++++++- icefuzz/tests/dsp_cbit/.gitignore | 1 + icefuzz/tests/dsp_cbit/dsp_cbits_up5k.txt | 9 ++ icefuzz/tests/dsp_cbit/fuzz_dsp_cbit.py | 132 ++++++++++++++++++++++++++++++ 4 files changed, 184 insertions(+), 3 deletions(-) create mode 100644 icefuzz/tests/dsp_cbit/.gitignore create mode 100644 icefuzz/tests/dsp_cbit/dsp_cbits_up5k.txt create mode 100755 icefuzz/tests/dsp_cbit/fuzz_dsp_cbit.py (limited to 'icefuzz') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 86fd857..4220cad 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -109,9 +109,48 @@ A work-in-progress effort to determine where signals and configuration bits are to DSP1 CBIT[7:0], CBIT[23:16] to DSP2 CBIT[7:0] and CBIT[24] to DSP3 CBIT0.

-

However, there are some locations where configuration bits are swapped between DSP tiles and IPConnect tiles. For example, DSP1 (0, 16) CBIT[4:3] is used - for the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) CBIT[6:5].

-

The exact permutations are not yet known, but a script will be developed to find them.

+

However, there is one location where configuration bits are swapped between DSP tiles and IPConnect tiles. In DSP1 (0, 16) CBIT[4:1] are used + for IP such as the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) CBIT[6:3].

+

The full list of configuration bits, including the changes for the DSP at (0, 15) are described in the table below.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterNormal PositionDSP (0, 15)
Changes
C_REGDSP0.CBIT_0
A_REGDSP0.CBIT_1
B_REGDSP0.CBIT_2
D_REGDSP0.CBIT_3
TOP_8x8_MULT_REGDSP0.CBIT_4
BOT_8x8_MULT_REGDSP0.CBIT_5
PIPELINE_16x16_MULT_REG1DSP0.CBIT_6
PIPELINE_16x16_MULT_REG2DSP0.CBIT_7
TOPOUTPUT_SELECT[0]DSP1.CBIT_0
TOPOUTPUT_SELECT[1]DSP1.CBIT_1(0, 19).CBIT_3
TOPADDSUB_LOWERINPUT[1:0]DSP1.CBIT_[3:2](0, 19).CBIT_[5:4]
TOPADDSUB_UPPERINUTDSP1.CBIT_4(0, 19).CBIT_6
TOPADDSUB_CARRYSELECT[1:0]DSP1.CBIT_[6:5]
BOTOUTPUT_SELECT[0]DSP1.CBIT_7
BOTOUTPUT_SELECT[1]DSP2.CBIT_0
BOTADDSUB_LOWERINPUT[1:0]DSP2.CBIT_[2:1]
BOTADDSUB_UPPERINPUTDSP2.CBIT_3
BOTADDSUB_CARRYSELECTDSP2.CBIT_[5:4]
MODE_8x8DSP2.CBIT_6
A_SIGNEDDSP2.CBIT_7
B_SIGNEDDSP3.CBIT_0
+ +

Lattice document a limited number of supported configurations in the ICE Technology Library document, and Lattice's EDIF parser will + reject designs not following a supported configuration. It is not yet known whether unsupported configurations (such as mixed + signed and unsigned) function correctly or not. +

Other Implementation Notes

diff --git a/icefuzz/tests/dsp_cbit/.gitignore b/icefuzz/tests/dsp_cbit/.gitignore new file mode 100644 index 0000000..83d459d --- /dev/null +++ b/icefuzz/tests/dsp_cbit/.gitignore @@ -0,0 +1 @@ +work_dsp_cbit/ \ No newline at end of file diff --git a/icefuzz/tests/dsp_cbit/dsp_cbits_up5k.txt b/icefuzz/tests/dsp_cbit/dsp_cbits_up5k.txt new file mode 100644 index 0000000..e90c647 --- /dev/null +++ b/icefuzz/tests/dsp_cbit/dsp_cbits_up5k.txt @@ -0,0 +1,9 @@ +DSP (0, 15): + Missing (0, 16, CBIT_1) + Missing (0, 16, CBIT_2) + Missing (0, 16, CBIT_3) + Missing (0, 16, CBIT_4) + New: (0, 19, CBIT_3) + New: (0, 19, CBIT_5) + New: (0, 19, CBIT_4) + New: (0, 19, CBIT_6) diff --git a/icefuzz/tests/dsp_cbit/fuzz_dsp_cbit.py b/icefuzz/tests/dsp_cbit/fuzz_dsp_cbit.py new file mode 100755 index 0000000..79f376c --- /dev/null +++ b/icefuzz/tests/dsp_cbit/fuzz_dsp_cbit.py @@ -0,0 +1,132 @@ +#!/usr/bin/env python3 + +import os, sys + +device = "up5k" + +# This script is designed to determine which DSPs have configuration bits +# not in their usual position, as in some cases DSP and IPConnect tiles have +# their config bits swapped + +# Unfortunately, arbitrary configurations are not allowed by icecube, so +# we define a set that gives us maximum coverage (full coverage is not +# possible as one CBIT is never set) + +allowed_configs = ["1110000010000001001110110", "0010000101000010111111111", "0001111000101100000000000"] + +coverage = set() +for c in allowed_configs: + for i in range(25): + if c[i] == "1": + coverage.add(i) + +assert len(coverage) >= 24 + +def parse_exp(f): + current_x = 0 + current_y = 0 + bits = set() + for line in f: + splitline = line.split(' ') + if splitline[0].endswith("_tile"): + current_x = int(splitline[1]) + current_y = int(splitline[2]) + elif splitline[0] == "IpConfig": + if splitline[1][:5] == "CBIT_": + bitidx = int(splitline[1][5:]) + bits.add((current_x, current_y, bitidx)) + return bits +dsp_locs = [( 0, 5, 0), ( 0, 10, 0), ( 0, 15, 0), ( 0, 23, 0), + (25, 5, 0), (25, 10, 0), (25, 15, 0), (25, 23, 0)] + +dsp_data = {} + +if not os.path.exists("./work_dsp_cbit"): + os.mkdir("./work_dsp_cbit") + +for loc in dsp_locs: + x, y, z = loc + missing_bits = set() + new_bits = set() + for config in allowed_configs: + params = config[::-1] + with open("./work_dsp_cbit/dsp_cbit.v","w") as f: + print(""" + module top(input clk, input a, input b, input c, input d, output y); + """, file=f) + print(""" + SB_MAC16 #( + .C_REG(1'b%s), + .A_REG(1'b%s), + .B_REG(1'b%s), + .D_REG(1'b%s), + .TOP_8x8_MULT_REG(1'b%s), + .BOT_8x8_MULT_REG(1'b%s), + .PIPELINE_16x16_MULT_REG1(1'b%s), + .PIPELINE_16x16_MULT_REG2(1'b%s), + .TOPOUTPUT_SELECT(2'b%s), + .TOPADDSUB_LOWERINPUT(2'b%s), + .TOPADDSUB_UPPERINPUT(1'b%s), + .TOPADDSUB_CARRYSELECT(2'b%s), + .BOTOUTPUT_SELECT(2'b%s), + .BOTADDSUB_LOWERINPUT(2'b%s), + .BOTADDSUB_UPPERINPUT(1'b%s), + .BOTADDSUB_CARRYSELECT(2'b%s), + .MODE_8x8(1'b%s), + .A_SIGNED(1'b%s), + .B_SIGNED(1'b%s) + ) dsp ( + .CLK(clk), + .C(c), + .A(a), + .B(b), + .D(d), + .O(y) + );""" + % ( + params[0], params[1], params[2], params[3], + params[4], params[5], params[6], params[7], + params[8:10][::-1], params[10:12][::-1], params[12], params[13:15][::-1], + params[15:17][::-1], params[17:19][::-1], params[19], params[20:22][::-1], + params[22], params[23], params[24]), file=f) + print("endmodule",file=f) + with open("./work_dsp_cbit/dsp_cbit.pcf","w") as f: + print("set_location dsp %d %d %d" % loc, file=f) + retval = os.system("bash ../../icecube.sh -" + device + " ./work_dsp_cbit/dsp_cbit.v > ./work_dsp_cbit/icecube.log 2>&1") + if retval != 0: + sys.stderr.write('ERROR: icecube returned non-zero error code\n') + sys.exit(1) + retval = os.system("../../../icebox/icebox_explain.py ./work_dsp_cbit/dsp_cbit.asc > ./work_dsp_cbit/dsp_cbit.exp") + if retval != 0: + sys.stderr.write('ERROR: icebox_explain returned non-zero error code\n') + sys.exit(1) + bits = set() + known = set() + with open('./work_dsp_cbit/dsp_cbit.exp', 'r') as f: + bits = parse_exp(f) + for i in range(25): + if params[i] == "1": + exp_pos = (x, y + (i // 8), i % 8) + if exp_pos not in bits: + missing_bits.add(exp_pos) + else: + known.add(exp_pos) + for bit in bits: + if bit not in known: + new_bits.add(bit) + if len(missing_bits) > 0 or len(new_bits) > 0: + print("DSP (%d, %d):" % (x, y)) + for bit in missing_bits: + print("\tMissing (%d, %d, CBIT_%d)" % bit) + for bit in new_bits: + print("\tNew: (%d, %d, CBIT_%d)" % bit) + dsp_data[loc] = (missing_bits, new_bits) +with open("dsp_cbits_%s.txt" % device, 'w') as f: + for loc in dsp_data: + x, y, z = loc + missing_bits, new_bits = dsp_data[loc] + print("DSP (%d, %d):" % (x, y), file=f) + for bit in missing_bits: + print("\tMissing (%d, %d, CBIT_%d)" % bit,file=f) + for bit in new_bits: + print("\tNew: (%d, %d, CBIT_%d)" % bit,file=f) -- cgit v1.2.3 From 2f962ac92e018370793b9db3635fabd5b599afef Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 13 Nov 2017 16:51:28 +0000 Subject: Fix 5k corner routing, and reverse engineer SPRAM --- docs/ultraplus.html | 24 ++++ icebox/icebox.py | 113 +++++++++++++--- icefuzz/tests/spram/.gitignore | 1 + icefuzz/tests/spram/fuzz_spram.py | 173 ++++++++++++++++++++++++ icefuzz/tests/spram/up5k_spram_data.txt | 232 ++++++++++++++++++++++++++++++++ 5 files changed, 523 insertions(+), 20 deletions(-) create mode 100644 icefuzz/tests/spram/.gitignore create mode 100755 icefuzz/tests/spram/fuzz_spram.py create mode 100644 icefuzz/tests/spram/up5k_spram_data.txt (limited to 'icefuzz') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 4220cad..1074862 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -193,4 +193,28 @@ The CLKLF output of SB_LFOSC is conne

SB_LFOSC has no configuration bits.

+

SPRAM

+

The UltraPlus devices have 1Mbit of extra single-ported RAM, split into 4 256kbit blocks. The full list of connections for each SPRAM block in the 5k device is shown below, + as well as the location of the 1 configuration bit which is set to enable use of that SPRAM block.

+ + + + + + + + + + + + + + + + + + + +
SignalSPRAM (0, 0, 1)SPRAM (0, 0, 2)SPRAM (25, 0, 3)SPRAM (25, 0, 4)
ADDRESS[1:0](0, 2, lutff_[1:0]/in_1)(0, 2, lutff_[7:6]/in_0)(25, 2, lutff_[1:0]/in_1)(25, 2, lutff_[7:6]/in_0)
ADDRESS[7:2](0, 2, lutff_[7:2]/in_1)(0, 3, lutff_[5:0]/in_3)(25, 2, lutff_[7:2]/in_1)(25, 3, lutff_[5:0]/in_3)
ADDRESS[9:8](0, 2, lutff_[1:0]/in_0)(0, 3, lutff_[7:6]/in_3)(25, 2, lutff_[1:0]/in_0)(25, 3, lutff_[7:6]/in_3)
ADDRESS[13:10](0, 2, lutff_[5:2]/in_0)(0, 3, lutff_[3:0]/in_1)(25, 2, lutff_[5:2]/in_0)(25, 3, lutff_[3:0]/in_1)
DATAIN[7:0](0, 1, lutff_[7:0]/in_3)(0, 1, lutff_[7:0]/in_0)(25, 1, lutff_[7:0]/in_3)(25, 1, lutff_[7:0]/in_0)
DATAIN[15:8](0, 1, lutff_[7:0]/in_1)(0, 2, lutff_[7:0]/in_3)(25, 1, lutff_[7:0]/in_1)(25, 2, lutff_[7:0]/in_3)
MASKWREN[3:0](0, 3, lutff_[3:0]/in_0)(0, 3, lutff_[7:4]/in_0)(25, 3, lutff_[3:0]/in_0)(25, 3, lutff_[7:4]/in_0)
WREN(0, 3, lutff_4/in_1)(0, 3, lutff_5/in_1)(25, 3, lutff_4/in_1)(25, 3, lutff_5/in_1)
CHIPSELECT(0, 3, lutff_6/in_1)(0, 3, lutff_7/in_1)(25, 3, lutff_6/in_1)(25, 3, lutff_7/in_1)
CLOCK(0, 1, clk)(0, 2, clk)(25, 1, clk)(25, 2, clk)
STANDBY(0, 4, lutff_0/in_3)(0, 4, lutff_1/in_3)(25, 4, lutff_0/in_3)(25, 4, lutff_1/in_3)
SLEEP(0, 4, lutff_2/in_3)(0, 4, lutff_3/in_3)(25, 4, lutff_2/in_3)(25, 4, lutff_3/in_3)
POWEROFF(0, 4, lutff_4/in_3)(0, 4, lutff_5/in_3)(25, 4, lutff_4/in_3)(25, 4, lutff_5/in_3)
DATAOUT[7:0](0, 1, slf_op_[7:0])(0, 3, slf_op_[7:0])(25, 1, slf_op_[7:0])(25, 3, slf_op_[7:0])
DATAOUT[15:8](0, 2, slf_op_[7:0])(0, 4, slf_op_[7:0])(25, 2, slf_op_[7:0])(25, 4, slf_op_[7:0])
SPRAM_ENABLE(0, 1, CBIT_0)(0, 1, CBIT_1)(25, 1, CBIT_0)(25, 1, CBIT_1)
+ diff --git a/icebox/icebox.py b/icebox/icebox.py index a6d7155..9b3e35f 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -313,25 +313,25 @@ class iceconfig: if netname.startswith("logic_op_bot_"): if y == self.max_y and 0 < x < self.max_x: return True if netname.startswith("logic_op_bnl_"): - if x == self.max_x and 1 < y < self.max_y: return True + if x == self.max_x and 1 < y < self.max_y and (self.device != "5k"): return True if y == self.max_y and 1 < x < self.max_x: return True if netname.startswith("logic_op_bnr_"): - if x == 0 and 1 < y < self.max_y: return True + if x == 0 and 1 < y < self.max_y and (self.device != "5k"): return True if y == self.max_y and 0 < x < self.max_x-1: return True if netname.startswith("logic_op_top_"): if y == 0 and 0 < x < self.max_x: return True if netname.startswith("logic_op_tnl_"): - if x == self.max_x and 0 < y < self.max_y-1: return True + if x == self.max_x and 0 < y < self.max_y-1 and (self.device != "5k"): return True if y == 0 and 1 < x < self.max_x: return True if netname.startswith("logic_op_tnr_"): - if x == 0 and 0 < y < self.max_y-1: return True + if x == 0 and 0 < y < self.max_y-1 and (self.device != "5k"): return True if y == 0 and 0 < x < self.max_x-1: return True if netname.startswith("logic_op_lft_"): - if x == self.max_x: return True + if x == self.max_x and (self.device != "5k"): return True if netname.startswith("logic_op_rgt_"): - if x == 0: return True + if x == 0 and (self.device != "5k"): return True return False @@ -355,7 +355,7 @@ class iceconfig: def follow_funcnet(self, x, y, func): neighbours = set() def do_direction(name, nx, ny): - if 0 < nx < self.max_x and 0 < ny < self.max_y: + if (0 < nx < self.max_x or self.device == "5k") and 0 < ny < self.max_y: neighbours.add((nx, ny, "neigh_op_%s_%d" % (name, func))) if nx in (0, self.max_x) and 0 < ny < self.max_y and nx != x: neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) @@ -444,7 +444,52 @@ class iceconfig: assert False return funcnets - + + #UltraPlus corner routing: given the corner name and net index, + #return a tuple containing H and V indexes, or none if NA + def ultraplus_trace_corner(self, corner, idx): + h_idx = None + v_idx = None + if corner == "bl": + if idx >= 4: + v_idx = idx + 28 + if idx >= 32 and idx < 48: + h_idx = idx - 28 + elif corner == "tl": + #TODO: bounds check for v_idx case? + v_idx = (idx + 8) ^ 1 + if idx >= 8 and idx < 32: + h_idx = (idx ^ 1) - 8 + elif corner == "tr": + #TODO: bounds check for v_idx case? + if idx <= 24: + v_idx = (idx + 12) ^ 1 + if idx >= 12 and idx < 36: + h_idx = (idx ^ 1) - 12 + elif corner == "br": + #TODO: bounds check for v_idx case? + if idx <= 16: + v_idx = idx + 32 + if idx >= 32 and idx < 48: #check + h_idx = idx - 32 + return (h_idx, v_idx) + + def get_corner(self, x, y): + corner = "" + if y == 0: + corner += "b" + elif y == self.max_y: + corner += "t" + else: + corner += "x" + if x == 0: + corner += "l" + elif x == self.max_x: + corner += "r" + else: + corner += "x" + return corner + def follow_net(self, netspec): x, y, netname = netspec neighbours = self.rlookup_funcnet(x, y, netname) @@ -465,7 +510,7 @@ class iceconfig: neighbours.add((nx, ny, netname)) match = re.match(r"sp4_r_v_b_(\d+)", netname) - if match and ((0 < x < self.max_x-1) or (self.device == "5k")): + if match and ((0 < x < self.max_x-1) or (self.device == "5k" and (x < self.max_x))): neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1)))) #print('\tafter r_v_b', neighbours) @@ -501,23 +546,39 @@ class iceconfig: if s[0] in (0, self.max_x) and s[1] in (0, self.max_y): if re.match("span4_(vert|horz)_[lrtb]_\d+$", n): - + m = re.match("span4_(vert|horz)_([lrtb])_\d+$", n) + if self.device == "5k" and (m.group(2) == "l" or m.group(2) == "t"): + continue vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") if self.device == "5k": m = re.match("span4_vert_([lrtb])_(\d+)$", vert_net) assert m - vert_net = "sp4_v_%s_%d" % (m.group(1), int(m.group(2)) + 28) + idx = int(m.group(2)) + h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) + if v_idx is None: + if (s[0] == 0 and s[1] == 0 and direction == "l") or (s[0] == self.max_x and s[1] == self.max_y and direction == "r"): + continue + else: + vert_net = "sp4_v_%s_%d" % (m.group(1), v_idx) m = re.match("span4_horz_([lrtb])_(\d+)$", horz_net) assert m - horz_net = "span4_horz_%s_%d" % (m.group(1), int(m.group(2)) - 28) + idx = int(m.group(2)) + h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) + if h_idx is None: + if (s[0] == 0 and s[1] == 0 and direction == "b") or (s[0] == self.max_x and s[1] == self.max_y and direction == "t"): + continue + else: + horz_net = "span4_horz_%s_%d" % (m.group(1), h_idx) + + if s[0] == 0 and s[1] == 0: if direction == "l": s = (0, 1, vert_net) if direction == "b": s = (1, 0, horz_net) - + if s[0] == self.max_x and s[1] == self.max_y: if direction == "r": s = (self.max_x, self.max_y-1, vert_net) if direction == "t": s = (self.max_x-1, self.max_y, horz_net) @@ -525,23 +586,35 @@ class iceconfig: vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_").replace("_h_", "_v_") horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_").replace("_v_", "_h_") - if self.device == "5k": + if self.device == "5k": m = re.match("(span4_vert|sp4_v)_([lrtb])_(\d+)$", vert_net) assert m - vert_net = "sp4_v_%s_%d" % (m.group(2), int(m.group(3)) + 28) + idx = int(m.group(3)) + h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) + if v_idx is None: + if (s[0] == 0 and s[1] == self.max_y and direction == "l") or (s[0] == self.max_x and s[1] == 0 and direction == "r"): + continue + else: + vert_net = "sp4_v_%s_%d" % (m.group(2), v_idx) m = re.match("(span4_horz|sp4_h)_([lrtb])_(\d+)$", horz_net) assert m - horz_net = "span4_horz_%s_%d" % (m.group(2), int(m.group(3)) - 28) + idx = int(m.group(3)) + h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) + if h_idx is None: + if (s[0] == 0 and s[1] == self.max_y and direction == "t") or (s[0] == self.max_x and s[1] == 0 and direction == "b"): + continue + else: + horz_net = "span4_horz_%s_%d" % (m.group(2), h_idx) if s[0] == 0 and s[1] == self.max_y: if direction == "l": s = (0, self.max_y-1, vert_net) if direction == "t": s = (1, self.max_y, horz_net) - + if s[0] == self.max_x and s[1] == 0: if direction == "r": s = (self.max_x, 1, vert_net) if direction == "b": s = (self.max_x-1, 0, horz_net) - + if self.tile_has_net(s[0], s[1], s[2]): neighbours.add((s[0], s[1], s[2])) @@ -1097,13 +1170,13 @@ def pos_follow_net(pos, direction, netname, device): if case == "rr" and idx >= 12: return "span4_horz_l_%d" % idx - if pos == "l" and direction == "r": + if pos == "l" and direction == "r" and (device != "5k"): m = re.match("span4_horz_(\d+)$", netname) if m: return sp4h_normalize("sp4_h_l_%s" % m.group(1)) m = re.match("span12_horz_(\d+)$", netname) if m: return sp12h_normalize("sp12_h_l_%s" % m.group(1)) - if pos == "r" and direction == "l": + if pos == "r" and direction == "l" and (device != "5k"): m = re.match("span4_horz_(\d+)$", netname) if m: return sp4h_normalize("sp4_h_r_%s" % m.group(1)) m = re.match("span12_horz_(\d+)$", netname) diff --git a/icefuzz/tests/spram/.gitignore b/icefuzz/tests/spram/.gitignore new file mode 100644 index 0000000..c6ebe02 --- /dev/null +++ b/icefuzz/tests/spram/.gitignore @@ -0,0 +1 @@ +work_spram/ \ No newline at end of file diff --git a/icefuzz/tests/spram/fuzz_spram.py b/icefuzz/tests/spram/fuzz_spram.py new file mode 100755 index 0000000..33e62cb --- /dev/null +++ b/icefuzz/tests/spram/fuzz_spram.py @@ -0,0 +1,173 @@ +#!/usr/bin/env python3 + +import os, sys, re + +device = "up5k" + +pins = "2 3 4 6 9 10 11 12 13 18 19 20 21 25 26 27 28 31 32 34 35 36 37 38 42 43 44 45 46 47 48".split() + +# This script is designed to determine the routing of 5k SPRAM signals, +# and the location of the enable config bits + +spram_locs = [(0, 0, 1), (0, 0, 2), (25, 0, 3), (25, 0, 4)] +#spram_locs = [(0, 0, 1)] +spram_data = { } + +spram_signals = ["WREN", "CHIPSELECT", "CLOCK", "STANDBY", "SLEEP", "POWEROFF"] + +for i in range(14): + spram_signals.append("ADDRESS[%d]" % i) + +for i in range(16): + spram_signals.append("DATAIN[%d]" % i) + +for i in range(16): + spram_signals.append("DATAOUT[%d]" % i) + +for i in range(4): + spram_signals.append("MASKWREN[%d]" % i) + +fuzz_options = ["ADDRESS", "DATAIN", "MASKWREN", "DATAOUT"] + +#Parse the output of an icebox vlog file to determine connectivity +def parse_vlog(f, pin2net, net_map): + current_net = None + + for line in f: + m = re.match(r"wire ([a-zA-Z0-9_]+);", line) + if m: + net = m.group(1) + mp = re.match(r"pin_([a-zA-Z0-9]+)", net) + if mp: + pin = mp.group(1) + if pin in pin2net: + current_net = pin2net[pin] + else: + current_net = None + else: + current_net = None + elif current_net is not None: + m = re.match(r"// \((\d+), (\d+), '([a-zA-Z0-9_/]+)'\)", line) + if m: + x = int(m.group(1)) + y = int(m.group(2)) + net = m.group(3) + if not (net.startswith("sp") or net.startswith("glb") or net.startswith("neigh") or net.startswith("io") or net.startswith("local") or net.startswith("fabout")): + net_map[current_net].add((x, y, net)) +def parse_exp(f): + current_x = 0 + current_y = 0 + bits = set() + for line in f: + splitline = line.split(' ') + if splitline[0].endswith("_tile"): + current_x = int(splitline[1]) + current_y = int(splitline[2]) + elif splitline[0] == "IpConfig": + if splitline[1][:5] == "CBIT_": + bitidx = int(splitline[1][5:]) + bits.add((current_x, current_y, splitline[1].strip())) + return bits + +if not os.path.exists("./work_spram"): + os.mkdir("./work_spram") + +for loc in spram_locs: + x, y, z = loc + net_map = {} + for sig in spram_signals: + net_map[sig] = set() + net_map["C_SPRAM_EN"] = set() # actually a CBIT not a net + + for n in fuzz_options: + with open("./work_spram/spram.v","w") as f: + print(""" + module top( + input WREN, + input CHIPSELECT, + input CLOCK, + input STANDBY, + input SLEEP, + input POWEROFF, + """, file=f) + if n == "ADDRESS": + print("\t\t\tinput [13:0] ADDRESS,", file=f) + if n == "DATAIN": + print("\t\t\tinput [15:0] DATAIN,", file=f) + if n == "MASKWREN": + print("\t\t\tinput [3:0] MASKWREN,", file=f) + if n == "DATAOUT": + print("\t\t\toutput [15:0] DATAOUT);", file=f) + else: + print("\t\t\toutput [0:0] DATAOUT);", file=f) #some dataout is always required to prevent optimisation away + + addr_net = "ADDRESS" if n == "ADDRESS" else "" + din_net = "DATAIN" if n == "DATAIN" else "" + mwren_net = "MASKWREN" if n == "MASKWREN" else "" + + print(""" + SB_SPRAM256KA spram_i + ( + .ADDRESS(%s), + .DATAIN(%s), + .MASKWREN(%s), + .WREN(WREN), + .CHIPSELECT(CHIPSELECT), + .CLOCK(CLOCK), + .STANDBY(STANDBY), + .SLEEP(SLEEP), + .POWEROFF(POWEROFF), + .DATAOUT(DATAOUT) + ); + """ % (addr_net, din_net, mwren_net), file=f) + print("endmodule",file=f) + pin2net = {} + with open("./work_spram/spram.pcf","w") as f: + temp_pins = list(pins) + for sig in spram_signals: + if sig.startswith("ADDRESS") and n != "ADDRESS": + continue + if sig.startswith("DATAIN") and n != "DATAIN": + continue + if sig.startswith("MASKWREN") and n != "MASKWREN": + continue + if sig.startswith("DATAOUT") and n != "DATAOUT" and sig != "DATAOUT[0]": + continue + + if len(temp_pins) == 0: + sys.stderr.write("ERROR: no remaining pins to alloc") + sys.exit(1) + + pin = temp_pins.pop() + pin2net[pin] = sig + print("set_io %s %s" % (sig, pin), file=f) + print("set_location spram_i %d %d %d" % loc, file=f) + retval = os.system("bash ../../icecube.sh -" + device + " ./work_spram/spram.v > ./work_spram/icecube.log 2>&1") + if retval != 0: + sys.stderr.write('ERROR: icecube returned non-zero error code\n') + sys.exit(1) + retval = os.system("../../../icebox/icebox_explain.py ./work_spram/spram.asc > ./work_spram/spram.exp") + if retval != 0: + sys.stderr.write('ERROR: icebox_explain returned non-zero error code\n') + sys.exit(1) + retval = os.system("../../../icebox/icebox_vlog.py -l ./work_spram/spram.asc > ./work_spram/spram.vlog") + if retval != 0: + sys.stderr.write('ERROR: icebox_vlog returned non-zero error code\n') + sys.exit(1) + with open("./work_spram/spram.vlog", "r") as f: + parse_vlog(f, pin2net, net_map) + bits = [] + with open("./work_spram/spram.exp", "r") as f: + bits = parse_exp(f) + net_map["C_SPRAM_EN"].update(bits) + spram_data[loc] = net_map + +with open(device + "_spram_data.txt", "w") as f: + for loc in spram_data: + print("SPRAM %d %d %d" % loc, file=f) + data = spram_data[loc] + for net in sorted(data): + cnets = [] + for cnet in data[net]: + cnets.append("(%d, %d, %s)" % cnet) + print("\t%s: %s" % (net, " ".join(cnets)), file=f) \ No newline at end of file diff --git a/icefuzz/tests/spram/up5k_spram_data.txt b/icefuzz/tests/spram/up5k_spram_data.txt new file mode 100644 index 0000000..c824e73 --- /dev/null +++ b/icefuzz/tests/spram/up5k_spram_data.txt @@ -0,0 +1,232 @@ +SPRAM 0 0 1 + ADDRESS[0]: (0, 2, lutff_0/in_1) + ADDRESS[10]: (0, 2, lutff_2/in_0) + ADDRESS[11]: (0, 2, lutff_3/in_0) + ADDRESS[12]: (0, 2, lutff_4/in_0) + ADDRESS[13]: (0, 2, lutff_5/in_0) + ADDRESS[1]: (0, 2, lutff_1/in_1) + ADDRESS[2]: (0, 2, lutff_2/in_1) + ADDRESS[3]: (0, 2, lutff_3/in_1) + ADDRESS[4]: (0, 2, lutff_4/in_1) + ADDRESS[5]: (0, 2, lutff_5/in_1) + ADDRESS[6]: (0, 2, lutff_6/in_1) + ADDRESS[7]: (0, 2, lutff_7/in_1) + ADDRESS[8]: (0, 2, lutff_0/in_0) + ADDRESS[9]: (0, 2, lutff_1/in_0) + CHIPSELECT: (0, 3, lutff_6/in_1) + CLOCK: (0, 1, clk) + C_SPRAM_EN: (0, 1, CBIT_0) + DATAIN[0]: (0, 1, lutff_0/in_3) + DATAIN[10]: (0, 1, lutff_2/in_1) + DATAIN[11]: (0, 1, lutff_3/in_1) + DATAIN[12]: (0, 1, lutff_4/in_1) + DATAIN[13]: (0, 1, lutff_5/in_1) + DATAIN[14]: (0, 1, lutff_6/in_1) + DATAIN[15]: (0, 1, lutff_7/in_1) + DATAIN[1]: (0, 1, lutff_1/in_3) + DATAIN[2]: (0, 1, lutff_2/in_3) + DATAIN[3]: (0, 1, lutff_3/in_3) + DATAIN[4]: (0, 1, lutff_4/in_3) + DATAIN[5]: (0, 1, lutff_5/in_3) + DATAIN[6]: (0, 1, lutff_6/in_3) + DATAIN[7]: (0, 1, lutff_7/in_3) + DATAIN[8]: (0, 1, lutff_0/in_1) + DATAIN[9]: (0, 1, lutff_1/in_1) + DATAOUT[0]: (0, 1, slf_op_0) + DATAOUT[10]: (0, 2, slf_op_2) + DATAOUT[11]: (0, 2, slf_op_3) + DATAOUT[12]: (0, 2, slf_op_4) + DATAOUT[13]: (0, 2, slf_op_5) + DATAOUT[14]: (0, 2, slf_op_6) + DATAOUT[15]: (0, 2, slf_op_7) + DATAOUT[1]: (0, 1, slf_op_1) + DATAOUT[2]: (0, 1, slf_op_2) + DATAOUT[3]: (0, 1, slf_op_3) + DATAOUT[4]: (0, 1, slf_op_4) + DATAOUT[5]: (0, 1, slf_op_5) + DATAOUT[6]: (0, 1, slf_op_6) + DATAOUT[7]: (0, 1, slf_op_7) + DATAOUT[8]: (0, 2, slf_op_0) + DATAOUT[9]: (0, 2, slf_op_1) + MASKWREN[0]: (0, 3, lutff_0/in_0) + MASKWREN[1]: (0, 3, lutff_1/in_0) + MASKWREN[2]: (0, 3, lutff_2/in_0) + MASKWREN[3]: (0, 3, lutff_3/in_0) + POWEROFF: (0, 4, lutff_4/in_3) + SLEEP: (0, 4, lutff_2/in_3) + STANDBY: (0, 4, lutff_0/in_3) + WREN: (0, 3, lutff_4/in_1) +SPRAM 0 0 2 + ADDRESS[0]: (0, 2, lutff_6/in_0) + ADDRESS[10]: (0, 3, lutff_0/in_1) + ADDRESS[11]: (0, 3, lutff_1/in_1) + ADDRESS[12]: (0, 3, lutff_2/in_1) + ADDRESS[13]: (0, 3, lutff_3/in_1) + ADDRESS[1]: (0, 2, lutff_7/in_0) + ADDRESS[2]: (0, 3, lutff_0/in_3) + ADDRESS[3]: (0, 3, lutff_1/in_3) + ADDRESS[4]: (0, 3, lutff_2/in_3) + ADDRESS[5]: (0, 3, lutff_3/in_3) + ADDRESS[6]: (0, 3, lutff_4/in_3) + ADDRESS[7]: (0, 3, lutff_5/in_3) + ADDRESS[8]: (0, 3, lutff_6/in_3) + ADDRESS[9]: (0, 3, lutff_7/in_3) + CHIPSELECT: (0, 3, lutff_7/in_1) + CLOCK: (0, 2, clk) + C_SPRAM_EN: (0, 1, CBIT_1) + DATAIN[0]: (0, 1, lutff_0/in_0) + DATAIN[10]: (0, 2, lutff_2/in_3) + DATAIN[11]: (0, 2, lutff_3/in_3) + DATAIN[12]: (0, 2, lutff_4/in_3) + DATAIN[13]: (0, 2, lutff_5/in_3) + DATAIN[14]: (0, 2, lutff_6/in_3) + DATAIN[15]: (0, 2, lutff_7/in_3) + DATAIN[1]: (0, 1, lutff_1/in_0) + DATAIN[2]: (0, 1, lutff_2/in_0) + DATAIN[3]: (0, 1, lutff_3/in_0) + DATAIN[4]: (0, 1, lutff_4/in_0) + DATAIN[5]: (0, 1, lutff_5/in_0) + DATAIN[6]: (0, 1, lutff_6/in_0) + DATAIN[7]: (0, 1, lutff_7/in_0) + DATAIN[8]: (0, 2, lutff_0/in_3) + DATAIN[9]: (0, 2, lutff_1/in_3) + DATAOUT[0]: (0, 3, slf_op_0) + DATAOUT[10]: (0, 4, slf_op_2) + DATAOUT[11]: (0, 4, slf_op_3) + DATAOUT[12]: (0, 4, slf_op_4) + DATAOUT[13]: (0, 4, slf_op_5) + DATAOUT[14]: (0, 4, slf_op_6) + DATAOUT[15]: (0, 4, slf_op_7) + DATAOUT[1]: (0, 3, slf_op_1) + DATAOUT[2]: (0, 3, slf_op_2) + DATAOUT[3]: (0, 3, slf_op_3) + DATAOUT[4]: (0, 3, slf_op_4) + DATAOUT[5]: (0, 3, slf_op_5) + DATAOUT[6]: (0, 3, slf_op_6) + DATAOUT[7]: (0, 3, slf_op_7) + DATAOUT[8]: (0, 4, slf_op_0) + DATAOUT[9]: (0, 4, slf_op_1) + MASKWREN[0]: (0, 3, lutff_4/in_0) + MASKWREN[1]: (0, 3, lutff_5/in_0) + MASKWREN[2]: (0, 3, lutff_6/in_0) + MASKWREN[3]: (0, 3, lutff_7/in_0) + POWEROFF: (0, 4, lutff_5/in_3) + SLEEP: (0, 4, lutff_3/in_3) + STANDBY: (0, 4, lutff_1/in_3) + WREN: (0, 3, lutff_5/in_1) +SPRAM 25 0 3 + ADDRESS[0]: (25, 2, lutff_0/in_1) + ADDRESS[10]: (25, 2, lutff_2/in_0) + ADDRESS[11]: (25, 2, lutff_3/in_0) + ADDRESS[12]: (25, 2, lutff_4/in_0) + ADDRESS[13]: (25, 2, lutff_5/in_0) + ADDRESS[1]: (25, 2, lutff_1/in_1) + ADDRESS[2]: (25, 2, lutff_2/in_1) + ADDRESS[3]: (25, 2, lutff_3/in_1) + ADDRESS[4]: (25, 2, lutff_4/in_1) + ADDRESS[5]: (25, 2, lutff_5/in_1) + ADDRESS[6]: (25, 2, lutff_6/in_1) + ADDRESS[7]: (25, 2, lutff_7/in_1) + ADDRESS[8]: (25, 2, lutff_0/in_0) + ADDRESS[9]: (25, 2, lutff_1/in_0) + CHIPSELECT: (25, 3, lutff_6/in_1) + CLOCK: (25, 1, clk) + C_SPRAM_EN: (25, 1, CBIT_0) + DATAIN[0]: (25, 1, lutff_0/in_3) + DATAIN[10]: (25, 1, lutff_2/in_1) + DATAIN[11]: (25, 1, lutff_3/in_1) + DATAIN[12]: (25, 1, lutff_4/in_1) + DATAIN[13]: (25, 1, lutff_5/in_1) + DATAIN[14]: (25, 1, lutff_6/in_1) + DATAIN[15]: (25, 1, lutff_7/in_1) + DATAIN[1]: (25, 1, lutff_1/in_3) + DATAIN[2]: (25, 1, lutff_2/in_3) + DATAIN[3]: (25, 1, lutff_3/in_3) + DATAIN[4]: (25, 1, lutff_4/in_3) + DATAIN[5]: (25, 1, lutff_5/in_3) + DATAIN[6]: (25, 1, lutff_6/in_3) + DATAIN[7]: (25, 1, lutff_7/in_3) + DATAIN[8]: (25, 1, lutff_0/in_1) + DATAIN[9]: (25, 1, lutff_1/in_1) + DATAOUT[0]: (25, 1, slf_op_0) + DATAOUT[10]: (25, 2, slf_op_2) + DATAOUT[11]: (25, 2, slf_op_3) + DATAOUT[12]: (25, 2, slf_op_4) + DATAOUT[13]: (25, 2, slf_op_5) + DATAOUT[14]: (25, 2, slf_op_6) + DATAOUT[15]: (25, 2, slf_op_7) + DATAOUT[1]: (25, 1, slf_op_1) + DATAOUT[2]: (25, 1, slf_op_2) + DATAOUT[3]: (25, 1, slf_op_3) + DATAOUT[4]: (25, 1, slf_op_4) + DATAOUT[5]: (25, 1, slf_op_5) + DATAOUT[6]: (25, 1, slf_op_6) + DATAOUT[7]: (25, 1, slf_op_7) + DATAOUT[8]: (25, 2, slf_op_0) + DATAOUT[9]: (25, 2, slf_op_1) + MASKWREN[0]: (25, 3, lutff_0/in_0) + MASKWREN[1]: (25, 3, lutff_1/in_0) + MASKWREN[2]: (25, 3, lutff_2/in_0) + MASKWREN[3]: (25, 3, lutff_3/in_0) + POWEROFF: (25, 4, lutff_4/in_3) + SLEEP: (25, 4, lutff_2/in_3) + STANDBY: (25, 4, lutff_0/in_3) + WREN: (25, 3, lutff_4/in_1) +SPRAM 25 0 4 + ADDRESS[0]: (25, 2, lutff_6/in_0) + ADDRESS[10]: (25, 3, lutff_0/in_1) + ADDRESS[11]: (25, 3, lutff_1/in_1) + ADDRESS[12]: (25, 3, lutff_2/in_1) + ADDRESS[13]: (25, 3, lutff_3/in_1) + ADDRESS[1]: (25, 2, lutff_7/in_0) + ADDRESS[2]: (25, 3, lutff_0/in_3) + ADDRESS[3]: (25, 3, lutff_1/in_3) + ADDRESS[4]: (25, 3, lutff_2/in_3) + ADDRESS[5]: (25, 3, lutff_3/in_3) + ADDRESS[6]: (25, 3, lutff_4/in_3) + ADDRESS[7]: (25, 3, lutff_5/in_3) + ADDRESS[8]: (25, 3, lutff_6/in_3) + ADDRESS[9]: (25, 3, lutff_7/in_3) + CHIPSELECT: (25, 3, lutff_7/in_1) + CLOCK: (25, 2, clk) + C_SPRAM_EN: (25, 1, CBIT_1) + DATAIN[0]: (25, 1, lutff_0/in_0) + DATAIN[10]: (25, 2, lutff_2/in_3) + DATAIN[11]: (25, 2, lutff_3/in_3) + DATAIN[12]: (25, 2, lutff_4/in_3) + DATAIN[13]: (25, 2, lutff_5/in_3) + DATAIN[14]: (25, 2, lutff_6/in_3) + DATAIN[15]: (25, 2, lutff_7/in_3) + DATAIN[1]: (25, 1, lutff_1/in_0) + DATAIN[2]: (25, 1, lutff_2/in_0) + DATAIN[3]: (25, 1, lutff_3/in_0) + DATAIN[4]: (25, 1, lutff_4/in_0) + DATAIN[5]: (25, 1, lutff_5/in_0) + DATAIN[6]: (25, 1, lutff_6/in_0) + DATAIN[7]: (25, 1, lutff_7/in_0) + DATAIN[8]: (25, 2, lutff_0/in_3) + DATAIN[9]: (25, 2, lutff_1/in_3) + DATAOUT[0]: (25, 3, slf_op_0) + DATAOUT[10]: (25, 4, slf_op_2) + DATAOUT[11]: (25, 4, slf_op_3) + DATAOUT[12]: (25, 4, slf_op_4) + DATAOUT[13]: (25, 4, slf_op_5) + DATAOUT[14]: (25, 4, slf_op_6) + DATAOUT[15]: (25, 4, slf_op_7) + DATAOUT[1]: (25, 3, slf_op_1) + DATAOUT[2]: (25, 3, slf_op_2) + DATAOUT[3]: (25, 3, slf_op_3) + DATAOUT[4]: (25, 3, slf_op_4) + DATAOUT[5]: (25, 3, slf_op_5) + DATAOUT[6]: (25, 3, slf_op_6) + DATAOUT[7]: (25, 3, slf_op_7) + DATAOUT[8]: (25, 4, slf_op_0) + DATAOUT[9]: (25, 4, slf_op_1) + MASKWREN[0]: (25, 3, lutff_4/in_0) + MASKWREN[1]: (25, 3, lutff_5/in_0) + MASKWREN[2]: (25, 3, lutff_6/in_0) + MASKWREN[3]: (25, 3, lutff_7/in_0) + POWEROFF: (25, 4, lutff_5/in_3) + SLEEP: (25, 4, lutff_3/in_3) + STANDBY: (25, 4, lutff_1/in_3) + WREN: (25, 3, lutff_5/in_1) -- cgit v1.2.3 From 25ad7a24b96b021c6ab25e275059e20187b4f882 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 14 Nov 2017 14:06:38 +0000 Subject: 5k RGB driver reverse engineered --- docs/ultraplus.html | 28 ++++ icefuzz/tests/rgba_drv_cbit/.gitignore | 1 + icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py | 174 +++++++++++++++++++++ icefuzz/tests/rgba_drv_cbit/rgba_drv_data_up5k.txt | 20 +++ 4 files changed, 223 insertions(+) create mode 100644 icefuzz/tests/rgba_drv_cbit/.gitignore create mode 100755 icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py create mode 100644 icefuzz/tests/rgba_drv_cbit/rgba_drv_data_up5k.txt (limited to 'icefuzz') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 1074862..1b9e950 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -217,4 +217,32 @@ The CLKLF output of SB_LFOSC is conne SPRAM_ENABLE(0, 1, CBIT_0)(0, 1, CBIT_1)(25, 1, CBIT_0)(25, 1, CBIT_1) +

RGB LED Driver

+

The UltraPlus devices contain an internal 3-channel 2-24mA constant-current driver intended for RGB led driving (SB_RGBA_DRV). It is broken out onto 3 pins: 39, 40 and 41 on the QFN48 package. +The LED driver is implemented using the IPConnect tiles and is entirely seperate to the IO cells, if the LED driver is ignored or disabled on a pin then the pin +can be used as an open-drain IO using the standard IO cell.

+

Note that the UltraPlus devices also have a seperate PWM generator IP core, which would often be connected to this one to create LED effects such as "breathing" without + involving FPGA resources.

+

The LED driver connections are shown in the label below.

+ + + + + + + +
SignalNet
CURREN(25, 29, lutff_6/in_3)
RGBLEDEN(0, 30, lutff_1/in_1)
RGB0PWM(0, 30, lutff_2/in_1)
RGB1PWM(0, 30, lutff_3/in_1)
RGB2PWM(0, 30, lutff_4/in_1)
+

The configuration bits are as follows. As well as the documented bits, another bit "RGBA_DRV_EN" is set if any of the channels are enabled.

+ + + + + + + + + + + +
ParameterBit
RGBA_DRV_EN(0, 28, CBIT_5)
RGB0_CURRENT[1:0](0, 28, CBIT_[7:6])
RGB0_CURRENT[5:2](0, 29, CBIT_[3:0])
RGB1_CURRENT[3:0](0, 29, CBIT_[7:4])
RGB1_CURRENT[5:4](0, 30, CBIT_[1:0])
RGB2_CURRENT[5:0](0, 30, CBIT_[7:2])
CURRENT_MODE(0, 28, CBIT_4)
diff --git a/icefuzz/tests/rgba_drv_cbit/.gitignore b/icefuzz/tests/rgba_drv_cbit/.gitignore new file mode 100644 index 0000000..68b6394 --- /dev/null +++ b/icefuzz/tests/rgba_drv_cbit/.gitignore @@ -0,0 +1 @@ +work_rgba_drv/ \ No newline at end of file diff --git a/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py b/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py new file mode 100755 index 0000000..a7e2006 --- /dev/null +++ b/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py @@ -0,0 +1,174 @@ +#!/usr/bin/env python3 + +import os, sys +# SB_RGBA_DRV automatic fuzzing script + +device = "up5k" + +# SB_RGBA_DRV config bits to be fuzzed +# These must be in an order such that a config with bit i set doesn't set any other undiscovered bits yet + + +fuzz_bits = [ + "RGB0_CURRENT_0", + "RGB0_CURRENT_1", + "RGB0_CURRENT_2", + "RGB0_CURRENT_3", + "RGB0_CURRENT_4", + "RGB0_CURRENT_5", + + "RGB1_CURRENT_0", + "RGB1_CURRENT_1", + "RGB1_CURRENT_2", + "RGB1_CURRENT_3", + "RGB1_CURRENT_4", + "RGB1_CURRENT_5", + + "RGB2_CURRENT_0", + "RGB2_CURRENT_1", + "RGB2_CURRENT_2", + "RGB2_CURRENT_3", + "RGB2_CURRENT_4", + "RGB2_CURRENT_5", + + "CURRENT_MODE" +] + + +# Boilerplate code based on the icefuzz script +code_prefix = """ +module top( + input curren, + input rgbleden, + input r_in, + input g_in, + input b_in, + output r_led, + output g_led, + output b_led); +""" + +def get_param_value(param_name, param_size, fuzz_bit): + param = "\"0b"; + #In the RGB driver, once bit i of a current parameter is set i-1..0 must also be set + is_high = False + for i in range(param_size - 1, -1, -1): + if fuzz_bit == param_name + "_" + str(i) or (i == 0 and fuzz_bit == "CURRENT_MODE") or is_high: + param += '1' + is_high = True + else: + param += '0' + param += "\"" + return param +def inst_rgba(fuzz_bit): + v = "" + v += """SB_RGBA_DRV rgba_inst ( + .CURREN(curren), + .RGBLEDEN(rgbleden), + .RGB0PWM(r_in), + .RGB1PWM(g_in), + .RGB2PWM(b_in), + .RGB0(r_led), + .RGB1(g_led), + .RGB2(b_led) + );""" + + v += "defparam rgba_inst.CURRENT_MODE = " + get_param_value("CURRENT_MODE", 1, fuzz_bit) + ";\n" + v += "defparam rgba_inst.RGB0_CURRENT = " + get_param_value("RGB0_CURRENT", 6, fuzz_bit) + ";\n" + v += "defparam rgba_inst.RGB1_CURRENT = " + get_param_value("RGB1_CURRENT", 6, fuzz_bit) + ";\n" + v += "defparam rgba_inst.RGB2_CURRENT = " + get_param_value("RGB2_CURRENT", 6, fuzz_bit) + ";\n" + + return v; + +def make_vlog(fuzz_bit): + vlog = code_prefix + vlog += inst_rgba(fuzz_bit) + vlog += "endmodule" + return vlog + +known_bits = [] + +# Set to true to continue even if multiple bits are changed (needed because +# of the issue discusssed below) +show_all_bits = False #TODO: make this an argument + +device = "up5k" #TODO: environment variable? + +#HACK: icecube doesn't let you set all of the config bits to 0, +#which makes fuzzing early on annoying as there is never a case +#with just 1 bit set. So a tiny bit of semi-manual work is needed +#first to discover this (basically run this script with show_all_bits=True +#and look for the stuck bit) +#TODO: clever code could get rid of this +rgba_drv_en_bit = { + "up5k" : (0, 28, 5) +} + +#Return a list of RGBA_DRIVER config bits in the format (x, y, bit) +def parse_exp(expfile): + current_x = 0 + current_y = 0 + bits = [] + with open(expfile, 'r') as f: + for line in f: + splitline = line.split(' ') + if splitline[0].endswith("_tile"): + current_x = int(splitline[1]) + current_y = int(splitline[2]) + elif splitline[0] == "IpConfig": + if splitline[1][:5] == "CBIT_": + bitidx = int(splitline[1][5:]) + bits.append((current_x, current_y, bitidx)) + return bits + +#Convert a bit tuple as returned from the above to a nice string +def bit_to_str(bit): + return "(%d, %d, \"CBIT_%d\")" % bit + +#The main fuzzing function +def do_fuzz(): + if not os.path.exists("./work_rgba_drv"): + os.mkdir("./work_rgba_drv") + known_bits.append(rgba_drv_en_bit[device]) + with open("rgba_drv_data_" + device + ".txt", 'w') as dat: + for fuzz_bit in fuzz_bits: + vlog = make_vlog(fuzz_bit) + with open("./work_rgba_drv/rgba_drv.v", 'w') as f: + f.write(vlog) + with open("./work_rgba_drv/rgba_drv.pcf", 'w') as f: + f.write(""" +set_io r_led 39 +set_io g_led 40 +set_io b_led 41 + """) + retval = os.system("bash ../../icecube.sh -" + device + " ./work_rgba_drv/rgba_drv.v > ./work_rgba_drv/icecube.log 2>&1") + if retval != 0: + sys.stderr.write('ERROR: icecube returned non-zero error code\n') + sys.exit(1) + retval = os.system("../../../icebox/icebox_explain.py ./work_rgba_drv/rgba_drv.asc > ./work_rgba_drv/rgba_drv.exp") + if retval != 0: + sys.stderr.write('ERROR: icebox_explain returned non-zero error code\n') + sys.exit(1) + rgba_bits = parse_exp("./work_rgba_drv/rgba_drv.exp") + new_bits = [] + for set_bit in rgba_bits: + if not (set_bit in known_bits): + new_bits.append(set_bit) + if len(new_bits) == 0: + sys.stderr.write('ERROR: no new bits set when setting config bit ' + fuzz_bit + '\n') + sys.exit(1) + if len(new_bits) > 1: + sys.stderr.write('ERROR: multiple new bits set when setting config bit ' + fuzz_bit + '\n') + for bit in new_bits: + sys.stderr.write('\t' + bit_to_str(bit) + '\n') + if not show_all_bits: + sys.exit(1) + if len(new_bits) == 1: + known_bits.append(new_bits[0]) + #print DIVQ_0 at the right moment, as it's not fuzzed normally + if fuzz_bit == "RGB0_CURRENT_0": + print(("\"RGBA_DRV_EN\":").ljust(24) + bit_to_str(rgba_drv_en_bit[device]) + ",") + dat.write(("\"RGBA_DRV_EN\":").ljust(24) + bit_to_str(rgba_drv_en_bit[device]) + ",\n") + print(("\"" + fuzz_bit + "\":").ljust(24) + bit_to_str(new_bits[0]) + ",") + dat.write(("\"" + fuzz_bit + "\":").ljust(24) + bit_to_str(new_bits[0]) + ",\n") +do_fuzz() \ No newline at end of file diff --git a/icefuzz/tests/rgba_drv_cbit/rgba_drv_data_up5k.txt b/icefuzz/tests/rgba_drv_cbit/rgba_drv_data_up5k.txt new file mode 100644 index 0000000..73bfb90 --- /dev/null +++ b/icefuzz/tests/rgba_drv_cbit/rgba_drv_data_up5k.txt @@ -0,0 +1,20 @@ +"RGBA_DRV_EN": (0, 28, "CBIT_5"), +"RGB0_CURRENT_0": (0, 28, "CBIT_6"), +"RGB0_CURRENT_1": (0, 28, "CBIT_7"), +"RGB0_CURRENT_2": (0, 29, "CBIT_0"), +"RGB0_CURRENT_3": (0, 29, "CBIT_1"), +"RGB0_CURRENT_4": (0, 29, "CBIT_2"), +"RGB0_CURRENT_5": (0, 29, "CBIT_3"), +"RGB1_CURRENT_0": (0, 29, "CBIT_4"), +"RGB1_CURRENT_1": (0, 29, "CBIT_5"), +"RGB1_CURRENT_2": (0, 29, "CBIT_6"), +"RGB1_CURRENT_3": (0, 29, "CBIT_7"), +"RGB1_CURRENT_4": (0, 30, "CBIT_0"), +"RGB1_CURRENT_5": (0, 30, "CBIT_1"), +"RGB2_CURRENT_0": (0, 30, "CBIT_2"), +"RGB2_CURRENT_1": (0, 30, "CBIT_3"), +"RGB2_CURRENT_2": (0, 30, "CBIT_4"), +"RGB2_CURRENT_3": (0, 30, "CBIT_5"), +"RGB2_CURRENT_4": (0, 30, "CBIT_6"), +"RGB2_CURRENT_5": (0, 30, "CBIT_7"), +"CURRENT_MODE": (0, 28, "CBIT_4"), -- cgit v1.2.3 From afcc653b7882217d98aad95829256d65665f7c07 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 17 Nov 2017 14:29:00 +0000 Subject: Add support for UltraPlus SPRAM --- icebox/icebox.py | 243 +++++++++++++++++ icebox/icebox_chipdb.py | 12 +- icefuzz/tests/spram/fuzz_spram.py | 11 +- icefuzz/tests/spram/up5k_spram_data.txt | 468 ++++++++++++++++---------------- 4 files changed, 496 insertions(+), 238 deletions(-) (limited to 'icefuzz') diff --git a/icebox/icebox.py b/icebox/icebox.py index 40934f3..0a810e8 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -4438,6 +4438,249 @@ dsp_config_db = { } } +# SPRAM data for UltraPlus devices, use icefuzz/tests/fuzz_spram.py +# to generate this +spram_db = { + "5k" : { + (0, 0, 1): { + "ADDRESS_0": (0, 2, "lutff_0/in_1"), + "ADDRESS_10": (0, 2, "lutff_2/in_0"), + "ADDRESS_11": (0, 2, "lutff_3/in_0"), + "ADDRESS_12": (0, 2, "lutff_4/in_0"), + "ADDRESS_13": (0, 2, "lutff_5/in_0"), + "ADDRESS_1": (0, 2, "lutff_1/in_1"), + "ADDRESS_2": (0, 2, "lutff_2/in_1"), + "ADDRESS_3": (0, 2, "lutff_3/in_1"), + "ADDRESS_4": (0, 2, "lutff_4/in_1"), + "ADDRESS_5": (0, 2, "lutff_5/in_1"), + "ADDRESS_6": (0, 2, "lutff_6/in_1"), + "ADDRESS_7": (0, 2, "lutff_7/in_1"), + "ADDRESS_8": (0, 2, "lutff_0/in_0"), + "ADDRESS_9": (0, 2, "lutff_1/in_0"), + "CHIPSELECT": (0, 3, "lutff_6/in_1"), + "CLOCK": (0, 1, "clk"), + "DATAIN_0": (0, 1, "lutff_0/in_3"), + "DATAIN_10": (0, 1, "lutff_2/in_1"), + "DATAIN_11": (0, 1, "lutff_3/in_1"), + "DATAIN_12": (0, 1, "lutff_4/in_1"), + "DATAIN_13": (0, 1, "lutff_5/in_1"), + "DATAIN_14": (0, 1, "lutff_6/in_1"), + "DATAIN_15": (0, 1, "lutff_7/in_1"), + "DATAIN_1": (0, 1, "lutff_1/in_3"), + "DATAIN_2": (0, 1, "lutff_2/in_3"), + "DATAIN_3": (0, 1, "lutff_3/in_3"), + "DATAIN_4": (0, 1, "lutff_4/in_3"), + "DATAIN_5": (0, 1, "lutff_5/in_3"), + "DATAIN_6": (0, 1, "lutff_6/in_3"), + "DATAIN_7": (0, 1, "lutff_7/in_3"), + "DATAIN_8": (0, 1, "lutff_0/in_1"), + "DATAIN_9": (0, 1, "lutff_1/in_1"), + "DATAOUT_0": (0, 1, "slf_op_0"), + "DATAOUT_10": (0, 2, "slf_op_2"), + "DATAOUT_11": (0, 2, "slf_op_3"), + "DATAOUT_12": (0, 2, "slf_op_4"), + "DATAOUT_13": (0, 2, "slf_op_5"), + "DATAOUT_14": (0, 2, "slf_op_6"), + "DATAOUT_15": (0, 2, "slf_op_7"), + "DATAOUT_1": (0, 1, "slf_op_1"), + "DATAOUT_2": (0, 1, "slf_op_2"), + "DATAOUT_3": (0, 1, "slf_op_3"), + "DATAOUT_4": (0, 1, "slf_op_4"), + "DATAOUT_5": (0, 1, "slf_op_5"), + "DATAOUT_6": (0, 1, "slf_op_6"), + "DATAOUT_7": (0, 1, "slf_op_7"), + "DATAOUT_8": (0, 2, "slf_op_0"), + "DATAOUT_9": (0, 2, "slf_op_1"), + "MASKWREN_0": (0, 3, "lutff_0/in_0"), + "MASKWREN_1": (0, 3, "lutff_1/in_0"), + "MASKWREN_2": (0, 3, "lutff_2/in_0"), + "MASKWREN_3": (0, 3, "lutff_3/in_0"), + "POWEROFF": (0, 4, "lutff_4/in_3"), + "SLEEP": (0, 4, "lutff_2/in_3"), + "SPRAM_EN": (0, 1, "CBIT_0"), + "STANDBY": (0, 4, "lutff_0/in_3"), + "WREN": (0, 3, "lutff_4/in_1"), + }, + (0, 0, 2): { + "ADDRESS_0": (0, 2, "lutff_6/in_0"), + "ADDRESS_10": (0, 3, "lutff_0/in_1"), + "ADDRESS_11": (0, 3, "lutff_1/in_1"), + "ADDRESS_12": (0, 3, "lutff_2/in_1"), + "ADDRESS_13": (0, 3, "lutff_3/in_1"), + "ADDRESS_1": (0, 2, "lutff_7/in_0"), + "ADDRESS_2": (0, 3, "lutff_0/in_3"), + "ADDRESS_3": (0, 3, "lutff_1/in_3"), + "ADDRESS_4": (0, 3, "lutff_2/in_3"), + "ADDRESS_5": (0, 3, "lutff_3/in_3"), + "ADDRESS_6": (0, 3, "lutff_4/in_3"), + "ADDRESS_7": (0, 3, "lutff_5/in_3"), + "ADDRESS_8": (0, 3, "lutff_6/in_3"), + "ADDRESS_9": (0, 3, "lutff_7/in_3"), + "CHIPSELECT": (0, 3, "lutff_7/in_1"), + "CLOCK": (0, 2, "clk"), + "DATAIN_0": (0, 1, "lutff_0/in_0"), + "DATAIN_10": (0, 2, "lutff_2/in_3"), + "DATAIN_11": (0, 2, "lutff_3/in_3"), + "DATAIN_12": (0, 2, "lutff_4/in_3"), + "DATAIN_13": (0, 2, "lutff_5/in_3"), + "DATAIN_14": (0, 2, "lutff_6/in_3"), + "DATAIN_15": (0, 2, "lutff_7/in_3"), + "DATAIN_1": (0, 1, "lutff_1/in_0"), + "DATAIN_2": (0, 1, "lutff_2/in_0"), + "DATAIN_3": (0, 1, "lutff_3/in_0"), + "DATAIN_4": (0, 1, "lutff_4/in_0"), + "DATAIN_5": (0, 1, "lutff_5/in_0"), + "DATAIN_6": (0, 1, "lutff_6/in_0"), + "DATAIN_7": (0, 1, "lutff_7/in_0"), + "DATAIN_8": (0, 2, "lutff_0/in_3"), + "DATAIN_9": (0, 2, "lutff_1/in_3"), + "DATAOUT_0": (0, 3, "slf_op_0"), + "DATAOUT_10": (0, 4, "slf_op_2"), + "DATAOUT_11": (0, 4, "slf_op_3"), + "DATAOUT_12": (0, 4, "slf_op_4"), + "DATAOUT_13": (0, 4, "slf_op_5"), + "DATAOUT_14": (0, 4, "slf_op_6"), + "DATAOUT_15": (0, 4, "slf_op_7"), + "DATAOUT_1": (0, 3, "slf_op_1"), + "DATAOUT_2": (0, 3, "slf_op_2"), + "DATAOUT_3": (0, 3, "slf_op_3"), + "DATAOUT_4": (0, 3, "slf_op_4"), + "DATAOUT_5": (0, 3, "slf_op_5"), + "DATAOUT_6": (0, 3, "slf_op_6"), + "DATAOUT_7": (0, 3, "slf_op_7"), + "DATAOUT_8": (0, 4, "slf_op_0"), + "DATAOUT_9": (0, 4, "slf_op_1"), + "MASKWREN_0": (0, 3, "lutff_4/in_0"), + "MASKWREN_1": (0, 3, "lutff_5/in_0"), + "MASKWREN_2": (0, 3, "lutff_6/in_0"), + "MASKWREN_3": (0, 3, "lutff_7/in_0"), + "POWEROFF": (0, 4, "lutff_5/in_3"), + "SLEEP": (0, 4, "lutff_3/in_3"), + "SPRAM_EN": (0, 1, "CBIT_1"), + "STANDBY": (0, 4, "lutff_1/in_3"), + "WREN": (0, 3, "lutff_5/in_1"), + }, + (25, 0, 3): { + "ADDRESS_0": (25, 2, "lutff_0/in_1"), + "ADDRESS_10": (25, 2, "lutff_2/in_0"), + "ADDRESS_11": (25, 2, "lutff_3/in_0"), + "ADDRESS_12": (25, 2, "lutff_4/in_0"), + "ADDRESS_13": (25, 2, "lutff_5/in_0"), + "ADDRESS_1": (25, 2, "lutff_1/in_1"), + "ADDRESS_2": (25, 2, "lutff_2/in_1"), + "ADDRESS_3": (25, 2, "lutff_3/in_1"), + "ADDRESS_4": (25, 2, "lutff_4/in_1"), + "ADDRESS_5": (25, 2, "lutff_5/in_1"), + "ADDRESS_6": (25, 2, "lutff_6/in_1"), + "ADDRESS_7": (25, 2, "lutff_7/in_1"), + "ADDRESS_8": (25, 2, "lutff_0/in_0"), + "ADDRESS_9": (25, 2, "lutff_1/in_0"), + "CHIPSELECT": (25, 3, "lutff_6/in_1"), + "CLOCK": (25, 1, "clk"), + "DATAIN_0": (25, 1, "lutff_0/in_3"), + "DATAIN_10": (25, 1, "lutff_2/in_1"), + "DATAIN_11": (25, 1, "lutff_3/in_1"), + "DATAIN_12": (25, 1, "lutff_4/in_1"), + "DATAIN_13": (25, 1, "lutff_5/in_1"), + "DATAIN_14": (25, 1, "lutff_6/in_1"), + "DATAIN_15": (25, 1, "lutff_7/in_1"), + "DATAIN_1": (25, 1, "lutff_1/in_3"), + "DATAIN_2": (25, 1, "lutff_2/in_3"), + "DATAIN_3": (25, 1, "lutff_3/in_3"), + "DATAIN_4": (25, 1, "lutff_4/in_3"), + "DATAIN_5": (25, 1, "lutff_5/in_3"), + "DATAIN_6": (25, 1, "lutff_6/in_3"), + "DATAIN_7": (25, 1, "lutff_7/in_3"), + "DATAIN_8": (25, 1, "lutff_0/in_1"), + "DATAIN_9": (25, 1, "lutff_1/in_1"), + "DATAOUT_0": (25, 1, "slf_op_0"), + "DATAOUT_10": (25, 2, "slf_op_2"), + "DATAOUT_11": (25, 2, "slf_op_3"), + "DATAOUT_12": (25, 2, "slf_op_4"), + "DATAOUT_13": (25, 2, "slf_op_5"), + "DATAOUT_14": (25, 2, "slf_op_6"), + "DATAOUT_15": (25, 2, "slf_op_7"), + "DATAOUT_1": (25, 1, "slf_op_1"), + "DATAOUT_2": (25, 1, "slf_op_2"), + "DATAOUT_3": (25, 1, "slf_op_3"), + "DATAOUT_4": (25, 1, "slf_op_4"), + "DATAOUT_5": (25, 1, "slf_op_5"), + "DATAOUT_6": (25, 1, "slf_op_6"), + "DATAOUT_7": (25, 1, "slf_op_7"), + "DATAOUT_8": (25, 2, "slf_op_0"), + "DATAOUT_9": (25, 2, "slf_op_1"), + "MASKWREN_0": (25, 3, "lutff_0/in_0"), + "MASKWREN_1": (25, 3, "lutff_1/in_0"), + "MASKWREN_2": (25, 3, "lutff_2/in_0"), + "MASKWREN_3": (25, 3, "lutff_3/in_0"), + "POWEROFF": (25, 4, "lutff_4/in_3"), + "SLEEP": (25, 4, "lutff_2/in_3"), + "SPRAM_EN": (25, 1, "CBIT_0"), + "STANDBY": (25, 4, "lutff_0/in_3"), + "WREN": (25, 3, "lutff_4/in_1"), + }, + (25, 0, 4): { + "ADDRESS_0": (25, 2, "lutff_6/in_0"), + "ADDRESS_10": (25, 3, "lutff_0/in_1"), + "ADDRESS_11": (25, 3, "lutff_1/in_1"), + "ADDRESS_12": (25, 3, "lutff_2/in_1"), + "ADDRESS_13": (25, 3, "lutff_3/in_1"), + "ADDRESS_1": (25, 2, "lutff_7/in_0"), + "ADDRESS_2": (25, 3, "lutff_0/in_3"), + "ADDRESS_3": (25, 3, "lutff_1/in_3"), + "ADDRESS_4": (25, 3, "lutff_2/in_3"), + "ADDRESS_5": (25, 3, "lutff_3/in_3"), + "ADDRESS_6": (25, 3, "lutff_4/in_3"), + "ADDRESS_7": (25, 3, "lutff_5/in_3"), + "ADDRESS_8": (25, 3, "lutff_6/in_3"), + "ADDRESS_9": (25, 3, "lutff_7/in_3"), + "CHIPSELECT": (25, 3, "lutff_7/in_1"), + "CLOCK": (25, 2, "clk"), + "DATAIN_0": (25, 1, "lutff_0/in_0"), + "DATAIN_10": (25, 2, "lutff_2/in_3"), + "DATAIN_11": (25, 2, "lutff_3/in_3"), + "DATAIN_12": (25, 2, "lutff_4/in_3"), + "DATAIN_13": (25, 2, "lutff_5/in_3"), + "DATAIN_14": (25, 2, "lutff_6/in_3"), + "DATAIN_15": (25, 2, "lutff_7/in_3"), + "DATAIN_1": (25, 1, "lutff_1/in_0"), + "DATAIN_2": (25, 1, "lutff_2/in_0"), + "DATAIN_3": (25, 1, "lutff_3/in_0"), + "DATAIN_4": (25, 1, "lutff_4/in_0"), + "DATAIN_5": (25, 1, "lutff_5/in_0"), + "DATAIN_6": (25, 1, "lutff_6/in_0"), + "DATAIN_7": (25, 1, "lutff_7/in_0"), + "DATAIN_8": (25, 2, "lutff_0/in_3"), + "DATAIN_9": (25, 2, "lutff_1/in_3"), + "DATAOUT_0": (25, 3, "slf_op_0"), + "DATAOUT_10": (25, 4, "slf_op_2"), + "DATAOUT_11": (25, 4, "slf_op_3"), + "DATAOUT_12": (25, 4, "slf_op_4"), + "DATAOUT_13": (25, 4, "slf_op_5"), + "DATAOUT_14": (25, 4, "slf_op_6"), + "DATAOUT_15": (25, 4, "slf_op_7"), + "DATAOUT_1": (25, 3, "slf_op_1"), + "DATAOUT_2": (25, 3, "slf_op_2"), + "DATAOUT_3": (25, 3, "slf_op_3"), + "DATAOUT_4": (25, 3, "slf_op_4"), + "DATAOUT_5": (25, 3, "slf_op_5"), + "DATAOUT_6": (25, 3, "slf_op_6"), + "DATAOUT_7": (25, 3, "slf_op_7"), + "DATAOUT_8": (25, 4, "slf_op_0"), + "DATAOUT_9": (25, 4, "slf_op_1"), + "MASKWREN_0": (25, 3, "lutff_4/in_0"), + "MASKWREN_1": (25, 3, "lutff_5/in_0"), + "MASKWREN_2": (25, 3, "lutff_6/in_0"), + "MASKWREN_3": (25, 3, "lutff_7/in_0"), + "POWEROFF": (25, 4, "lutff_5/in_3"), + "SLEEP": (25, 4, "lutff_3/in_3"), + "SPRAM_EN": (25, 1, "CBIT_1"), + "STANDBY": (25, 4, "lutff_1/in_3"), + "WREN": (25, 3, "lutff_5/in_1"), + } + } +} + # This contains the data for extra cells not included # in any previous databases diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py index 9a7b531..520d884 100755 --- a/icebox/icebox_chipdb.py +++ b/icebox/icebox_chipdb.py @@ -325,7 +325,17 @@ if ic.device in icebox.extra_cells_db: for key in sorted(cellinfo): print("%s %s" % (key, " ".join([str(k) for k in cellinfo[key]]))) print() - + +if ic.device in icebox.spram_db: + for cell in icebox.spram_db[ic.device]: + loc = cell + x, y, z = loc + print(".extra_cell %d %d %d SPRAM" % (x, y, z)) + cellinfo = icebox.spram_db[ic.device][cell] + for key in sorted(cellinfo): + print("%s %s" % (key, " ".join([str(k) for k in cellinfo[key]]))) + print() + print(".extra_bits") extra_bits = dict() for idx in sorted(ic.extra_bits_db()): diff --git a/icefuzz/tests/spram/fuzz_spram.py b/icefuzz/tests/spram/fuzz_spram.py index 33e62cb..a92a361 100755 --- a/icefuzz/tests/spram/fuzz_spram.py +++ b/icefuzz/tests/spram/fuzz_spram.py @@ -77,7 +77,7 @@ for loc in spram_locs: net_map = {} for sig in spram_signals: net_map[sig] = set() - net_map["C_SPRAM_EN"] = set() # actually a CBIT not a net + net_map["SPRAM_EN"] = set() # actually a CBIT not a net for n in fuzz_options: with open("./work_spram/spram.v","w") as f: @@ -159,15 +159,16 @@ for loc in spram_locs: bits = [] with open("./work_spram/spram.exp", "r") as f: bits = parse_exp(f) - net_map["C_SPRAM_EN"].update(bits) + net_map["SPRAM_EN"].update(bits) spram_data[loc] = net_map with open(device + "_spram_data.txt", "w") as f: for loc in spram_data: - print("SPRAM %d %d %d" % loc, file=f) + print("\t(%d, %d, %d): {" % loc, file=f) data = spram_data[loc] for net in sorted(data): cnets = [] for cnet in data[net]: - cnets.append("(%d, %d, %s)" % cnet) - print("\t%s: %s" % (net, " ".join(cnets)), file=f) \ No newline at end of file + cnets.append("(%d, %d, \"%s\")" % cnet) + print("\t\t%s %s, " % (("\"" + net.replace("[","_").replace("]","") + "\":").ljust(24), " ".join(cnets)), file=f) + print("\t},", file=f) \ No newline at end of file diff --git a/icefuzz/tests/spram/up5k_spram_data.txt b/icefuzz/tests/spram/up5k_spram_data.txt index c824e73..4526f93 100644 --- a/icefuzz/tests/spram/up5k_spram_data.txt +++ b/icefuzz/tests/spram/up5k_spram_data.txt @@ -1,232 +1,236 @@ -SPRAM 0 0 1 - ADDRESS[0]: (0, 2, lutff_0/in_1) - ADDRESS[10]: (0, 2, lutff_2/in_0) - ADDRESS[11]: (0, 2, lutff_3/in_0) - ADDRESS[12]: (0, 2, lutff_4/in_0) - ADDRESS[13]: (0, 2, lutff_5/in_0) - ADDRESS[1]: (0, 2, lutff_1/in_1) - ADDRESS[2]: (0, 2, lutff_2/in_1) - ADDRESS[3]: (0, 2, lutff_3/in_1) - ADDRESS[4]: (0, 2, lutff_4/in_1) - ADDRESS[5]: (0, 2, lutff_5/in_1) - ADDRESS[6]: (0, 2, lutff_6/in_1) - ADDRESS[7]: (0, 2, lutff_7/in_1) - ADDRESS[8]: (0, 2, lutff_0/in_0) - ADDRESS[9]: (0, 2, lutff_1/in_0) - CHIPSELECT: (0, 3, lutff_6/in_1) - CLOCK: (0, 1, clk) - C_SPRAM_EN: (0, 1, CBIT_0) - DATAIN[0]: (0, 1, lutff_0/in_3) - DATAIN[10]: (0, 1, lutff_2/in_1) - DATAIN[11]: (0, 1, lutff_3/in_1) - DATAIN[12]: (0, 1, lutff_4/in_1) - DATAIN[13]: (0, 1, lutff_5/in_1) - DATAIN[14]: (0, 1, lutff_6/in_1) - DATAIN[15]: (0, 1, lutff_7/in_1) - DATAIN[1]: (0, 1, lutff_1/in_3) - DATAIN[2]: (0, 1, lutff_2/in_3) - DATAIN[3]: (0, 1, lutff_3/in_3) - DATAIN[4]: (0, 1, lutff_4/in_3) - DATAIN[5]: (0, 1, lutff_5/in_3) - DATAIN[6]: (0, 1, lutff_6/in_3) - DATAIN[7]: (0, 1, lutff_7/in_3) - DATAIN[8]: (0, 1, lutff_0/in_1) - DATAIN[9]: (0, 1, lutff_1/in_1) - DATAOUT[0]: (0, 1, slf_op_0) - DATAOUT[10]: (0, 2, slf_op_2) - DATAOUT[11]: (0, 2, slf_op_3) - DATAOUT[12]: (0, 2, slf_op_4) - DATAOUT[13]: (0, 2, slf_op_5) - DATAOUT[14]: (0, 2, slf_op_6) - DATAOUT[15]: (0, 2, slf_op_7) - DATAOUT[1]: (0, 1, slf_op_1) - DATAOUT[2]: (0, 1, slf_op_2) - DATAOUT[3]: (0, 1, slf_op_3) - DATAOUT[4]: (0, 1, slf_op_4) - DATAOUT[5]: (0, 1, slf_op_5) - DATAOUT[6]: (0, 1, slf_op_6) - DATAOUT[7]: (0, 1, slf_op_7) - DATAOUT[8]: (0, 2, slf_op_0) - DATAOUT[9]: (0, 2, slf_op_1) - MASKWREN[0]: (0, 3, lutff_0/in_0) - MASKWREN[1]: (0, 3, lutff_1/in_0) - MASKWREN[2]: (0, 3, lutff_2/in_0) - MASKWREN[3]: (0, 3, lutff_3/in_0) - POWEROFF: (0, 4, lutff_4/in_3) - SLEEP: (0, 4, lutff_2/in_3) - STANDBY: (0, 4, lutff_0/in_3) - WREN: (0, 3, lutff_4/in_1) -SPRAM 0 0 2 - ADDRESS[0]: (0, 2, lutff_6/in_0) - ADDRESS[10]: (0, 3, lutff_0/in_1) - ADDRESS[11]: (0, 3, lutff_1/in_1) - ADDRESS[12]: (0, 3, lutff_2/in_1) - ADDRESS[13]: (0, 3, lutff_3/in_1) - ADDRESS[1]: (0, 2, lutff_7/in_0) - ADDRESS[2]: (0, 3, lutff_0/in_3) - ADDRESS[3]: (0, 3, lutff_1/in_3) - ADDRESS[4]: (0, 3, lutff_2/in_3) - ADDRESS[5]: (0, 3, lutff_3/in_3) - ADDRESS[6]: (0, 3, lutff_4/in_3) - ADDRESS[7]: (0, 3, lutff_5/in_3) - ADDRESS[8]: (0, 3, lutff_6/in_3) - ADDRESS[9]: (0, 3, lutff_7/in_3) - CHIPSELECT: (0, 3, lutff_7/in_1) - CLOCK: (0, 2, clk) - C_SPRAM_EN: (0, 1, CBIT_1) - DATAIN[0]: (0, 1, lutff_0/in_0) - DATAIN[10]: (0, 2, lutff_2/in_3) - DATAIN[11]: (0, 2, lutff_3/in_3) - DATAIN[12]: (0, 2, lutff_4/in_3) - DATAIN[13]: (0, 2, lutff_5/in_3) - DATAIN[14]: (0, 2, lutff_6/in_3) - DATAIN[15]: (0, 2, lutff_7/in_3) - DATAIN[1]: (0, 1, lutff_1/in_0) - DATAIN[2]: (0, 1, lutff_2/in_0) - DATAIN[3]: (0, 1, lutff_3/in_0) - DATAIN[4]: (0, 1, lutff_4/in_0) - DATAIN[5]: (0, 1, lutff_5/in_0) - DATAIN[6]: (0, 1, lutff_6/in_0) - DATAIN[7]: (0, 1, lutff_7/in_0) - DATAIN[8]: (0, 2, lutff_0/in_3) - DATAIN[9]: (0, 2, lutff_1/in_3) - DATAOUT[0]: (0, 3, slf_op_0) - DATAOUT[10]: (0, 4, slf_op_2) - DATAOUT[11]: (0, 4, slf_op_3) - DATAOUT[12]: (0, 4, slf_op_4) - DATAOUT[13]: (0, 4, slf_op_5) - DATAOUT[14]: (0, 4, slf_op_6) - DATAOUT[15]: (0, 4, slf_op_7) - DATAOUT[1]: (0, 3, slf_op_1) - DATAOUT[2]: (0, 3, slf_op_2) - DATAOUT[3]: (0, 3, slf_op_3) - DATAOUT[4]: (0, 3, slf_op_4) - DATAOUT[5]: (0, 3, slf_op_5) - DATAOUT[6]: (0, 3, slf_op_6) - DATAOUT[7]: (0, 3, slf_op_7) - DATAOUT[8]: (0, 4, slf_op_0) - DATAOUT[9]: (0, 4, slf_op_1) - MASKWREN[0]: (0, 3, lutff_4/in_0) - MASKWREN[1]: (0, 3, lutff_5/in_0) - MASKWREN[2]: (0, 3, lutff_6/in_0) - MASKWREN[3]: (0, 3, lutff_7/in_0) - POWEROFF: (0, 4, lutff_5/in_3) - SLEEP: (0, 4, lutff_3/in_3) - STANDBY: (0, 4, lutff_1/in_3) - WREN: (0, 3, lutff_5/in_1) -SPRAM 25 0 3 - ADDRESS[0]: (25, 2, lutff_0/in_1) - ADDRESS[10]: (25, 2, lutff_2/in_0) - ADDRESS[11]: (25, 2, lutff_3/in_0) - ADDRESS[12]: (25, 2, lutff_4/in_0) - ADDRESS[13]: (25, 2, lutff_5/in_0) - ADDRESS[1]: (25, 2, lutff_1/in_1) - ADDRESS[2]: (25, 2, lutff_2/in_1) - ADDRESS[3]: (25, 2, lutff_3/in_1) - ADDRESS[4]: (25, 2, lutff_4/in_1) - ADDRESS[5]: (25, 2, lutff_5/in_1) - ADDRESS[6]: (25, 2, lutff_6/in_1) - ADDRESS[7]: (25, 2, lutff_7/in_1) - ADDRESS[8]: (25, 2, lutff_0/in_0) - ADDRESS[9]: (25, 2, lutff_1/in_0) - CHIPSELECT: (25, 3, lutff_6/in_1) - CLOCK: (25, 1, clk) - C_SPRAM_EN: (25, 1, CBIT_0) - DATAIN[0]: (25, 1, lutff_0/in_3) - DATAIN[10]: (25, 1, lutff_2/in_1) - DATAIN[11]: (25, 1, lutff_3/in_1) - DATAIN[12]: (25, 1, lutff_4/in_1) - DATAIN[13]: (25, 1, lutff_5/in_1) - DATAIN[14]: (25, 1, lutff_6/in_1) - DATAIN[15]: (25, 1, lutff_7/in_1) - DATAIN[1]: (25, 1, lutff_1/in_3) - DATAIN[2]: (25, 1, lutff_2/in_3) - DATAIN[3]: (25, 1, lutff_3/in_3) - DATAIN[4]: (25, 1, lutff_4/in_3) - DATAIN[5]: (25, 1, lutff_5/in_3) - DATAIN[6]: (25, 1, lutff_6/in_3) - DATAIN[7]: (25, 1, lutff_7/in_3) - DATAIN[8]: (25, 1, lutff_0/in_1) - DATAIN[9]: (25, 1, lutff_1/in_1) - DATAOUT[0]: (25, 1, slf_op_0) - DATAOUT[10]: (25, 2, slf_op_2) - DATAOUT[11]: (25, 2, slf_op_3) - DATAOUT[12]: (25, 2, slf_op_4) - DATAOUT[13]: (25, 2, slf_op_5) - DATAOUT[14]: (25, 2, slf_op_6) - DATAOUT[15]: (25, 2, slf_op_7) - DATAOUT[1]: (25, 1, slf_op_1) - DATAOUT[2]: (25, 1, slf_op_2) - DATAOUT[3]: (25, 1, slf_op_3) - DATAOUT[4]: (25, 1, slf_op_4) - DATAOUT[5]: (25, 1, slf_op_5) - DATAOUT[6]: (25, 1, slf_op_6) - DATAOUT[7]: (25, 1, slf_op_7) - DATAOUT[8]: (25, 2, slf_op_0) - DATAOUT[9]: (25, 2, slf_op_1) - MASKWREN[0]: (25, 3, lutff_0/in_0) - MASKWREN[1]: (25, 3, lutff_1/in_0) - MASKWREN[2]: (25, 3, lutff_2/in_0) - MASKWREN[3]: (25, 3, lutff_3/in_0) - POWEROFF: (25, 4, lutff_4/in_3) - SLEEP: (25, 4, lutff_2/in_3) - STANDBY: (25, 4, lutff_0/in_3) - WREN: (25, 3, lutff_4/in_1) -SPRAM 25 0 4 - ADDRESS[0]: (25, 2, lutff_6/in_0) - ADDRESS[10]: (25, 3, lutff_0/in_1) - ADDRESS[11]: (25, 3, lutff_1/in_1) - ADDRESS[12]: (25, 3, lutff_2/in_1) - ADDRESS[13]: (25, 3, lutff_3/in_1) - ADDRESS[1]: (25, 2, lutff_7/in_0) - ADDRESS[2]: (25, 3, lutff_0/in_3) - ADDRESS[3]: (25, 3, lutff_1/in_3) - ADDRESS[4]: (25, 3, lutff_2/in_3) - ADDRESS[5]: (25, 3, lutff_3/in_3) - ADDRESS[6]: (25, 3, lutff_4/in_3) - ADDRESS[7]: (25, 3, lutff_5/in_3) - ADDRESS[8]: (25, 3, lutff_6/in_3) - ADDRESS[9]: (25, 3, lutff_7/in_3) - CHIPSELECT: (25, 3, lutff_7/in_1) - CLOCK: (25, 2, clk) - C_SPRAM_EN: (25, 1, CBIT_1) - DATAIN[0]: (25, 1, lutff_0/in_0) - DATAIN[10]: (25, 2, lutff_2/in_3) - DATAIN[11]: (25, 2, lutff_3/in_3) - DATAIN[12]: (25, 2, lutff_4/in_3) - DATAIN[13]: (25, 2, lutff_5/in_3) - DATAIN[14]: (25, 2, lutff_6/in_3) - DATAIN[15]: (25, 2, lutff_7/in_3) - DATAIN[1]: (25, 1, lutff_1/in_0) - DATAIN[2]: (25, 1, lutff_2/in_0) - DATAIN[3]: (25, 1, lutff_3/in_0) - DATAIN[4]: (25, 1, lutff_4/in_0) - DATAIN[5]: (25, 1, lutff_5/in_0) - DATAIN[6]: (25, 1, lutff_6/in_0) - DATAIN[7]: (25, 1, lutff_7/in_0) - DATAIN[8]: (25, 2, lutff_0/in_3) - DATAIN[9]: (25, 2, lutff_1/in_3) - DATAOUT[0]: (25, 3, slf_op_0) - DATAOUT[10]: (25, 4, slf_op_2) - DATAOUT[11]: (25, 4, slf_op_3) - DATAOUT[12]: (25, 4, slf_op_4) - DATAOUT[13]: (25, 4, slf_op_5) - DATAOUT[14]: (25, 4, slf_op_6) - DATAOUT[15]: (25, 4, slf_op_7) - DATAOUT[1]: (25, 3, slf_op_1) - DATAOUT[2]: (25, 3, slf_op_2) - DATAOUT[3]: (25, 3, slf_op_3) - DATAOUT[4]: (25, 3, slf_op_4) - DATAOUT[5]: (25, 3, slf_op_5) - DATAOUT[6]: (25, 3, slf_op_6) - DATAOUT[7]: (25, 3, slf_op_7) - DATAOUT[8]: (25, 4, slf_op_0) - DATAOUT[9]: (25, 4, slf_op_1) - MASKWREN[0]: (25, 3, lutff_4/in_0) - MASKWREN[1]: (25, 3, lutff_5/in_0) - MASKWREN[2]: (25, 3, lutff_6/in_0) - MASKWREN[3]: (25, 3, lutff_7/in_0) - POWEROFF: (25, 4, lutff_5/in_3) - SLEEP: (25, 4, lutff_3/in_3) - STANDBY: (25, 4, lutff_1/in_3) - WREN: (25, 3, lutff_5/in_1) + (0, 0, 1): { + "ADDRESS_0": (0, 2, "lutff_0/in_1"), + "ADDRESS_10": (0, 2, "lutff_2/in_0"), + "ADDRESS_11": (0, 2, "lutff_3/in_0"), + "ADDRESS_12": (0, 2, "lutff_4/in_0"), + "ADDRESS_13": (0, 2, "lutff_5/in_0"), + "ADDRESS_1": (0, 2, "lutff_1/in_1"), + "ADDRESS_2": (0, 2, "lutff_2/in_1"), + "ADDRESS_3": (0, 2, "lutff_3/in_1"), + "ADDRESS_4": (0, 2, "lutff_4/in_1"), + "ADDRESS_5": (0, 2, "lutff_5/in_1"), + "ADDRESS_6": (0, 2, "lutff_6/in_1"), + "ADDRESS_7": (0, 2, "lutff_7/in_1"), + "ADDRESS_8": (0, 2, "lutff_0/in_0"), + "ADDRESS_9": (0, 2, "lutff_1/in_0"), + "CHIPSELECT": (0, 3, "lutff_6/in_1"), + "CLOCK": (0, 1, "clk"), + "DATAIN_0": (0, 1, "lutff_0/in_3"), + "DATAIN_10": (0, 1, "lutff_2/in_1"), + "DATAIN_11": (0, 1, "lutff_3/in_1"), + "DATAIN_12": (0, 1, "lutff_4/in_1"), + "DATAIN_13": (0, 1, "lutff_5/in_1"), + "DATAIN_14": (0, 1, "lutff_6/in_1"), + "DATAIN_15": (0, 1, "lutff_7/in_1"), + "DATAIN_1": (0, 1, "lutff_1/in_3"), + "DATAIN_2": (0, 1, "lutff_2/in_3"), + "DATAIN_3": (0, 1, "lutff_3/in_3"), + "DATAIN_4": (0, 1, "lutff_4/in_3"), + "DATAIN_5": (0, 1, "lutff_5/in_3"), + "DATAIN_6": (0, 1, "lutff_6/in_3"), + "DATAIN_7": (0, 1, "lutff_7/in_3"), + "DATAIN_8": (0, 1, "lutff_0/in_1"), + "DATAIN_9": (0, 1, "lutff_1/in_1"), + "DATAOUT_0": (0, 1, "slf_op_0"), + "DATAOUT_10": (0, 2, "slf_op_2"), + "DATAOUT_11": (0, 2, "slf_op_3"), + "DATAOUT_12": (0, 2, "slf_op_4"), + "DATAOUT_13": (0, 2, "slf_op_5"), + "DATAOUT_14": (0, 2, "slf_op_6"), + "DATAOUT_15": (0, 2, "slf_op_7"), + "DATAOUT_1": (0, 1, "slf_op_1"), + "DATAOUT_2": (0, 1, "slf_op_2"), + "DATAOUT_3": (0, 1, "slf_op_3"), + "DATAOUT_4": (0, 1, "slf_op_4"), + "DATAOUT_5": (0, 1, "slf_op_5"), + "DATAOUT_6": (0, 1, "slf_op_6"), + "DATAOUT_7": (0, 1, "slf_op_7"), + "DATAOUT_8": (0, 2, "slf_op_0"), + "DATAOUT_9": (0, 2, "slf_op_1"), + "MASKWREN_0": (0, 3, "lutff_0/in_0"), + "MASKWREN_1": (0, 3, "lutff_1/in_0"), + "MASKWREN_2": (0, 3, "lutff_2/in_0"), + "MASKWREN_3": (0, 3, "lutff_3/in_0"), + "POWEROFF": (0, 4, "lutff_4/in_3"), + "SLEEP": (0, 4, "lutff_2/in_3"), + "SPRAM_EN": (0, 1, "CBIT_0"), + "STANDBY": (0, 4, "lutff_0/in_3"), + "WREN": (0, 3, "lutff_4/in_1"), + }, + (0, 0, 2): { + "ADDRESS_0": (0, 2, "lutff_6/in_0"), + "ADDRESS_10": (0, 3, "lutff_0/in_1"), + "ADDRESS_11": (0, 3, "lutff_1/in_1"), + "ADDRESS_12": (0, 3, "lutff_2/in_1"), + "ADDRESS_13": (0, 3, "lutff_3/in_1"), + "ADDRESS_1": (0, 2, "lutff_7/in_0"), + "ADDRESS_2": (0, 3, "lutff_0/in_3"), + "ADDRESS_3": (0, 3, "lutff_1/in_3"), + "ADDRESS_4": (0, 3, "lutff_2/in_3"), + "ADDRESS_5": (0, 3, "lutff_3/in_3"), + "ADDRESS_6": (0, 3, "lutff_4/in_3"), + "ADDRESS_7": (0, 3, "lutff_5/in_3"), + "ADDRESS_8": (0, 3, "lutff_6/in_3"), + "ADDRESS_9": (0, 3, "lutff_7/in_3"), + "CHIPSELECT": (0, 3, "lutff_7/in_1"), + "CLOCK": (0, 2, "clk"), + "DATAIN_0": (0, 1, "lutff_0/in_0"), + "DATAIN_10": (0, 2, "lutff_2/in_3"), + "DATAIN_11": (0, 2, "lutff_3/in_3"), + "DATAIN_12": (0, 2, "lutff_4/in_3"), + "DATAIN_13": (0, 2, "lutff_5/in_3"), + "DATAIN_14": (0, 2, "lutff_6/in_3"), + "DATAIN_15": (0, 2, "lutff_7/in_3"), + "DATAIN_1": (0, 1, "lutff_1/in_0"), + "DATAIN_2": (0, 1, "lutff_2/in_0"), + "DATAIN_3": (0, 1, "lutff_3/in_0"), + "DATAIN_4": (0, 1, "lutff_4/in_0"), + "DATAIN_5": (0, 1, "lutff_5/in_0"), + "DATAIN_6": (0, 1, "lutff_6/in_0"), + "DATAIN_7": (0, 1, "lutff_7/in_0"), + "DATAIN_8": (0, 2, "lutff_0/in_3"), + "DATAIN_9": (0, 2, "lutff_1/in_3"), + "DATAOUT_0": (0, 3, "slf_op_0"), + "DATAOUT_10": (0, 4, "slf_op_2"), + "DATAOUT_11": (0, 4, "slf_op_3"), + "DATAOUT_12": (0, 4, "slf_op_4"), + "DATAOUT_13": (0, 4, "slf_op_5"), + "DATAOUT_14": (0, 4, "slf_op_6"), + "DATAOUT_15": (0, 4, "slf_op_7"), + "DATAOUT_1": (0, 3, "slf_op_1"), + "DATAOUT_2": (0, 3, "slf_op_2"), + "DATAOUT_3": (0, 3, "slf_op_3"), + "DATAOUT_4": (0, 3, "slf_op_4"), + "DATAOUT_5": (0, 3, "slf_op_5"), + "DATAOUT_6": (0, 3, "slf_op_6"), + "DATAOUT_7": (0, 3, "slf_op_7"), + "DATAOUT_8": (0, 4, "slf_op_0"), + "DATAOUT_9": (0, 4, "slf_op_1"), + "MASKWREN_0": (0, 3, "lutff_4/in_0"), + "MASKWREN_1": (0, 3, "lutff_5/in_0"), + "MASKWREN_2": (0, 3, "lutff_6/in_0"), + "MASKWREN_3": (0, 3, "lutff_7/in_0"), + "POWEROFF": (0, 4, "lutff_5/in_3"), + "SLEEP": (0, 4, "lutff_3/in_3"), + "SPRAM_EN": (0, 1, "CBIT_1"), + "STANDBY": (0, 4, "lutff_1/in_3"), + "WREN": (0, 3, "lutff_5/in_1"), + }, + (25, 0, 3): { + "ADDRESS_0": (25, 2, "lutff_0/in_1"), + "ADDRESS_10": (25, 2, "lutff_2/in_0"), + "ADDRESS_11": (25, 2, "lutff_3/in_0"), + "ADDRESS_12": (25, 2, "lutff_4/in_0"), + "ADDRESS_13": (25, 2, "lutff_5/in_0"), + "ADDRESS_1": (25, 2, "lutff_1/in_1"), + "ADDRESS_2": (25, 2, "lutff_2/in_1"), + "ADDRESS_3": (25, 2, "lutff_3/in_1"), + "ADDRESS_4": (25, 2, "lutff_4/in_1"), + "ADDRESS_5": (25, 2, "lutff_5/in_1"), + "ADDRESS_6": (25, 2, "lutff_6/in_1"), + "ADDRESS_7": (25, 2, "lutff_7/in_1"), + "ADDRESS_8": (25, 2, "lutff_0/in_0"), + "ADDRESS_9": (25, 2, "lutff_1/in_0"), + "CHIPSELECT": (25, 3, "lutff_6/in_1"), + "CLOCK": (25, 1, "clk"), + "DATAIN_0": (25, 1, "lutff_0/in_3"), + "DATAIN_10": (25, 1, "lutff_2/in_1"), + "DATAIN_11": (25, 1, "lutff_3/in_1"), + "DATAIN_12": (25, 1, "lutff_4/in_1"), + "DATAIN_13": (25, 1, "lutff_5/in_1"), + "DATAIN_14": (25, 1, "lutff_6/in_1"), + "DATAIN_15": (25, 1, "lutff_7/in_1"), + "DATAIN_1": (25, 1, "lutff_1/in_3"), + "DATAIN_2": (25, 1, "lutff_2/in_3"), + "DATAIN_3": (25, 1, "lutff_3/in_3"), + "DATAIN_4": (25, 1, "lutff_4/in_3"), + "DATAIN_5": (25, 1, "lutff_5/in_3"), + "DATAIN_6": (25, 1, "lutff_6/in_3"), + "DATAIN_7": (25, 1, "lutff_7/in_3"), + "DATAIN_8": (25, 1, "lutff_0/in_1"), + "DATAIN_9": (25, 1, "lutff_1/in_1"), + "DATAOUT_0": (25, 1, "slf_op_0"), + "DATAOUT_10": (25, 2, "slf_op_2"), + "DATAOUT_11": (25, 2, "slf_op_3"), + "DATAOUT_12": (25, 2, "slf_op_4"), + "DATAOUT_13": (25, 2, "slf_op_5"), + "DATAOUT_14": (25, 2, "slf_op_6"), + "DATAOUT_15": (25, 2, "slf_op_7"), + "DATAOUT_1": (25, 1, "slf_op_1"), + "DATAOUT_2": (25, 1, "slf_op_2"), + "DATAOUT_3": (25, 1, "slf_op_3"), + "DATAOUT_4": (25, 1, "slf_op_4"), + "DATAOUT_5": (25, 1, "slf_op_5"), + "DATAOUT_6": (25, 1, "slf_op_6"), + "DATAOUT_7": (25, 1, "slf_op_7"), + "DATAOUT_8": (25, 2, "slf_op_0"), + "DATAOUT_9": (25, 2, "slf_op_1"), + "MASKWREN_0": (25, 3, "lutff_0/in_0"), + "MASKWREN_1": (25, 3, "lutff_1/in_0"), + "MASKWREN_2": (25, 3, "lutff_2/in_0"), + "MASKWREN_3": (25, 3, "lutff_3/in_0"), + "POWEROFF": (25, 4, "lutff_4/in_3"), + "SLEEP": (25, 4, "lutff_2/in_3"), + "SPRAM_EN": (25, 1, "CBIT_0"), + "STANDBY": (25, 4, "lutff_0/in_3"), + "WREN": (25, 3, "lutff_4/in_1"), + }, + (25, 0, 4): { + "ADDRESS_0": (25, 2, "lutff_6/in_0"), + "ADDRESS_10": (25, 3, "lutff_0/in_1"), + "ADDRESS_11": (25, 3, "lutff_1/in_1"), + "ADDRESS_12": (25, 3, "lutff_2/in_1"), + "ADDRESS_13": (25, 3, "lutff_3/in_1"), + "ADDRESS_1": (25, 2, "lutff_7/in_0"), + "ADDRESS_2": (25, 3, "lutff_0/in_3"), + "ADDRESS_3": (25, 3, "lutff_1/in_3"), + "ADDRESS_4": (25, 3, "lutff_2/in_3"), + "ADDRESS_5": (25, 3, "lutff_3/in_3"), + "ADDRESS_6": (25, 3, "lutff_4/in_3"), + "ADDRESS_7": (25, 3, "lutff_5/in_3"), + "ADDRESS_8": (25, 3, "lutff_6/in_3"), + "ADDRESS_9": (25, 3, "lutff_7/in_3"), + "CHIPSELECT": (25, 3, "lutff_7/in_1"), + "CLOCK": (25, 2, "clk"), + "DATAIN_0": (25, 1, "lutff_0/in_0"), + "DATAIN_10": (25, 2, "lutff_2/in_3"), + "DATAIN_11": (25, 2, "lutff_3/in_3"), + "DATAIN_12": (25, 2, "lutff_4/in_3"), + "DATAIN_13": (25, 2, "lutff_5/in_3"), + "DATAIN_14": (25, 2, "lutff_6/in_3"), + "DATAIN_15": (25, 2, "lutff_7/in_3"), + "DATAIN_1": (25, 1, "lutff_1/in_0"), + "DATAIN_2": (25, 1, "lutff_2/in_0"), + "DATAIN_3": (25, 1, "lutff_3/in_0"), + "DATAIN_4": (25, 1, "lutff_4/in_0"), + "DATAIN_5": (25, 1, "lutff_5/in_0"), + "DATAIN_6": (25, 1, "lutff_6/in_0"), + "DATAIN_7": (25, 1, "lutff_7/in_0"), + "DATAIN_8": (25, 2, "lutff_0/in_3"), + "DATAIN_9": (25, 2, "lutff_1/in_3"), + "DATAOUT_0": (25, 3, "slf_op_0"), + "DATAOUT_10": (25, 4, "slf_op_2"), + "DATAOUT_11": (25, 4, "slf_op_3"), + "DATAOUT_12": (25, 4, "slf_op_4"), + "DATAOUT_13": (25, 4, "slf_op_5"), + "DATAOUT_14": (25, 4, "slf_op_6"), + "DATAOUT_15": (25, 4, "slf_op_7"), + "DATAOUT_1": (25, 3, "slf_op_1"), + "DATAOUT_2": (25, 3, "slf_op_2"), + "DATAOUT_3": (25, 3, "slf_op_3"), + "DATAOUT_4": (25, 3, "slf_op_4"), + "DATAOUT_5": (25, 3, "slf_op_5"), + "DATAOUT_6": (25, 3, "slf_op_6"), + "DATAOUT_7": (25, 3, "slf_op_7"), + "DATAOUT_8": (25, 4, "slf_op_0"), + "DATAOUT_9": (25, 4, "slf_op_1"), + "MASKWREN_0": (25, 3, "lutff_4/in_0"), + "MASKWREN_1": (25, 3, "lutff_5/in_0"), + "MASKWREN_2": (25, 3, "lutff_6/in_0"), + "MASKWREN_3": (25, 3, "lutff_7/in_0"), + "POWEROFF": (25, 4, "lutff_5/in_3"), + "SLEEP": (25, 4, "lutff_3/in_3"), + "SPRAM_EN": (25, 1, "CBIT_1"), + "STANDBY": (25, 4, "lutff_1/in_3"), + "WREN": (25, 3, "lutff_5/in_1"), + }, -- cgit v1.2.3 From 614c60df255751b5b1348aae8e64c4035f22c422 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 17 Nov 2017 18:29:14 +0000 Subject: Add missing 5k BRAM bits --- icebox/iceboxdb.py | 345 +++++++++++++++++++++++++++++++- icefuzz/cached_dsp3_5k.txt | 5 + icefuzz/cached_ramb_5k.txt | 486 +++++++++++++++++++++++++++++++++++++++++++++ icefuzz/cached_ramt_5k.txt | 448 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1277 insertions(+), 7 deletions(-) (limited to 'icefuzz') diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index a8b6990..61c0757 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -6742,6 +6742,7 @@ B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 @@ -6749,27 +6750,53 @@ B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 !B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 +!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 +!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 +!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 -!B12[0],B12[1],B13[0] buffer glb_netwk_1 glb2local_3 +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 -B12[0],B12[1],B13[0] buffer glb_netwk_3 glb2local_3 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE -B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 -B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 @@ -6785,6 +6812,7 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 @@ -6797,10 +6825,13 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 @@ -6811,6 +6842,7 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 @@ -6825,25 +6857,34 @@ B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 +B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 @@ -6852,11 +6893,13 @@ B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 @@ -6865,7 +6908,9 @@ B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_ !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 @@ -6877,19 +6922,26 @@ B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDAT !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 @@ -6899,7 +6951,10 @@ B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 @@ -6921,18 +6976,28 @@ B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 @@ -6942,7 +7007,11 @@ B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 @@ -6953,6 +7022,7 @@ B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 @@ -6960,11 +7030,13 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 @@ -6980,6 +7052,7 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 @@ -6990,6 +7063,7 @@ B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 @@ -7004,32 +7078,47 @@ B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 +B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 @@ -7054,7 +7143,9 @@ B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 @@ -7064,12 +7155,15 @@ B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 +!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 @@ -7077,6 +7171,9 @@ B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_ !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -7091,6 +7188,8 @@ B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 @@ -7099,10 +7198,15 @@ B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 @@ -7111,6 +7215,7 @@ B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 @@ -7125,7 +7230,10 @@ B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 @@ -7161,16 +7269,22 @@ B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 B12[19] buffer sp12_h_l_1 sp4_h_r_13 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 B8[2] buffer sp12_h_l_15 sp4_h_l_9 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 B10[2] buffer sp12_h_l_17 sp4_h_r_21 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 @@ -7179,6 +7293,7 @@ B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_r_15 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 B3[1] buffer sp12_h_l_9 sp4_h_r_17 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 @@ -7191,21 +7306,29 @@ B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_r_18 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 B6[2] buffer sp12_h_r_14 sp4_h_l_6 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 B14[2] buffer sp12_h_r_22 sp4_h_r_23 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_r_16 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_b_12 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 @@ -7226,6 +7349,7 @@ B8[19] buffer sp12_v_b_19 sp4_v_t_8 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 B0[19] buffer sp12_v_b_3 sp4_v_b_13 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 @@ -7249,6 +7373,7 @@ B9[19] buffer sp12_v_t_14 sp4_v_b_20 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 B11[19] buffer sp12_v_t_18 sp4_v_t_11 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 B10[19] buffer sp12_v_t_20 sp4_v_b_23 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 @@ -7258,6 +7383,7 @@ B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 B4[19] buffer sp12_v_t_8 sp4_v_t_4 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 @@ -7270,7 +7396,9 @@ B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 @@ -7283,10 +7411,12 @@ B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 @@ -7304,6 +7434,7 @@ B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 @@ -7326,6 +7457,7 @@ B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 @@ -7339,6 +7471,7 @@ B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 @@ -7346,6 +7479,8 @@ B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 @@ -7420,6 +7555,7 @@ B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 @@ -7456,11 +7592,14 @@ B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 @@ -7502,44 +7641,69 @@ B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 +B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 +B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 +B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 +B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 +B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 +B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 +B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 +B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 +B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 @@ -7558,14 +7722,18 @@ B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 +B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 +B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 +B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 +B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 @@ -7578,11 +7746,14 @@ B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 +B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 +B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 +B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 @@ -7590,6 +7761,7 @@ B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 +B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 @@ -8009,20 +8181,38 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 -B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK -B8[0],B8[1],B9[1] buffer glb_netwk_6 glb2local_1 +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 @@ -8033,10 +8223,12 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 @@ -8048,29 +8240,41 @@ B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 @@ -8078,8 +8282,10 @@ B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 @@ -8089,6 +8295,9 @@ B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 @@ -8100,18 +8309,23 @@ B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 +!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 @@ -8123,6 +8337,9 @@ B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 @@ -8132,10 +8349,14 @@ B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 @@ -8143,6 +8364,7 @@ B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 @@ -8150,10 +8372,12 @@ B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 +B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 @@ -8169,17 +8393,24 @@ B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 @@ -8192,25 +8423,35 @@ B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 @@ -8223,6 +8464,7 @@ B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 @@ -8236,6 +8478,8 @@ B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 @@ -8246,9 +8490,12 @@ B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 @@ -8259,6 +8506,7 @@ B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 @@ -8283,6 +8531,7 @@ B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 @@ -8294,10 +8543,12 @@ B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 @@ -8322,6 +8573,7 @@ B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 @@ -8351,6 +8603,7 @@ B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 @@ -8363,6 +8616,7 @@ B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 @@ -8375,12 +8629,14 @@ B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 @@ -8395,10 +8651,12 @@ B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 @@ -8410,47 +8668,82 @@ B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 B6[2] buffer sp12_h_l_13 sp4_h_r_19 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 B14[2] buffer sp12_h_l_21 sp4_h_l_10 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_l_2 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_r_12 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 B3[1] buffer sp12_h_r_10 sp4_h_r_17 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_l_7 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 B8[2] buffer sp12_h_r_16 sp4_h_r_20 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 B10[2] buffer sp12_h_r_18 sp4_h_l_8 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 B12[19] buffer sp12_h_r_2 sp4_h_r_13 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_r_22 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_l_5 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_t_1 @@ -8458,6 +8751,7 @@ B1[19] buffer sp12_v_b_1 sp4_v_t_1 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 B4[19] buffer sp12_v_b_11 sp4_v_b_17 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 @@ -8499,9 +8793,11 @@ B8[19] buffer sp12_v_t_16 sp4_v_t_8 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 @@ -8509,6 +8805,7 @@ B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 @@ -8520,7 +8817,11 @@ B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 @@ -8539,6 +8840,7 @@ B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 @@ -8553,33 +8855,43 @@ B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 @@ -8742,9 +9054,11 @@ B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 @@ -8754,6 +9068,8 @@ B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 @@ -8770,11 +9086,16 @@ B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 +B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 @@ -8798,16 +9119,19 @@ B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 +B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 +B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 +B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 @@ -8842,7 +9166,9 @@ B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 +B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 +B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 @@ -8853,6 +9179,9 @@ B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 +B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 +B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 +B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 @@ -15871,6 +16200,7 @@ B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 @@ -15897,6 +16227,7 @@ B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 diff --git a/icefuzz/cached_dsp3_5k.txt b/icefuzz/cached_dsp3_5k.txt index f42a3f9..0979d71 100644 --- a/icefuzz/cached_dsp3_5k.txt +++ b/icefuzz/cached_dsp3_5k.txt @@ -22,6 +22,7 @@ (0 15) routing glb_netwk_6 wire_mult/lc_7/s_r (0 15) routing lc_trk_g1_5 wire_mult/lc_7/s_r (0 15) routing lc_trk_g3_5 wire_mult/lc_7/s_r +(0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 (0 6) routing glb_netwk_6 glb2local_0 (0 6) routing glb_netwk_7 glb2local_0 @@ -76,6 +77,7 @@ (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 @@ -328,11 +330,13 @@ (13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 +(14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 +(14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 @@ -691,6 +695,7 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt index 65c15e3..85d0e11 100644 --- a/icefuzz/cached_ramb_5k.txt +++ b/icefuzz/cached_ramb_5k.txt @@ -2,17 +2,30 @@ (0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 +(0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_2 glb2local_3 (0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 +(0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/RE +(0 14) routing glb_netwk_6 wire_bram/ram/RE (0 14) routing lc_trk_g2_4 wire_bram/ram/RE (0 14) routing lc_trk_g3_5 wire_bram/ram/RE +(0 15) routing glb_netwk_2 wire_bram/ram/RE +(0 15) routing glb_netwk_6 wire_bram/ram/RE (0 15) routing lc_trk_g1_5 wire_bram/ram/RE (0 15) routing lc_trk_g3_5 wire_bram/ram/RE (0 2) routing glb_netwk_2 wire_bram/ram/RCLK (0 2) routing glb_netwk_3 wire_bram/ram/RCLK +(0 2) routing glb_netwk_6 wire_bram/ram/RCLK (0 2) routing glb_netwk_7 wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/RCLK @@ -26,18 +39,43 @@ (0 4) routing lc_trk_g3_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE +(0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 +(0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_3 glb2local_1 +(0 8) routing glb_netwk_6 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 +(1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 +(1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE @@ -48,6 +86,7 @@ (1 15) routing lc_trk_g3_5 wire_bram/ram/RE (1 2) routing glb_netwk_4 wire_bram/ram/RCLK (1 2) routing glb_netwk_5 wire_bram/ram/RCLK +(1 2) routing glb_netwk_6 wire_bram/ram/RCLK (1 2) routing glb_netwk_7 wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE @@ -59,10 +98,23 @@ (1 5) routing lc_trk_g2_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 +(1 9) routing glb_netwk_6 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 @@ -396,10 +448,13 @@ (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_r_16 lc_trk_g1_0 +(14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 +(14 5) routing sp12_h_l_15 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_h_r_16 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 @@ -414,6 +469,7 @@ (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_l_9 lc_trk_g1_4 +(14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_b_12 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 @@ -426,6 +482,7 @@ (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 +(14 9) routing sp4_h_r_24 lc_trk_g2_0 (14 9) routing sp4_h_r_40 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_b_32 lc_trk_g2_0 @@ -434,7 +491,9 @@ (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 +(15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_t_4 lc_trk_g0_1 +(15 1) routing bot_op_0 lc_trk_g0_0 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -446,7 +505,9 @@ (15 10) routing sp4_h_r_29 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 +(15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 +(15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_b_4 lc_trk_g2_4 (15 11) routing sp4_h_r_28 lc_trk_g2_4 @@ -461,6 +522,8 @@ (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_h_r_33 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 +(15 12) routing tnl_op_1 lc_trk_g3_1 +(15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_r_24 lc_trk_g3_0 @@ -468,6 +531,7 @@ (15 13) routing sp4_h_r_40 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 +(15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_r_29 lc_trk_g3_5 @@ -483,11 +547,14 @@ (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_b_44 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 +(15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 +(15 2) routing sp12_h_l_2 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_21 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 +(15 3) routing bot_op_4 lc_trk_g0_4 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_l_1 lc_trk_g0_4 @@ -503,32 +570,44 @@ (15 5) routing bot_op_0 lc_trk_g1_0 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 +(15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_16 lc_trk_g1_0 +(15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 +(15 6) routing sp12_h_l_2 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_21 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 +(15 7) routing bot_op_4 lc_trk_g1_4 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_l_1 lc_trk_g1_4 (15 7) routing sp4_h_l_9 lc_trk_g1_4 +(15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 +(15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_h_r_33 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 +(15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 +(15 9) routing sp4_h_r_24 lc_trk_g2_0 (15 9) routing sp4_h_r_32 lc_trk_g2_0 (15 9) routing sp4_h_r_40 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 +(15 9) routing tnr_op_0 lc_trk_g2_0 +(16 0) routing sp12_h_l_14 lc_trk_g0_1 +(16 0) routing sp12_h_r_9 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 +(16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 0) routing sp4_v_t_4 lc_trk_g0_1 @@ -546,6 +625,7 @@ (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 +(16 10) routing sp4_v_b_45 lc_trk_g2_5 (16 10) routing sp4_v_t_24 lc_trk_g2_5 (16 11) routing sp12_v_b_20 lc_trk_g2_4 (16 11) routing sp12_v_t_11 lc_trk_g2_4 @@ -587,6 +667,8 @@ (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_b_44 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 +(16 2) routing sp12_h_l_10 lc_trk_g0_5 +(16 2) routing sp12_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 @@ -602,17 +684,23 @@ (16 3) routing sp4_v_b_20 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 4) routing sp12_h_l_14 lc_trk_g1_1 +(16 4) routing sp12_h_r_9 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 4) routing sp4_v_t_4 lc_trk_g1_1 +(16 5) routing sp12_h_l_15 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 +(16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_16 lc_trk_g1_0 +(16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 6) routing sp12_h_l_10 lc_trk_g1_5 +(16 6) routing sp12_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 @@ -623,6 +711,7 @@ (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_l_1 lc_trk_g1_4 (16 7) routing sp4_h_l_9 lc_trk_g1_4 +(16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_12 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 @@ -636,6 +725,7 @@ (16 8) routing sp4_v_t_20 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_t_7 lc_trk_g2_0 +(16 9) routing sp4_h_r_24 lc_trk_g2_0 (16 9) routing sp4_h_r_32 lc_trk_g2_0 (16 9) routing sp4_h_r_40 lc_trk_g2_0 (16 9) routing sp4_v_b_32 lc_trk_g2_0 @@ -643,15 +733,19 @@ (16 9) routing sp4_v_t_13 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 @@ -675,8 +769,10 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 @@ -705,6 +801,8 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 @@ -719,6 +817,7 @@ (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 @@ -748,9 +847,13 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 @@ -759,6 +862,7 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 @@ -775,6 +879,7 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 @@ -786,9 +891,12 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 @@ -796,6 +904,9 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 @@ -805,12 +916,14 @@ (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 @@ -818,6 +931,7 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 @@ -829,11 +943,13 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 @@ -842,13 +958,16 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 +(18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 +(18 1) routing sp12_h_l_14 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 @@ -883,6 +1002,7 @@ (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_t_20 lc_trk_g3_1 +(18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 @@ -900,11 +1020,14 @@ (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 +(18 2) routing sp12_h_l_2 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_h_r_21 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_l_2 lc_trk_g0_5 +(18 3) routing sp12_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 @@ -925,22 +1048,27 @@ (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 +(18 6) routing sp12_h_l_2 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_h_r_21 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_l_2 lc_trk_g1_5 +(18 7) routing sp12_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 +(18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_h_r_33 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 +(18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_t_14 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 @@ -972,6 +1100,7 @@ (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK @@ -988,6 +1117,7 @@ (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_r_3 lc_trk_g0_3 (21 0) routing sp4_h_l_6 lc_trk_g0_3 +(21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 @@ -1000,15 +1130,18 @@ (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_t_4 lc_trk_g2_7 +(21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_b_31 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 +(21 11) routing sp12_v_t_20 lc_trk_g2_7 (21 11) routing sp12_v_t_4 lc_trk_g2_7 (21 11) routing sp4_h_r_31 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 +(21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_b_3 lc_trk_g3_3 @@ -1023,49 +1156,58 @@ (21 13) routing sp4_h_r_43 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_b_35 lc_trk_g3_3 +(21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_t_4 lc_trk_g3_7 (21 14) routing sp4_h_l_26 lc_trk_g3_7 +(21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_b_31 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_t_20 lc_trk_g3_7 (21 15) routing sp12_v_t_4 lc_trk_g3_7 (21 15) routing sp4_h_r_31 lc_trk_g3_7 +(21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_r_7 lc_trk_g0_7 (21 2) routing sp4_h_r_15 lc_trk_g0_7 (21 2) routing sp4_h_r_23 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_20 lc_trk_g0_7 +(21 3) routing sp12_h_r_7 lc_trk_g0_7 (21 3) routing sp4_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_t_2 lc_trk_g0_7 +(21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_r_3 lc_trk_g1_3 (21 4) routing sp4_h_l_6 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 +(21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp12_h_r_3 lc_trk_g1_3 (21 5) routing sp4_h_l_6 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 +(21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_r_7 lc_trk_g1_7 (21 6) routing sp4_h_r_15 lc_trk_g1_7 (21 6) routing sp4_h_r_23 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 +(21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_20 lc_trk_g1_7 (21 7) routing sp12_h_r_7 lc_trk_g1_7 (21 7) routing sp4_h_r_23 lc_trk_g1_7 @@ -1074,11 +1216,14 @@ (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 +(21 8) routing sp12_v_b_3 lc_trk_g2_3 +(21 8) routing sp4_h_l_22 lc_trk_g2_3 (21 8) routing sp4_h_r_43 lc_trk_g2_3 (21 8) routing sp4_v_b_27 lc_trk_g2_3 (21 8) routing sp4_v_b_35 lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_b_19 lc_trk_g2_3 +(21 9) routing sp12_v_b_3 lc_trk_g2_3 (21 9) routing sp4_h_l_14 lc_trk_g2_3 (21 9) routing sp4_h_r_43 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 @@ -1090,6 +1235,7 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 @@ -1097,9 +1243,11 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 @@ -1111,7 +1259,9 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 @@ -1119,6 +1269,8 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 @@ -1147,6 +1299,8 @@ (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 @@ -1161,6 +1315,7 @@ (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 @@ -1168,12 +1323,14 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 @@ -1184,6 +1341,7 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 @@ -1193,6 +1351,7 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1201,9 +1360,11 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 @@ -1212,6 +1373,7 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 @@ -1238,6 +1400,7 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 @@ -1251,19 +1414,26 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1286,14 +1456,17 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_l_6 lc_trk_g0_3 +(23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 0) routing sp4_v_t_6 lc_trk_g0_3 (23 1) routing sp12_h_l_17 lc_trk_g0_2 +(23 1) routing sp12_h_l_9 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 @@ -1301,6 +1474,8 @@ (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_t_12 lc_trk_g2_7 +(23 10) routing sp12_v_t_20 lc_trk_g2_7 +(23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_31 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_31 lc_trk_g2_7 @@ -1334,6 +1509,7 @@ (23 14) routing sp12_v_t_20 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_31 lc_trk_g3_7 +(23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_31 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 14) routing sp4_v_t_34 lc_trk_g3_7 @@ -1342,6 +1518,7 @@ (23 15) routing sp4_h_l_19 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 +(23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 15) routing sp4_v_t_19 lc_trk_g3_6 (23 15) routing sp4_v_t_27 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 @@ -1352,6 +1529,7 @@ (23 2) routing sp4_v_b_23 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 +(23 3) routing sp12_h_r_14 lc_trk_g0_6 (23 3) routing sp12_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_l_11 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 @@ -1384,12 +1562,17 @@ (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 (23 7) routing sp12_h_r_14 lc_trk_g1_6 +(23 7) routing sp12_h_r_22 lc_trk_g1_6 (23 7) routing sp4_h_l_11 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 +(23 7) routing sp4_v_b_14 lc_trk_g1_6 +(23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 7) routing sp4_v_t_11 lc_trk_g1_6 (23 8) routing sp12_v_b_19 lc_trk_g2_3 +(23 8) routing sp12_v_t_8 lc_trk_g2_3 (23 8) routing sp4_h_l_14 lc_trk_g2_3 +(23 8) routing sp4_h_l_22 lc_trk_g2_3 (23 8) routing sp4_h_r_43 lc_trk_g2_3 (23 8) routing sp4_v_b_27 lc_trk_g2_3 (23 8) routing sp4_v_b_35 lc_trk_g2_3 @@ -1405,8 +1588,10 @@ (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_r_3 lc_trk_g0_3 (24 0) routing sp4_h_l_6 lc_trk_g0_3 +(24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_t_6 lc_trk_g0_3 +(24 1) routing bot_op_2 lc_trk_g0_2 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_l_1 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 @@ -1415,9 +1600,12 @@ (24 1) routing sp4_v_t_7 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_t_4 lc_trk_g2_7 +(24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_31 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_t_34 lc_trk_g2_7 +(24 10) routing tnl_op_7 lc_trk_g2_7 +(24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_t_5 lc_trk_g2_6 (24 11) routing sp4_h_l_19 lc_trk_g2_6 @@ -1432,6 +1620,8 @@ (24 12) routing sp4_h_l_22 lc_trk_g3_3 (24 12) routing sp4_h_r_43 lc_trk_g3_3 (24 12) routing sp4_v_b_43 lc_trk_g3_3 +(24 12) routing tnl_op_3 lc_trk_g3_3 +(24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_t_1 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 @@ -1439,24 +1629,30 @@ (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 +(24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_t_4 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_31 lc_trk_g3_7 +(24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_t_34 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 +(24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_t_5 lc_trk_g3_6 (24 15) routing sp4_h_l_19 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 +(24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_r_7 lc_trk_g0_7 (24 2) routing sp4_h_r_15 lc_trk_g0_7 (24 2) routing sp4_h_r_23 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_b_23 lc_trk_g0_7 +(24 3) routing bot_op_6 lc_trk_g0_6 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_11 lc_trk_g0_6 @@ -1482,6 +1678,7 @@ (24 6) routing sp4_h_r_23 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_b_23 lc_trk_g1_7 +(24 7) routing bot_op_6 lc_trk_g1_6 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_11 lc_trk_g1_6 @@ -1489,7 +1686,9 @@ (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_t_11 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 +(24 8) routing sp12_v_b_3 lc_trk_g2_3 (24 8) routing sp4_h_l_14 lc_trk_g2_3 +(24 8) routing sp4_h_l_22 lc_trk_g2_3 (24 8) routing sp4_h_r_43 lc_trk_g2_3 (24 8) routing sp4_v_b_43 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 @@ -1501,6 +1700,7 @@ (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 +(24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_l_1 lc_trk_g0_2 @@ -1593,11 +1793,15 @@ (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_11 lc_trk_g1_6 (25 6) routing sp4_h_l_3 lc_trk_g1_6 +(25 6) routing sp4_v_b_14 lc_trk_g1_6 +(25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 +(25 7) routing sp12_h_r_22 lc_trk_g1_6 (25 7) routing sp4_h_l_11 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 +(25 7) routing sp4_v_b_14 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_t_1 lc_trk_g2_2 @@ -1742,8 +1946,11 @@ (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 +(27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (27 1) routing lc_trk_g1_1 input0_0 @@ -1754,10 +1961,14 @@ (27 1) routing lc_trk_g3_3 input0_0 (27 1) routing lc_trk_g3_5 input0_0 (27 1) routing lc_trk_g3_7 input0_0 +(27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 +(27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 @@ -1784,8 +1995,12 @@ (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 +(27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 @@ -1796,9 +2011,12 @@ (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 +(27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 @@ -1823,7 +2041,10 @@ (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 +(27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_12 +(27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 +(27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 @@ -1837,10 +2058,12 @@ (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 +(27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (27 9) routing lc_trk_g1_1 input0_4 (27 9) routing lc_trk_g1_3 input0_4 @@ -1852,8 +2075,10 @@ (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 +(28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (28 1) routing lc_trk_g2_0 input0_0 @@ -1864,10 +2089,14 @@ (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 +(28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 +(28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 @@ -1895,8 +2124,11 @@ (28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 +(28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 @@ -1906,10 +2138,13 @@ (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 +(28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 @@ -1936,6 +2171,7 @@ (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 +(28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -1949,11 +2185,13 @@ (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 +(28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 +(28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (28 9) routing lc_trk_g2_0 input0_4 (28 9) routing lc_trk_g2_2 input0_4 @@ -1965,12 +2203,18 @@ (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 @@ -1993,11 +2237,18 @@ (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 @@ -2047,15 +2298,21 @@ (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 +(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 @@ -2073,16 +2330,21 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 @@ -2133,9 +2395,15 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -2158,15 +2426,20 @@ (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 @@ -2216,22 +2489,38 @@ (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 +(30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 +(30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 +(30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 +(30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 +(30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 @@ -2250,21 +2539,36 @@ (30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 +(30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 +(30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 +(30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 +(30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 @@ -2281,22 +2585,33 @@ (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 +(30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 +(30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 +(30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 +(30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 +(30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 +(30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 @@ -2305,58 +2620,89 @@ (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 +(31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_15 +(31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 +(31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_10 +(31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_10 +(31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 +(31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_9 +(31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 +(31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_8 +(31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_14 +(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_14 +(31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_14 +(31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 +(31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_13 @@ -2364,25 +2710,40 @@ (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_13 +(31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 +(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_12 +(31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 +(31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_11 +(31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 @@ -2390,39 +2751,60 @@ (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 @@ -2444,10 +2826,16 @@ (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 @@ -2460,34 +2848,44 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 +(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 @@ -2495,37 +2893,57 @@ (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 +(33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 +(33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 +(33 11) routing lc_trk_g2_1 input2_5 (33 11) routing lc_trk_g2_3 input2_5 +(33 11) routing lc_trk_g2_5 input2_5 +(33 11) routing lc_trk_g2_7 input2_5 (33 11) routing lc_trk_g3_0 input2_5 +(33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 +(33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 @@ -2539,10 +2957,14 @@ (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 +(33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (33 15) routing lc_trk_g2_1 input2_7 (33 15) routing lc_trk_g2_3 input2_7 (33 15) routing lc_trk_g2_5 input2_7 +(33 15) routing lc_trk_g2_7 input2_7 (33 15) routing lc_trk_g3_0 input2_7 (33 15) routing lc_trk_g3_2 input2_7 (33 15) routing lc_trk_g3_4 input2_7 @@ -2552,10 +2974,13 @@ (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 +(33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 +(33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 @@ -2563,34 +2988,50 @@ (33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 +(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 +(33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 +(34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 +(34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (34 11) routing lc_trk_g1_0 input2_5 +(34 11) routing lc_trk_g1_2 input2_5 (34 11) routing lc_trk_g1_4 input2_5 +(34 11) routing lc_trk_g1_6 input2_5 (34 11) routing lc_trk_g3_0 input2_5 +(34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 +(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 +(34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 @@ -2601,6 +3042,12 @@ (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 +(34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (34 15) routing lc_trk_g1_0 input2_7 (34 15) routing lc_trk_g1_2 input2_7 @@ -2610,11 +3057,15 @@ (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 +(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 +(34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 +(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 @@ -2626,19 +3077,33 @@ (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 +(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 +(34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 +(35 10) routing lc_trk_g0_5 input2_5 (35 10) routing lc_trk_g0_7 input2_5 (35 10) routing lc_trk_g1_4 input2_5 +(35 10) routing lc_trk_g1_6 input2_5 +(35 10) routing lc_trk_g2_5 input2_5 +(35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 (35 11) routing lc_trk_g0_3 input2_5 (35 11) routing lc_trk_g0_7 input2_5 +(35 11) routing lc_trk_g1_2 input2_5 +(35 11) routing lc_trk_g1_6 input2_5 (35 11) routing lc_trk_g2_3 input2_5 +(35 11) routing lc_trk_g2_7 input2_5 +(35 11) routing lc_trk_g3_2 input2_5 (35 11) routing lc_trk_g3_6 input2_5 (35 12) routing lc_trk_g0_4 input2_6 (35 12) routing lc_trk_g0_6 input2_6 @@ -2661,6 +3126,7 @@ (35 14) routing lc_trk_g1_4 input2_7 (35 14) routing lc_trk_g1_6 input2_7 (35 14) routing lc_trk_g2_5 input2_7 +(35 14) routing lc_trk_g2_7 input2_7 (35 14) routing lc_trk_g3_4 input2_7 (35 14) routing lc_trk_g3_6 input2_7 (35 15) routing lc_trk_g0_3 input2_7 @@ -2668,15 +3134,25 @@ (35 15) routing lc_trk_g1_2 input2_7 (35 15) routing lc_trk_g1_6 input2_7 (35 15) routing lc_trk_g2_3 input2_7 +(35 15) routing lc_trk_g2_7 input2_7 (35 15) routing lc_trk_g3_2 input2_7 (35 15) routing lc_trk_g3_6 input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 +(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 +(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 +(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 +(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 +(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 +(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 +(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 +(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 +(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 @@ -2695,15 +3171,20 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 +(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 +(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 +(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 +(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 +(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 @@ -2785,8 +3266,12 @@ (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 +(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 +(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 +(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 +(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 @@ -2805,6 +3290,7 @@ (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 +(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt index 768ae76..8f2669c 100644 --- a/icefuzz/cached_ramt_5k.txt +++ b/icefuzz/cached_ramt_5k.txt @@ -1,21 +1,34 @@ (0 0) Negative Clock bit (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 +(0 10) routing glb_netwk_7 glb2local_2 +(0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 +(0 11) routing glb_netwk_7 glb2local_2 +(0 12) routing glb_netwk_3 glb2local_3 +(0 12) routing glb_netwk_6 glb2local_3 +(0 12) routing glb_netwk_7 glb2local_3 +(0 13) routing glb_netwk_1 glb2local_3 +(0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 +(0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/WE (0 14) routing glb_netwk_6 wire_bram/ram/WE (0 14) routing lc_trk_g2_4 wire_bram/ram/WE (0 14) routing lc_trk_g3_5 wire_bram/ram/WE +(0 15) routing glb_netwk_2 wire_bram/ram/WE (0 15) routing glb_netwk_6 wire_bram/ram/WE (0 15) routing lc_trk_g1_5 wire_bram/ram/WE (0 15) routing lc_trk_g3_5 wire_bram/ram/WE (0 2) routing glb_netwk_2 wire_bram/ram/WCLK +(0 2) routing glb_netwk_3 wire_bram/ram/WCLK +(0 2) routing glb_netwk_6 wire_bram/ram/WCLK (0 2) routing glb_netwk_7 wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 3) routing glb_netwk_1 wire_bram/ram/WCLK +(0 3) routing glb_netwk_3 wire_bram/ram/WCLK (0 3) routing glb_netwk_5 wire_bram/ram/WCLK (0 3) routing glb_netwk_7 wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/WCLK @@ -25,18 +38,38 @@ (0 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 6) routing glb_netwk_3 glb2local_0 +(0 6) routing glb_netwk_6 glb2local_0 +(0 6) routing glb_netwk_7 glb2local_0 +(0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 +(0 7) routing glb_netwk_7 glb2local_0 +(0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 +(0 9) routing glb_netwk_1 glb2local_1 +(0 9) routing glb_netwk_3 glb2local_1 +(0 9) routing glb_netwk_5 glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 +(1 11) routing glb_netwk_7 glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 +(1 13) routing glb_netwk_6 glb2local_3 +(1 13) routing glb_netwk_7 glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE @@ -49,6 +82,7 @@ (1 15) routing lc_trk_g3_5 wire_bram/ram/WE (1 2) routing glb_netwk_4 wire_bram/ram/WCLK (1 2) routing glb_netwk_5 wire_bram/ram/WCLK +(1 2) routing glb_netwk_6 wire_bram/ram/WCLK (1 2) routing glb_netwk_7 wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE @@ -59,10 +93,23 @@ (1 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 +(1 7) routing glb_netwk_6 glb2local_0 +(1 7) routing glb_netwk_7 glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 9) routing glb_netwk_4 glb2local_1 +(1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 @@ -322,16 +369,20 @@ (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 +(14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 +(14 1) routing sp12_h_r_0 lc_trk_g0_0 +(14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 +(14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_t_3 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 @@ -347,21 +398,31 @@ (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 +(14 12) routing sp12_v_b_0 lc_trk_g3_0 +(14 12) routing sp4_h_l_21 lc_trk_g3_0 (14 12) routing sp4_h_l_29 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 12) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 +(14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 +(14 13) routing sp4_h_l_13 lc_trk_g3_0 (14 13) routing sp4_h_l_29 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 +(14 14) routing sp12_v_t_3 lc_trk_g3_4 +(14 14) routing sp4_h_r_36 lc_trk_g3_4 +(14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_28 lc_trk_g3_4 (14 14) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 +(14 15) routing sp12_v_t_19 lc_trk_g3_4 +(14 15) routing sp12_v_t_3 lc_trk_g3_4 (14 15) routing sp4_h_l_17 lc_trk_g3_4 +(14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 @@ -374,11 +435,13 @@ (14 2) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 +(14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_t_1 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 +(14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_l_5 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 @@ -386,6 +449,7 @@ (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 +(14 5) routing sp12_h_r_16 lc_trk_g1_0 (14 5) routing sp4_h_l_5 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 @@ -399,28 +463,34 @@ (14 6) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 +(14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_t_1 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 +(14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_l_21 lc_trk_g2_0 (14 8) routing sp4_h_l_29 lc_trk_g2_0 (14 8) routing sp4_v_t_13 lc_trk_g2_0 (14 8) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 +(14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_l_13 lc_trk_g2_0 (14 9) routing sp4_h_l_29 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_t_21 lc_trk_g2_0 +(14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 +(15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_b_17 lc_trk_g0_1 (15 1) routing lft_op_0 lc_trk_g0_0 +(15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_l_5 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 @@ -428,10 +498,12 @@ (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_l_16 lc_trk_g2_5 +(15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 +(15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_t_3 lc_trk_g2_4 (15 11) routing sp4_h_l_17 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 @@ -439,13 +511,18 @@ (15 11) routing sp4_v_t_33 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 +(15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 +(15 12) routing sp4_h_l_20 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 +(15 13) routing sp12_v_b_0 lc_trk_g3_0 +(15 13) routing sp4_h_l_13 lc_trk_g3_0 +(15 13) routing sp4_h_l_21 lc_trk_g3_0 (15 13) routing sp4_h_l_29 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 @@ -454,11 +531,15 @@ (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_l_16 lc_trk_g3_5 (15 14) routing sp4_h_r_37 lc_trk_g3_5 +(15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 +(15 15) routing sp12_v_t_3 lc_trk_g3_4 (15 15) routing sp4_h_l_17 lc_trk_g3_4 +(15 15) routing sp4_h_r_36 lc_trk_g3_4 +(15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_t_33 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 @@ -480,6 +561,7 @@ (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_b_17 lc_trk_g1_1 +(15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_l_5 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 @@ -497,6 +579,7 @@ (15 7) routing sp4_h_r_20 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 +(15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_20 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 @@ -505,17 +588,22 @@ (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 +(15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_l_13 lc_trk_g2_0 (15 9) routing sp4_h_l_21 lc_trk_g2_0 (15 9) routing sp4_h_l_29 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 +(15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_6 lc_trk_g0_1 +(16 0) routing sp12_h_r_17 lc_trk_g0_1 +(16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_17 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 +(16 1) routing sp12_h_r_16 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_l_5 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -526,6 +614,7 @@ (16 10) routing sp12_v_b_21 lc_trk_g2_5 (16 10) routing sp12_v_t_10 lc_trk_g2_5 (16 10) routing sp4_h_l_16 lc_trk_g2_5 +(16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_37 lc_trk_g2_5 @@ -540,6 +629,7 @@ (16 11) routing sp4_v_t_33 lc_trk_g2_4 (16 12) routing sp12_v_b_17 lc_trk_g3_1 (16 12) routing sp12_v_b_9 lc_trk_g3_1 +(16 12) routing sp4_h_l_20 lc_trk_g3_1 (16 12) routing sp4_h_l_28 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_v_b_25 lc_trk_g3_1 @@ -547,6 +637,8 @@ (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 +(16 13) routing sp4_h_l_13 lc_trk_g3_0 +(16 13) routing sp4_h_l_21 lc_trk_g3_0 (16 13) routing sp4_h_l_29 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 @@ -555,13 +647,19 @@ (16 14) routing sp12_v_t_10 lc_trk_g3_5 (16 14) routing sp4_h_l_16 lc_trk_g3_5 (16 14) routing sp4_h_r_37 lc_trk_g3_5 +(16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_29 lc_trk_g3_5 (16 14) routing sp4_v_b_37 lc_trk_g3_5 (16 14) routing sp4_v_b_45 lc_trk_g3_5 +(16 15) routing sp12_v_b_12 lc_trk_g3_4 +(16 15) routing sp12_v_t_19 lc_trk_g3_4 (16 15) routing sp4_h_l_17 lc_trk_g3_4 +(16 15) routing sp4_h_r_36 lc_trk_g3_4 +(16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 15) routing sp4_v_t_33 lc_trk_g3_4 +(16 2) routing sp12_h_l_18 lc_trk_g0_5 (16 2) routing sp12_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_l_8 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 @@ -569,6 +667,8 @@ (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 +(16 3) routing sp12_h_r_12 lc_trk_g0_4 +(16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_12 lc_trk_g0_4 (16 3) routing sp4_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 @@ -583,6 +683,7 @@ (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_17 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 +(16 5) routing sp12_h_r_16 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_l_5 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 @@ -590,12 +691,16 @@ (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 +(16 6) routing sp12_h_l_18 lc_trk_g1_5 +(16 6) routing sp12_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_l_8 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 +(16 7) routing sp12_h_r_12 lc_trk_g1_4 +(16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_12 lc_trk_g1_4 (16 7) routing sp4_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 @@ -622,6 +727,8 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 @@ -631,6 +738,8 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 @@ -646,6 +755,7 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 @@ -655,6 +765,7 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 @@ -669,9 +780,11 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 @@ -683,8 +796,11 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 @@ -700,6 +816,7 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 @@ -709,7 +826,12 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 @@ -720,6 +842,7 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 @@ -733,6 +856,8 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 @@ -754,7 +879,9 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 @@ -766,6 +893,8 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 @@ -778,6 +907,8 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 @@ -787,6 +918,7 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 @@ -802,6 +934,7 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 @@ -812,6 +945,7 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 @@ -822,12 +956,15 @@ (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 +(18 1) routing sp12_h_r_17 lc_trk_g0_1 +(18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 +(18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_b_37 lc_trk_g2_5 @@ -840,7 +977,9 @@ (18 11) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 +(18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 +(18 12) routing sp4_h_l_20 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 (18 12) routing sp4_v_b_25 lc_trk_g3_1 (18 12) routing sp4_v_b_33 lc_trk_g3_1 @@ -856,12 +995,14 @@ (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 (18 14) routing sp4_h_r_37 lc_trk_g3_5 +(18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_29 lc_trk_g3_5 (18 14) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_21 lc_trk_g3_5 (18 15) routing sp12_v_b_5 lc_trk_g3_5 (18 15) routing sp4_h_l_16 lc_trk_g3_5 +(18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 @@ -873,6 +1014,7 @@ (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 +(18 3) routing sp12_h_l_18 lc_trk_g0_5 (18 3) routing sp12_h_r_5 lc_trk_g0_5 (18 3) routing sp4_h_l_8 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 @@ -900,12 +1042,14 @@ (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 +(18 7) routing sp12_h_l_18 lc_trk_g1_5 (18 7) routing sp12_h_r_5 lc_trk_g1_5 (18 7) routing sp4_h_l_8 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 +(18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_20 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 @@ -941,8 +1085,10 @@ (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK @@ -956,6 +1102,7 @@ (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 lc_trk_g0_3 +(21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_l_0 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_h_r_19 lc_trk_g0_3 @@ -963,11 +1110,15 @@ (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_0 lc_trk_g0_3 +(21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp4_h_r_19 lc_trk_g0_3 +(21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 +(21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_b_7 lc_trk_g2_7 +(21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_t_18 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 @@ -978,6 +1129,7 @@ (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 +(21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_t_0 lc_trk_g3_3 @@ -996,21 +1148,28 @@ (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_b_7 lc_trk_g3_7 +(21 14) routing sp4_h_l_26 lc_trk_g3_7 +(21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_t_18 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_b_23 lc_trk_g3_7 (21 15) routing sp12_v_b_7 lc_trk_g3_7 (21 15) routing sp4_h_l_18 lc_trk_g3_7 +(21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 +(21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 +(21 2) routing sp12_h_l_4 lc_trk_g0_7 (21 2) routing sp4_h_l_10 lc_trk_g0_7 (21 2) routing sp4_h_l_2 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 +(21 3) routing sp12_h_l_4 lc_trk_g0_7 +(21 3) routing sp12_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_l_10 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 @@ -1024,22 +1183,27 @@ (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_0 lc_trk_g1_3 +(21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp4_h_r_19 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 +(21 6) routing sp12_h_l_4 lc_trk_g1_7 (21 6) routing sp4_h_l_10 lc_trk_g1_7 (21 6) routing sp4_h_l_2 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 +(21 7) routing sp12_h_l_4 lc_trk_g1_7 +(21 7) routing sp12_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_l_10 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 +(21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_t_0 lc_trk_g2_3 (21 8) routing sp4_h_l_30 lc_trk_g2_3 (21 8) routing sp4_h_r_35 lc_trk_g2_3 @@ -1049,13 +1213,18 @@ (21 9) routing sp12_v_t_0 lc_trk_g2_3 (21 9) routing sp12_v_t_16 lc_trk_g2_3 (21 9) routing sp4_h_l_30 lc_trk_g2_3 +(21 9) routing sp4_h_r_27 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 @@ -1063,6 +1232,8 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 @@ -1072,17 +1243,21 @@ (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 @@ -1135,11 +1310,14 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 @@ -1147,6 +1325,7 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 @@ -1158,6 +1337,9 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1168,7 +1350,9 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 @@ -1176,9 +1360,12 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 @@ -1190,16 +1377,22 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 @@ -1210,19 +1403,25 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1244,12 +1443,18 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 lc_trk_g0_3 +(23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_19 lc_trk_g0_3 +(23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_19 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 +(23 1) routing sp12_h_r_10 lc_trk_g0_2 +(23 1) routing sp12_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_l_7 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 @@ -1259,6 +1464,7 @@ (23 10) routing sp12_v_b_23 lc_trk_g2_7 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp4_h_l_18 lc_trk_g2_7 +(23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_47 lc_trk_g2_7 (23 10) routing sp4_v_t_18 lc_trk_g2_7 @@ -1290,22 +1496,28 @@ (23 14) routing sp12_v_b_23 lc_trk_g3_7 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp4_h_l_18 lc_trk_g3_7 +(23 14) routing sp4_h_l_26 lc_trk_g3_7 +(23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_47 lc_trk_g3_7 (23 14) routing sp4_v_t_18 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_t_21 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 +(23 15) routing sp4_h_r_30 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_30 lc_trk_g3_6 (23 15) routing sp4_v_b_38 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 +(23 2) routing sp12_h_l_12 lc_trk_g0_7 +(23 2) routing sp12_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_l_10 lc_trk_g0_7 (23 2) routing sp4_h_l_2 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_10 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 +(23 3) routing sp12_h_l_13 lc_trk_g0_6 (23 3) routing sp12_h_l_21 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_22 lc_trk_g0_6 @@ -1313,6 +1525,8 @@ (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_22 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 +(23 4) routing sp12_h_l_16 lc_trk_g1_3 +(23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_19 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 @@ -1320,25 +1534,33 @@ (23 4) routing sp4_v_b_19 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 5) routing sp12_h_r_10 lc_trk_g1_2 +(23 5) routing sp12_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_l_7 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 +(23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 +(23 6) routing sp12_h_l_12 lc_trk_g1_7 +(23 6) routing sp12_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_l_10 lc_trk_g1_7 (23 6) routing sp4_h_l_2 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_10 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 +(23 7) routing sp12_h_l_13 lc_trk_g1_6 +(23 7) routing sp12_h_l_21 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_22 lc_trk_g1_6 +(23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_22 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 8) routing sp12_v_b_11 lc_trk_g2_3 (23 8) routing sp12_v_t_16 lc_trk_g2_3 (23 8) routing sp4_h_l_30 lc_trk_g2_3 +(23 8) routing sp4_h_r_27 lc_trk_g2_3 (23 8) routing sp4_h_r_35 lc_trk_g2_3 (23 8) routing sp4_v_t_14 lc_trk_g2_3 (23 8) routing sp4_v_t_22 lc_trk_g2_3 @@ -1351,9 +1573,11 @@ (23 9) routing sp4_v_b_26 lc_trk_g2_2 (23 9) routing sp4_v_t_23 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_l_0 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_19 lc_trk_g0_3 +(24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_b_19 lc_trk_g0_3 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_r_2 lc_trk_g0_2 @@ -1361,10 +1585,14 @@ (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 +(24 1) routing top_op_2 lc_trk_g0_2 +(24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_b_7 lc_trk_g2_7 (24 10) routing sp4_h_l_18 lc_trk_g2_7 +(24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_b_47 lc_trk_g2_7 +(24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_b_6 lc_trk_g2_6 @@ -1393,25 +1621,32 @@ (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_b_7 lc_trk_g3_7 (24 14) routing sp4_h_l_18 lc_trk_g3_7 +(24 14) routing sp4_h_l_26 lc_trk_g3_7 +(24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_b_47 lc_trk_g3_7 +(24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_b_6 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 +(24 15) routing sp4_h_r_30 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 +(24 2) routing sp12_h_l_4 lc_trk_g0_7 (24 2) routing sp4_h_l_10 lc_trk_g0_7 (24 2) routing sp4_h_l_2 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_t_10 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 +(24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_3 lc_trk_g0_6 (24 3) routing sp4_h_r_22 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_b_22 lc_trk_g0_6 +(24 3) routing top_op_6 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_l_0 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 @@ -1422,8 +1657,11 @@ (24 5) routing sp12_h_r_2 lc_trk_g1_2 (24 5) routing sp4_h_l_7 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 +(24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 +(24 5) routing top_op_2 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 +(24 6) routing sp12_h_l_4 lc_trk_g1_7 (24 6) routing sp4_h_l_10 lc_trk_g1_7 (24 6) routing sp4_h_l_2 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 @@ -1432,9 +1670,13 @@ (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_22 lc_trk_g1_6 +(24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_b_22 lc_trk_g1_6 +(24 7) routing top_op_6 lc_trk_g1_6 +(24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_t_0 lc_trk_g2_3 (24 8) routing sp4_h_l_30 lc_trk_g2_3 +(24 8) routing sp4_h_r_27 lc_trk_g2_3 (24 8) routing sp4_h_r_35 lc_trk_g2_3 (24 8) routing sp4_v_t_30 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 @@ -1445,6 +1687,7 @@ (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 +(24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 @@ -1454,11 +1697,13 @@ (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 +(25 1) routing sp12_h_r_18 lc_trk_g0_2 (25 1) routing sp12_h_r_2 lc_trk_g0_2 (25 1) routing sp4_h_l_7 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 +(25 1) routing top_op_2 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_b_6 lc_trk_g2_6 @@ -1499,22 +1744,26 @@ (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_6 lc_trk_g3_6 (25 15) routing sp12_v_t_21 lc_trk_g3_6 +(25 15) routing sp4_h_r_30 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 +(25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_3 lc_trk_g0_6 (25 2) routing sp4_h_r_22 lc_trk_g0_6 (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_21 lc_trk_g0_6 +(25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp4_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_b_14 lc_trk_g0_6 +(25 3) routing top_op_6 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_r_2 lc_trk_g1_2 @@ -1523,10 +1772,13 @@ (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 +(25 5) routing sp12_h_r_18 lc_trk_g1_2 (25 5) routing sp12_h_r_2 lc_trk_g1_2 (25 5) routing sp4_h_l_7 lc_trk_g1_2 +(25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 +(25 5) routing top_op_2 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 @@ -1535,10 +1787,13 @@ (25 6) routing sp4_v_b_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 +(25 7) routing sp12_h_l_21 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp4_h_r_22 lc_trk_g1_6 +(25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 +(25 7) routing top_op_6 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_b_2 lc_trk_g2_2 @@ -1553,6 +1808,8 @@ (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_t_23 lc_trk_g2_2 +(25 9) routing tnl_op_2 lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 input0_0 (26 0) routing lc_trk_g0_6 input0_0 (26 0) routing lc_trk_g1_5 input0_0 (26 0) routing lc_trk_g1_7 input0_0 @@ -1687,6 +1944,7 @@ (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 +(27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 (27 1) routing lc_trk_g1_5 input0_0 @@ -1698,6 +1956,7 @@ (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 +(27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 @@ -1743,7 +2002,9 @@ (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 +(27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 @@ -1774,6 +2035,7 @@ (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 +(27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -1788,6 +2050,7 @@ (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_3 +(27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_3 @@ -1809,6 +2072,7 @@ (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 +(28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 (28 1) routing lc_trk_g2_4 input0_0 @@ -1865,6 +2129,7 @@ (28 15) routing lc_trk_g3_2 input0_7 (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 +(28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 @@ -1898,6 +2163,7 @@ (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 +(28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -1942,8 +2208,10 @@ (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 +(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 +(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 @@ -1958,11 +2226,13 @@ (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 +(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 @@ -2051,10 +2321,15 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 +(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 @@ -2112,12 +2387,15 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 +(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2142,7 +2420,9 @@ (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 +(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 @@ -2208,6 +2488,7 @@ (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 +(30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_7 @@ -2215,15 +2496,19 @@ (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 +(30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 +(30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 +(30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 @@ -2260,14 +2545,18 @@ (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 +(30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 +(30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 +(30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 @@ -2288,8 +2577,11 @@ (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 +(30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 +(30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 @@ -2302,6 +2594,7 @@ (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_3 +(30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_3 @@ -2309,40 +2602,63 @@ (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 +(30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 +(31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 +(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_7 +(31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_7 +(31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 +(31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_2 +(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_2 +(31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 +(31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_1 +(31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_0 +(31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 @@ -2350,12 +2666,17 @@ (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_0 +(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_0 +(31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 +(31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 @@ -2363,23 +2684,37 @@ (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_6 +(31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 +(31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_5 +(31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_5 +(31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 +(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_4 +(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_4 @@ -2394,45 +2729,75 @@ (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_3 +(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 +(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 +(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 +(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 +(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 @@ -2451,9 +2816,12 @@ (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 +(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 @@ -2478,8 +2846,14 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 +(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 @@ -2489,23 +2863,38 @@ (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 +(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 +(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 +(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 @@ -2516,12 +2905,17 @@ (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 +(33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 +(33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 +(33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_2 +(33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 @@ -2531,13 +2925,18 @@ (33 11) routing lc_trk_g2_3 input2_5 (33 11) routing lc_trk_g2_5 input2_5 (33 11) routing lc_trk_g2_7 input2_5 +(33 11) routing lc_trk_g3_0 input2_5 (33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 +(33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 +(33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 (33 13) routing lc_trk_g2_4 input2_6 @@ -2546,6 +2945,7 @@ (33 13) routing lc_trk_g3_3 input2_6 (33 13) routing lc_trk_g3_5 input2_6 (33 13) routing lc_trk_g3_7 input2_6 +(33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 @@ -2561,6 +2961,8 @@ (33 15) routing lc_trk_g3_2 input2_7 (33 15) routing lc_trk_g3_4 input2_7 (33 15) routing lc_trk_g3_6 input2_7 +(33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_6 +(33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 @@ -2568,14 +2970,20 @@ (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 +(33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 +(33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 +(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_3 @@ -2586,24 +2994,37 @@ (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 +(34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 +(34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_2 +(34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 +(34 11) routing lc_trk_g1_0 input2_5 +(34 11) routing lc_trk_g1_2 input2_5 +(34 11) routing lc_trk_g1_4 input2_5 +(34 11) routing lc_trk_g1_6 input2_5 +(34 11) routing lc_trk_g3_0 input2_5 (34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 +(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 +(34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 (34 13) routing lc_trk_g1_5 input2_6 @@ -2613,6 +3034,7 @@ (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_0 +(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 @@ -2627,22 +3049,32 @@ (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 +(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 +(34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 +(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 +(34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 +(34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 +(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_3 +(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 @@ -2651,11 +3083,16 @@ (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (35 10) routing lc_trk_g0_5 input2_5 (35 10) routing lc_trk_g0_7 input2_5 +(35 10) routing lc_trk_g1_4 input2_5 +(35 10) routing lc_trk_g1_6 input2_5 (35 10) routing lc_trk_g2_5 input2_5 (35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 +(35 11) routing lc_trk_g0_3 input2_5 (35 11) routing lc_trk_g0_7 input2_5 +(35 11) routing lc_trk_g1_2 input2_5 +(35 11) routing lc_trk_g1_6 input2_5 (35 11) routing lc_trk_g2_3 input2_5 (35 11) routing lc_trk_g2_7 input2_5 (35 11) routing lc_trk_g3_2 input2_5 @@ -2693,16 +3130,21 @@ (35 15) routing lc_trk_g3_2 input2_7 (35 15) routing lc_trk_g3_6 input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 +(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 +(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 +(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 +(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 +(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 @@ -2721,6 +3163,7 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 +(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 @@ -2814,6 +3257,7 @@ (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 +(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 @@ -2821,6 +3265,7 @@ (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 +(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 @@ -2829,6 +3274,7 @@ (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 +(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 @@ -2986,6 +3432,7 @@ (7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 @@ -2994,6 +3441,7 @@ (7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 -- cgit v1.2.3 From da7a2a9d0db95d6a172286eaddd6e930a27ea752 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 20 Nov 2017 09:43:54 +0000 Subject: Fix whitespace and a couple of typos --- examples/up5k_mac16/mac16.pcf | 2 +- examples/up5k_mac16/mac16.v | 2 +- examples/up5k_rgb/rgb.pcf | 2 +- examples/up5k_rgb/rgb.v | 2 +- icebox/icebox.py | 6 +++--- icefuzz/tests/dsp_cbit/.gitignore | 2 +- icefuzz/tests/rgba_drv_cbit/.gitignore | 2 +- icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py | 2 +- icefuzz/tests/spram/.gitignore | 2 +- icefuzz/tests/spram/fuzz_spram.py | 2 +- icepack/icepack.cc | 4 ++-- 11 files changed, 14 insertions(+), 14 deletions(-) (limited to 'icefuzz') diff --git a/examples/up5k_mac16/mac16.pcf b/examples/up5k_mac16/mac16.pcf index 24b9b45..5e21181 100644 --- a/examples/up5k_mac16/mac16.pcf +++ b/examples/up5k_mac16/mac16.pcf @@ -1,4 +1,4 @@ set_io clk 44 set_io rstn 27 set_io LED1 12 -set_io LED2 13 \ No newline at end of file +set_io LED2 13 diff --git a/examples/up5k_mac16/mac16.v b/examples/up5k_mac16/mac16.v index 73740e3..0323fc3 100644 --- a/examples/up5k_mac16/mac16.v +++ b/examples/up5k_mac16/mac16.v @@ -68,4 +68,4 @@ assign LED2 = 1'b0; -endmodule \ No newline at end of file +endmodule diff --git a/examples/up5k_rgb/rgb.pcf b/examples/up5k_rgb/rgb.pcf index cfdb874..0954260 100644 --- a/examples/up5k_rgb/rgb.pcf +++ b/examples/up5k_rgb/rgb.pcf @@ -1,3 +1,3 @@ set_io RGB0 39 set_io RGB1 40 -set_io RGB2 41 \ No newline at end of file +set_io RGB2 41 diff --git a/examples/up5k_rgb/rgb.v b/examples/up5k_rgb/rgb.v index c83b943..81920cb 100644 --- a/examples/up5k_rgb/rgb.v +++ b/examples/up5k_rgb/rgb.v @@ -78,4 +78,4 @@ defparam RGBA_DRIVER.RGB1_CURRENT = "0b000011"; defparam RGBA_DRIVER.RGB2_CURRENT = "0b000011"; -endmodule \ No newline at end of file +endmodule diff --git a/icebox/icebox.py b/icebox/icebox.py index 6b0dfd8..5e94f31 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -642,7 +642,7 @@ class iceconfig: if s[0] == 0 and s[1] == 0: if direction == "l": s = (0, 1, vert_net) if direction == "b": s = (1, 0, horz_net) - + if s[0] == self.max_x and s[1] == self.max_y: if direction == "r": s = (self.max_x, self.max_y-1, vert_net) if direction == "t": s = (self.max_x-1, self.max_y, horz_net) @@ -677,11 +677,11 @@ class iceconfig: if s[0] == 0 and s[1] == self.max_y: if direction == "l": s = (0, self.max_y-1, vert_net) if direction == "t": s = (1, self.max_y, horz_net) - + if s[0] == self.max_x and s[1] == 0: if direction == "r": s = (self.max_x, 1, vert_net) if direction == "b": s = (self.max_x-1, 0, horz_net) - + if self.tile_has_net(s[0], s[1], s[2]): neighbours.add((s[0], s[1], s[2])) diff --git a/icefuzz/tests/dsp_cbit/.gitignore b/icefuzz/tests/dsp_cbit/.gitignore index 83d459d..95ff890 100644 --- a/icefuzz/tests/dsp_cbit/.gitignore +++ b/icefuzz/tests/dsp_cbit/.gitignore @@ -1 +1 @@ -work_dsp_cbit/ \ No newline at end of file +work_dsp_cbit/ diff --git a/icefuzz/tests/rgba_drv_cbit/.gitignore b/icefuzz/tests/rgba_drv_cbit/.gitignore index 68b6394..a0beeed 100644 --- a/icefuzz/tests/rgba_drv_cbit/.gitignore +++ b/icefuzz/tests/rgba_drv_cbit/.gitignore @@ -1 +1 @@ -work_rgba_drv/ \ No newline at end of file +work_rgba_drv/ diff --git a/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py b/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py index a7e2006..3d43ba4 100755 --- a/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py +++ b/icefuzz/tests/rgba_drv_cbit/fuzz_rgba_drv_cbit.py @@ -171,4 +171,4 @@ set_io b_led 41 dat.write(("\"RGBA_DRV_EN\":").ljust(24) + bit_to_str(rgba_drv_en_bit[device]) + ",\n") print(("\"" + fuzz_bit + "\":").ljust(24) + bit_to_str(new_bits[0]) + ",") dat.write(("\"" + fuzz_bit + "\":").ljust(24) + bit_to_str(new_bits[0]) + ",\n") -do_fuzz() \ No newline at end of file +do_fuzz() diff --git a/icefuzz/tests/spram/.gitignore b/icefuzz/tests/spram/.gitignore index c6ebe02..7ce4577 100644 --- a/icefuzz/tests/spram/.gitignore +++ b/icefuzz/tests/spram/.gitignore @@ -1 +1 @@ -work_spram/ \ No newline at end of file +work_spram/ diff --git a/icefuzz/tests/spram/fuzz_spram.py b/icefuzz/tests/spram/fuzz_spram.py index a92a361..05fd828 100755 --- a/icefuzz/tests/spram/fuzz_spram.py +++ b/icefuzz/tests/spram/fuzz_spram.py @@ -171,4 +171,4 @@ with open(device + "_spram_data.txt", "w") as f: for cnet in data[net]: cnets.append("(%d, %d, \"%s\")" % cnet) print("\t\t%s %s, " % (("\"" + net.replace("[","_").replace("]","") + "\":").ljust(24), " ".join(cnets)), file=f) - print("\t},", file=f) \ No newline at end of file + print("\t},", file=f) diff --git a/icepack/icepack.cc b/icepack/icepack.cc index fd3050e..b67241f 100644 --- a/icepack/icepack.cc +++ b/icepack/icepack.cc @@ -1013,7 +1013,7 @@ vector FpgaConfig::chip_cols() const { if (this->device == "384") return vector({18, 54, 54, 54, 54}); if (this->device == "1k") return vector({18, 54, 54, 42, 54, 54, 54}); - // Its ipconect or Mutiplier block, five logic, ram, six logic. + // Its IPConnect or Mutiplier block, five logic, ram, six logic. if (this->device == "5k") return vector({54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54}); if (this->device == "8k") return vector({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54}); panic("Unknown chip type '%s'.\n", this->device.c_str()); @@ -1022,7 +1022,7 @@ vector FpgaConfig::chip_cols() const string FpgaConfig::tile_type(int x, int y) const { if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner"; - // The sides on the 5k devices are ipconect or DSP tiles + // The sides on the 5k devices are IPConnect or DSP tiles if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) { if( (y == 5) || (y == 10) || (y == 15) || (y == 23)) //check ordering here, tile 23-26 might be reversed return "dsp0"; -- cgit v1.2.3