i.MX RT Runtime Support https://git.mciantyre.dev/imxrt-rt/atom?h=main 2025-11-26T15:49:04+00:00 2025-11-26T15:49:04+00:00 Ian McIntyre me@mciantyre.dev 2025-11-26T15:17:14+00:00 urn:sha1:8b0d5278b0de5254a242f8a356f061949a896161 The vector tables exported by imxrt-ral are smaller than the default cortex-m-rt vector table. The tests fail once we enable the rt / device features. With this change, we expect the MCU-dependent vector table sizes. 2025-11-22T16:20:32+00:00 Ian McIntyre me@mciantyre.dev 2025-11-09T16:53:17+00:00 urn:sha1:c4ee315a20e41c234d2d0f7ca3ed7e37a09b9d32 The layout, or assignment of FlexRAM banks to memory regions, is more precise than the count. When a user specifies the count, we still apply the same layout as we always have. But now, by default, we prefer the fuse layout for users who have made no choice. This commit supports RAM loading with probe-rs. After probe-rs resets the MCU and uses the fuse FlexRAM layout, firmware can perfectly match that layout without disrupting the data already copied into RAM by the debugger. 2025-11-11T13:24:39+00:00 Ian McIntyre ianpmcintyre@gmail.com 2023-03-13T13:38:22+00:00 urn:sha1:3a6bbd912c92c277611c7cea5780eb9afb04e451 2025-11-11T13:24:38+00:00 Ian McIntyre ianpmcintyre@gmail.com 2023-03-13T10:50:57+00:00 urn:sha1:6f5633761528e484e8d0963c7ac59403f7210093 Just a proof-of-concept. The new inspect_elf test seems to show that we're building the correct image. We need another commit in order to help the program run in FlexRAM. 2025-09-23T11:52:54+00:00 Ian McIntyre me@mciantyre.dev 2025-09-23T11:52:40+00:00 urn:sha1:439036a6f49663e99779b7c88209999e2b34d28f 2025-09-09T12:55:06+00:00 Ian McIntyre me@mciantyre.dev 2025-09-09T12:29:25+00:00 urn:sha1:ce97696bcd4515b5b2556163aa50c1b4723e7c0f The runtime previously allowed function placement at address 0 in ITCM. However, if you ever formed a pointer to the function placed there, it would look like a null pointer. And you would never be able to call that function if you relied on null pointer optimization. Also, most MCU reference manuals (RM) recommend against this placement. This commit reduces the total capacity of ITCM by 32 bytes, the smallest possible size of a MPU region. Note that this is greater than the RM's recommendation of a four byte reservation. It affects all supported MCUs, except the 1180. If you're so inclined, your MPU could disallow loads, stores, and execution from this reservation. Revised unit tests should cover this change. Additionally, you can manually verify that the ITCM region lengths are reduced by 32 bytes by opening the linker scripts generated by the ELF test suite. 2025-08-03T11:22:19+00:00 Ian McIntyre me@mciantyre.dev 2025-08-03T11:20:01+00:00 urn:sha1:19946bde2f691f26f8e6623a5e08b101ca9309dc 2025-03-22T00:04:24+00:00 Sherif A Abdou sherif_abdou@outlook.com 2025-02-03T15:22:32+00:00 urn:sha1:b319d62052d6b553b135837ff8c35ee0c8d475bf Applications linked through this builder can be placed in a flash reservation. You'll need some other software to launch these programs, since they lack the boot header required by the NXP boot ROM. 2025-03-14T00:14:25+00:00 Ian McIntyre me@mciantyre.dev 2025-03-13T01:50:39+00:00 urn:sha1:4ecbed698241e637a13048a199d29c142445c360 We added the `.xip` section to ensure that the reset handler and pre-init functions would be placed in flash. This commit lets users place other content into that section. `.xip` is intended for instructions. The runtime builder will place these instructions into the same load region as `.text`. However, there's no pre-`main` relocation. Aligning the `.xip` and the `.text` section produces more predictable behavior between GNU's ld and LLVM's lld. 2024-10-18T16:17:35+00:00 Ian McIntyre me@mciantyre.dev 2024-10-18T16:15:23+00:00 urn:sha1:80b9ea634a8e5d6094ef7fe22cb7f75d69e288b7 There's no requirement for 16 byte-aligned read-only data, and this is the only assertion expecting that requirement. Reducing the requirement lets the test pass when the image is built with a Rust 1.82 toolchain.