diff options
| -rw-r--r-- | CHANGELOG.md | 18 | ||||
| -rw-r--r-- | Cargo.toml | 2 | ||||
| -rw-r--r-- | src/host/imxrt-link.x | 6 |
3 files changed, 24 insertions, 2 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 0ae56f7..70c7376 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -21,6 +21,24 @@ true if you only specify the count, or if you make no choice. However, if you specify the layout, the builder guarantees that the FlexRAM banks will match that layout. +### cortex-m-rt 0.7.5 + +Update to cortex-m-rt 0.7.5. The new runtime introduces additional build-time +features. You could enable these features yourself by depending on the same +`cortex-m-rt` package and selecting features. Here's how this runtime supports +each `cortex-m-rt` feature. + +The `paint-stack` feature is not supported. Do not enable this feature. +(Upstream commits suggest that we should be able to support stack painting in a +future release.) + +The `zero-init-ram` feature will zero the VMA region of `.data` before copying +contents from the load region. This isn't particularly useful, but it's safe to +enable. + +This package still enables `set-vtor` and `set-sp` features by default. For +convenience, this package still forwards the `device` feature. + ## [0.1.7] 2025-06-14 Introduce `RuntimeBuilder::in_flash` for creating images that can be launched @@ -18,7 +18,7 @@ device = ["cortex-m-rt/device"] cfg-if = "1.0" [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies] -cortex-m-rt = { version = "=0.7.3", features = ["set-vtor", "set-sp"] } +cortex-m-rt = { version = "=0.7.5", features = ["set-vtor", "set-sp"] } [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dev-dependencies] board = { path = "board" } diff --git a/src/host/imxrt-link.x b/src/host/imxrt-link.x index 7fcd76c..2a5deff 100644 --- a/src/host/imxrt-link.x +++ b/src/host/imxrt-link.x @@ -42,8 +42,9 @@ SECTIONS __estack = .; . += ALIGN(__stack_size, 8); __sstack = .; - /* Symbol expected by cortex-m-rt */ + /* Symbols expected by cortex-m-rt */ _stack_start = __sstack; + _stack_end = __estack; } > REGION_STACK .vector_table : ALIGN(1024) @@ -118,6 +119,9 @@ SECTIONS } > REGION_DATA AT> REGION_LOAD_DATA __sidata = LOADADDR(.data); + _ram_start = __sdata; + _ram_end = __edata; + .bss (NOLOAD) : ALIGN(4) { . = ALIGN(4); |