diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/host.rs | 24 | ||||
| -rw-r--r-- | src/lib.rs | 2 | ||||
| -rw-r--r-- | src/target.rs | 20 |
3 files changed, 31 insertions, 15 deletions
diff --git a/src/host.rs b/src/host.rs index fe2017f..eb10b22 100644 --- a/src/host.rs +++ b/src/host.rs @@ -67,6 +67,7 @@ impl FlexSpi { | Family::Imxrt1040 | Family::Imxrt1050 | Family::Imxrt1060 + | Family::Imxrt1160 | Family::Imxrt1170 | Family::Imxrt1180 => FlexSpi::FlexSpi1, } @@ -94,6 +95,8 @@ impl FlexSpi { Some(0x7000_0000) } // 11xx support + (FlexSpi::FlexSpi1, Family::Imxrt1160) => Some(0x3000_0000), + (FlexSpi::FlexSpi2, Family::Imxrt1160) => Some(0x6000_0000), (FlexSpi::FlexSpi1, Family::Imxrt1170) => Some(0x3000_0000), (FlexSpi::FlexSpi2, Family::Imxrt1170) => Some(0x6000_0000), (FlexSpi::FlexSpi1, Family::Imxrt1180) => Some(0x2800_0000), @@ -513,6 +516,7 @@ impl RuntimeBuilder { | Family::Imxrt1050 | Family::Imxrt1060 | Family::Imxrt1064 + | Family::Imxrt1160 | Family::Imxrt1170 => include_bytes!("host/imxrt-boot-header.x").as_slice(), Family::Imxrt1180 => include_bytes!("host/imxrt-boot-header-1180.x").as_slice(), }; @@ -645,6 +649,7 @@ fn write_flexram_memories( | Family::Imxrt1050 | Family::Imxrt1060 | Family::Imxrt1064 + | Family::Imxrt1160 | Family::Imxrt1170 => 0x00000000, Family::Imxrt1180 => 0x10000000 - itcm_size, }; @@ -736,6 +741,7 @@ pub enum Family { Imxrt1050, Imxrt1060, Imxrt1064, + Imxrt1160, Imxrt1170, Imxrt1180, } @@ -755,6 +761,7 @@ impl Family { Family::Imxrt1050 => 1050, Family::Imxrt1060 => 1060, Family::Imxrt1064 => 1064, + Family::Imxrt1160 => 1160, Family::Imxrt1170 => 1170, Family::Imxrt1180 => 1180, } @@ -766,7 +773,7 @@ impl Family { Family::Imxrt1020 => 8, Family::Imxrt1040 | Family::Imxrt1050 | Family::Imxrt1060 | Family::Imxrt1064 => 16, // No ECC support; treating all banks as equal. - Family::Imxrt1170 => 16, + Family::Imxrt1160 | Family::Imxrt1170 => 16, Family::Imxrt1180 => 2, } } @@ -780,6 +787,7 @@ impl Family { | Family::Imxrt1050 | Family::Imxrt1060 | Family::Imxrt1064 + | Family::Imxrt1160 | Family::Imxrt1170 => 32 * 1024, Family::Imxrt1180 => 128 * 1024, } @@ -795,13 +803,13 @@ impl Family { // 9.5.1. memory maps point at OCRAM2. Family::Imxrt1060 | Family::Imxrt1064 => 0, // Boot ROM uses dedicated OCRAM1. - Family::Imxrt1170 | Family::Imxrt1180 => 0, + Family::Imxrt1160 | Family::Imxrt1170 | Family::Imxrt1180 => 0, } } /// Where's the FlexSPI configuration bank located? fn fcb_offset(self) -> usize { match self { - Family::Imxrt1010 | Family::Imxrt1170 | Family::Imxrt1180 => 0x400, + Family::Imxrt1010 | Family::Imxrt1160 | Family::Imxrt1170 | Family::Imxrt1180 => 0x400, Family::Imxrt1015 | Family::Imxrt1020 | Family::Imxrt1040 @@ -818,6 +826,10 @@ impl Family { match self { // 256 KiB offset from the OCRAM M4 backdoor. Family::Imxrt1170 => 0x2024_0000, + // Using the alias regions, assuming ECC is disabled. + // The two alias regions, plus the ECC region, provide + // the *contiguous* 256 KiB of dedicated OCRAM. + Family::Imxrt1160 => 0x2034_0000, // Skip the first 16 KiB, "cannot be safely used by application images". Family::Imxrt1180 => 0x2048_4000, // Either starts the FlexRAM OCRAM banks, or the @@ -844,6 +856,9 @@ impl Family { | Family::Imxrt1050 => 0, Family::Imxrt1060 | Family::Imxrt1064 => 512 * 1024, // - Two dedicated OCRAMs + // - One FlexRAM OCRAM EC region that's OCRAM when ECC is disabled. + Family::Imxrt1160 => (2 * 64 + 128) * 1024, + // - Two dedicated OCRAMs // - Two dedicated OCRAM ECC regions that aren't used for ECC // - One FlexRAM OCRAM ECC region that's strictly OCRAM, without ECC Family::Imxrt1170 => (2 * 512 + 2 * 64 + 128) * 1024, @@ -874,7 +889,7 @@ impl Family { dtcm: 4, } } - Family::Imxrt1170 => FlexRamBanks { + Family::Imxrt1160 | Family::Imxrt1170 => FlexRamBanks { ocram: 0, itcm: 8, dtcm: 8, @@ -934,6 +949,7 @@ impl FlexRamBanks { | Family::Imxrt1050 | Family::Imxrt1060 | Family::Imxrt1064 + | Family::Imxrt1160 | Family::Imxrt1170 => self.config_gpr(), Family::Imxrt1180 => self.config_1180(), } @@ -145,7 +145,7 @@ //! the 1050, which has the widest spread of bank-to-power domain assignment //! (according to AN12077). //! -//! There is no support for ECC on 1170. The runtime assumes that OCRAM and TCM ECC +//! There is no support for ECC on 1160 or 1170. The runtime assumes that OCRAM and TCM ECC //! is disabled, and that the corresponding memory banks can be used for OCRAM. //! //! The runtime installs a `cortex-m-rt` `pre_init` function to configure the runtime. diff --git a/src/target.rs b/src/target.rs index 0eb1f88..98072e0 100644 --- a/src/target.rs +++ b/src/target.rs @@ -44,13 +44,13 @@ __pre_init: ldr r1, =1180 cmp r0, r1 @ Is this an 1180? beq flexram_1180 - ldr r1, =1170 - cmp r0, r1 @ Is this an 1170? + ldr r1, =1100 + cmp r0, r1 @ Is this an 1160 or 1170? # Disable RTWODOG3. - ite eq - ldreq r2, =0x40038000 @ RTWDOG base address for 11xx chips... - ldrne r2, =0x400BC000 @ RTWDOG base address for 10xx chips... + ite gt + ldrgt r2, =0x40038000 @ RTWDOG base address for 11xx chips... + ldrle r2, =0x400BC000 @ RTWDOG base address for 10xx chips... ldr r3, =0xD928C520 @ RTWDOG magic number str r3, [r2, #4] @ RTWDOG[CNT] = 0xD928C520. ldr r3, [r2] @ r3 = RTWDOG[CS] @@ -60,11 +60,11 @@ __pre_init: # Prepare FlexRAM regions. ldr r0, =0x400AC000 @ IMXRT_IOMUXC_GPR base address for 10xx chips, overwritten if actually 11xx... ldr r1, =__flexram_config @ Value for GPR17 (and GPR18 for 11xx) - itttt eq @ Need a few extra operations to handle 1170 split banks. - ldreq r0, =0x400E4000 @ IMXRT_IOMUXC_GPR base address for 11xx chips, overwrite 10xx address... - lsreq r2, r1, #16 @ r2 = ((unsigned)r1 >> 16) - streq r2, [r0, #72] @ *(IMXRT_IOMUXC_GPR + 18) = r2 - ubfxeq r1, r1, #0, #16 @ r1 = ((unsigned)r1 >> 0) & 0xFFFF, overwrite r1 with lower halfword. + itttt gt @ Need a few extra operations to handle 11xx split banks. + ldrgt r0, =0x400E4000 @ IMXRT_IOMUXC_GPR base address for 11xx chips, overwrite 10xx address... + lsrgt r2, r1, #16 @ r2 = ((unsigned)r1 >> 16) + strgt r2, [r0, #72] @ *(IMXRT_IOMUXC_GPR + 18) = r2 + ubfxgt r1, r1, #0, #16 @ r1 = ((unsigned)r1 >> 0) & 0xFFFF, overwrite r1 with lower halfword. str r1, [r0, #68] @ *(IMXRT_IOMUXC_GPR + 17) = r1 ldr r1, [r0, #64] @ r1 = *(IMXRT_IOMUXC_GPR + 16) orr r1, r1, #1<<2 @ r1 |= 1 << 2 |