From c7a9b9f3d4b9e71303c7b988d2bd916c2e4df9bc Mon Sep 17 00:00:00 2001
From: Ian McIntyre <ianpmcintyre@gmail.com>
Date: Tue, 2 Aug 2022 06:21:12 -0400
Subject: First commit

---
 board/src/shared/imxrt10xx.rs | 35 +++++++++++++++++++++++++++++
 board/src/shared/imxrt11xx.rs | 52 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)
 create mode 100644 board/src/shared/imxrt10xx.rs
 create mode 100644 board/src/shared/imxrt11xx.rs

(limited to 'board/src/shared')

diff --git a/board/src/shared/imxrt10xx.rs b/board/src/shared/imxrt10xx.rs
new file mode 100644
index 0000000..5ba44eb
--- /dev/null
+++ b/board/src/shared/imxrt10xx.rs
@@ -0,0 +1,35 @@
+//! Code shared across all i.MX RT 10xx chips.
+use crate::ral;
+
+pub(crate) fn prepare_pit(timer_delay_microseconds: u32) -> Option<crate::Pit> {
+    #[cfg(feature = "rtic")]
+    {
+        extern "C" {
+            // Not actually mut in cortex-m. But, no one is reading it...
+            static __INTERRUPTS: [core::cell::UnsafeCell<unsafe extern "C" fn()>; 240];
+            fn PIT();
+        }
+        unsafe {
+            __INTERRUPTS[crate::ral::interrupt::PIT as usize]
+                .get()
+                .write_volatile(PIT);
+        }
+    }
+    let ccm = unsafe { ral::ccm::CCM::instance() };
+    // Disable the PIT clock gate while we change the clock...
+    ral::modify_reg!(ral::ccm, ccm, CCGR1, CG6: 0b00);
+    // Set the periodic clock divider, selection.
+    // 24MHz crystal oscillator, divided by 24 == 1MHz PIT clock
+    ral::modify_reg!(
+        ral::ccm,
+        ccm,
+        CSCMR1,
+        PERCLK_PODF: DIVIDE_24,
+        PERCLK_CLK_SEL: PERCLK_CLK_SEL_1 // Oscillator clock
+    );
+    // Re-enable PIT clock
+    ral::modify_reg!(ral::ccm, ccm, CCGR1, CG6: 0b11);
+
+    let pit = unsafe { ral::pit::PIT::instance() };
+    Some(crate::Pit::new(&pit, timer_delay_microseconds))
+}
diff --git a/board/src/shared/imxrt11xx.rs b/board/src/shared/imxrt11xx.rs
new file mode 100644
index 0000000..e0d1074
--- /dev/null
+++ b/board/src/shared/imxrt11xx.rs
@@ -0,0 +1,52 @@
+//! Code shared across all i.MX RT 11xx chips.
+
+use crate::ral;
+
+pub(crate) fn prepare_pit(timer_delay_microseconds: u32) -> Option<crate::Pit> {
+    #[cfg(feature = "rtic")]
+    {
+        extern "C" {
+            // Not actually mut in cortex-m. But, no one is reading it...
+            static __INTERRUPTS: [core::cell::UnsafeCell<unsafe extern "C" fn()>; 240];
+            fn PIT();
+        }
+        unsafe {
+            __INTERRUPTS[crate::ral::Interrupt::PIT1 as usize]
+                .get()
+                .write_volatile(PIT);
+        }
+    }
+
+    let ccm = unsafe { ral::ccm::CCM::instance() };
+
+    // Change the bus clock to the 24 MHz XTAL.
+    // Wouldn't recommend doing this in a real system,
+    // since the bus clock is running rather slowly.
+    // But, it's good enough for a demo, and it lets us match
+    // the behaviors of the 10xx examples.
+    //
+    // If we decrease the bus speed too much, we seem to reach a condition
+    // where we can't re-flash the device. Haven't dug too deeply; only
+    // observed that keeping the bus clock faster lets us flash more reliably,
+    // at least with pyOCD.
+    let clock_root_2 = &ccm.CLOCK_ROOT[2];
+    ral::modify_reg!(ral::ccm::clockroot, clock_root_2, CLOCK_ROOT_CONTROL, MUX: 0b001, DIV: 0);
+    while ral::read_reg!(
+        ral::ccm::clockroot,
+        clock_root_2,
+        CLOCK_ROOT_STATUS0,
+        CHANGING == 1
+    ) {}
+
+    // Enable the clock gate to PIT1.
+    ral::write_reg!(ral::ccm, ccm, LPCG61_DIRECT, 1);
+
+    let pit = unsafe { ral::pit::PIT1::instance() };
+    // 24x scaling accounts for the 24x faster PIT clock.
+    // Looks like it's blinking at 1Hz, but I'm not pulling out
+    // my scope or stopwatch or anything.
+    Some(crate::Pit::new(
+        &pit,
+        timer_delay_microseconds.saturating_mul(24),
+    ))
+}
-- 
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