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<title>rtic/.cargo/config, branch main</title>
<subtitle>Real-Time Interrupt-driven Concurrency (RTIC) framework for ARM Cortex-M microcontrollers
</subtitle>
<id>https://git.mciantyre.dev/rtic/atom?h=main</id>
<link rel='self' href='https://git.mciantyre.dev/rtic/atom?h=main'/>
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<updated>2022-09-27T15:29:03+00:00</updated>
<entry>
<title>.toml and note aboute target</title>
<updated>2022-09-27T15:29:03+00:00</updated>
<author>
<name>Jonas Jacobsson</name>
<email>01joja@gmail.com</email>
</author>
<published>2022-09-27T15:29:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.mciantyre.dev/rtic/commit/?id=ccbaea82aa6a55f6774b6eccad975382900f86d9'/>
<id>urn:sha1:ccbaea82aa6a55f6774b6eccad975382900f86d9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>implement run-pass tests as xtasks</title>
<updated>2021-09-16T14:31:30+00:00</updated>
<author>
<name>Lotte Steenbrink</name>
<email>lotte.steenbrink@ferrous-systems.com</email>
</author>
<published>2021-08-26T08:58:59+00:00</published>
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<id>urn:sha1:d172df6f0a9e105fbb501dc2c044ab685a269246</id>
<content type='text'>
`
</content>
</entry>
<entry>
<title>CI: replace compiletest-rs with trybuild</title>
<updated>2019-11-07T00:05:37+00:00</updated>
<author>
<name>Jorge Aparicio</name>
<email>jorge@japaric.io</email>
</author>
<published>2019-11-07T00:05:37+00:00</published>
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<id>urn:sha1:31b392fe3a6961596a0bd4e1bb24c0da2a9b7b42</id>
<content type='text'>
We use compiletest to run compile-fail tests but compiletest depends on compiler
internals so it breaks every now and then and requires nightly. With trybuild we
can also run compile-fail tests but it works on stable and it already has
reached version 1.0
</content>
</entry>
<entry>
<title>v0.4.0</title>
<updated>2018-11-03T16:16:55+00:00</updated>
<author>
<name>Jorge Aparicio</name>
<email>jorge@japaric.io</email>
</author>
<published>2018-11-03T16:02:41+00:00</published>
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<id>urn:sha1:c631049efcadca8b07940c794cce2be58fa48444</id>
<content type='text'>
closes #32
closes #33
</content>
</entry>
<entry>
<title>Use `true` as the armv6 linker</title>
<updated>2017-09-22T20:44:31+00:00</updated>
<author>
<name>Jonas Schievink</name>
<email>jonasschievink@gmail.com</email>
</author>
<published>2017-09-22T20:44:31+00:00</published>
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<id>urn:sha1:a190da3e3ff63a25a33ac30fc99421ab0decce57</id>
<content type='text'>
Horrible hack until we switch to a Cortex-M0 device crate that works with armv6.
</content>
</entry>
<entry>
<title>update CI</title>
<updated>2017-07-21T04:03:45+00:00</updated>
<author>
<name>Jorge Aparicio</name>
<email>jorge@japaric.io</email>
</author>
<published>2017-07-21T04:03:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.mciantyre.dev/rtic/commit/?id=0788a15a39599dece96ba5d2f8cb15c7e397939a'/>
<id>urn:sha1:0788a15a39599dece96ba5d2f8cb15c7e397939a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>`Resource` trait, docs, examples and rtfm-syntax related changes</title>
<updated>2017-07-21T03:53:44+00:00</updated>
<author>
<name>Jorge Aparicio</name>
<email>jorge@japaric.io</email>
</author>
<published>2017-07-21T03:53:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.mciantyre.dev/rtic/commit/?id=c7b9507a57f2ba28c18b15dd2719a1c56f74a302'/>
<id>urn:sha1:c7b9507a57f2ba28c18b15dd2719a1c56f74a302</id>
<content type='text'>
</content>
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