rtic/book/en/src/internals, branch main Real-Time Interrupt-driven Concurrency (RTIC) framework for ARM Cortex-M microcontrollers https://git.mciantyre.dev/rtic/atom?h=main 2025-03-12T19:41:40+00:00 Adding docs about RISC-V 2025-03-12T19:41:40+00:00 Román Cárdenas Rodríguez rcardenas.rod@gmail.com 2025-02-18T08:39:38+00:00 urn:sha1:5d5ecb95c2dc52b414f5a2aeb3fa77b4089b6320 Disable the playground on all of these 2023-05-11T17:20:58+00:00 datdenkikniet jcdra1@gmail.com 2023-04-23T13:33:56+00:00 urn:sha1:a66540efa014b3716d252612bfc7f8f17ed765c4 Fix this link 2023-05-11T17:20:58+00:00 datdenkikniet jcdra1@gmail.com 2023-04-22T14:24:31+00:00 urn:sha1:16f8ea9ba7d0fed1c9f1622b2e9cbcdbbdd807f5 Fixes for repo rename to rtic 2023-03-02T21:38:25+00:00 Henrik Tjäder henrik@tjaders.com 2023-03-02T21:38:25+00:00 urn:sha1:f03aede2f5a926bdb26d052766492c32454a60dd Book: Fix links, proofread targets and starting_a_project 2023-02-28T23:35:21+00:00 Henrik Tjäder henrik@tjaders.com 2023-02-22T18:03:51+00:00 urn:sha1:d82f57772459d9bf12bb2c935e3ebc9b93368f51 Fix Unicode ✓ 2023-01-04T23:18:48+00:00 Nathan n8tlarsen@gmail.com 2023-01-04T23:18:48+00:00 urn:sha1:baffeaca227e36ccad828a959492b6ccb1c3207a Update example with SRP priority ceiling 2022-12-29T16:21:54+00:00 Nathan n8tlarsen@gmail.com 2022-12-29T16:20:46+00:00 urn:sha1:80b81ef122e68744744df9e866fec3263a0d7e11 Possessive its 2022-12-20T00:18:04+00:00 n8tlarsen 96437952+n8tlarsen@users.noreply.github.com 2022-12-20T00:18:04+00:00 urn:sha1:dd1fb68f425d4bc4712b6c6bfe8313d6270017ff Co-authored-by: Henrik Tjäder <henrik@tjaders.com> typo 2022-12-20T00:17:06+00:00 n8tlarsen 96437952+n8tlarsen@users.noreply.github.com 2022-12-20T00:17:06+00:00 urn:sha1:c688b601f1b447d51398ae3caac8ed5155cdbeb1 Co-authored-by: Henrik Tjäder <henrik@tjaders.com> Clarify BASEPRI and NVIC interaction 2022-12-20T00:16:25+00:00 n8tlarsen 96437952+n8tlarsen@users.noreply.github.com 2022-12-20T00:16:25+00:00 urn:sha1:70ebcc409ff4e34764337a978882a25f34484c4f Co-authored-by: Henrik Tjäder <henrik@tjaders.com>