Real-Time Interrupt-driven Concurrency (RTIC) framework for ARM Cortex-M microcontrollers https://git.mciantyre.dev/rtic/atom?h=main 2025-04-07T21:11:21+00:00 2025-04-07T21:11:21+00:00 Wouter Geraedts git@woutergeraedts.nl 2024-04-09T13:01:27+00:00 urn:sha1:b97bc791260554edfd79dbd84c05815bef26b636 2025-03-12T19:41:40+00:00 Román Cárdenas Rodríguez rcardenas.rod@gmail.com 2024-10-23T16:50:12+00:00 urn:sha1:183e73904a5d14e29f8a7edbb2d9553dddb736af 2024-03-20T20:06:47+00:00 Román Cárdenas Rodríguez rcardenas.rod@gmail.com 2024-03-20T20:06:47+00:00 urn:sha1:4060c3def88f82d4e4f48de7137ce365167ef265 * Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com>