diff options
| -rw-r--r-- | .github/workflows/build.yml | 47 | ||||
| -rw-r--r-- | .github/workflows/clippy-check-example.yml | 20 | ||||
| -rw-r--r-- | rtic-macros/src/codegen/bindings/esp32c3.rs | 7 | ||||
| -rw-r--r-- | rtic-monotonics/src/esp32c3.rs | 6 | ||||
| -rw-r--r-- | rtic/src/export/riscv_esp32c3.rs | 3 |
5 files changed, 27 insertions, 56 deletions
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index a18fcd7..1c7301d 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -74,53 +74,6 @@ jobs: platform: esp32-c3 rustup-target: riscv32imc-unknown-none-elf - # Clippy - # TODO: put in clippy-check-example once esp32-c3 clippy is fixed - clippy: - name: clippy - runs-on: ubuntu-22.04 - strategy: - matrix: - input: - - backend: thumbv7 - platform: lm3s6965 - rustup-target: thumbv7m-none-eabi - - - backend: thumbv6 - platform: lm3s6965 - rustup-target: thumbv6m-none-eabi - - - backend: thumbv8-base - platform: lm3s6965 - rustup-target: thumbv8m.base-none-eabi - - - backend: thumbv8-main - platform: lm3s6965 - rustup-target: thumbv8m.main-none-eabi - - - backend: riscv32-imc-clint - platform: hifive1 - rustup-target: riscv32imc-unknown-none-elf - - - backend: riscv32-imc-mecall - platform: hifive1 - rustup-target: riscv32imc-unknown-none-elf - - steps: - - name: Checkout - uses: actions/checkout@v4 - - - name: Configure Rust target ${{ matrix.input.rustup-target }} - run: rustup target add ${{ matrix.input.rustup-target }} - - - name: Add Rust component clippy - run: rustup component add clippy - - - name: Cache Dependencies - uses: Swatinem/rust-cache@v2 - - - run: cargo xtask --deny-warnings --platform ${{ matrix.input.platform }} --backend ${{ matrix.input.backend }} clippy - buildqemu: name: Get modern QEMU, build and store runs-on: ubuntu-22.04 diff --git a/.github/workflows/clippy-check-example.yml b/.github/workflows/clippy-check-example.yml index 5d44614..e1a5f62 100644 --- a/.github/workflows/clippy-check-example.yml +++ b/.github/workflows/clippy-check-example.yml @@ -53,4 +53,22 @@ jobs: uses: Swatinem/rust-cache@v2 - name: Check the examples - run: cargo xtask example-check --platform ${{ inputs.platform }} --backend ${{ inputs.backend }} ${{ inputs.example-args }}
\ No newline at end of file + run: cargo xtask example-check --platform ${{ inputs.platform }} --backend ${{ inputs.backend }} ${{ inputs.example-args }} + + clippy: + runs-on: ubuntu-22.04 + name: Run clippy + steps: + - name: Checkout + uses: actions/checkout@v4 + + - name: Configure Rust target ${{ inputs.rustup-target }} + run: rustup target add ${{ inputs.rustup-target }} + + - name: Add Rust component clippy + run: rustup component add clippy + + - name: Cache Dependencies + uses: Swatinem/rust-cache@v2 + + - run: cargo xtask --deny-warnings --platform ${{ inputs.platform }} --backend ${{ inputs.backend }} clippy
\ No newline at end of file diff --git a/rtic-macros/src/codegen/bindings/esp32c3.rs b/rtic-macros/src/codegen/bindings/esp32c3.rs index 9c778f9..444f4e3 100644 --- a/rtic-macros/src/codegen/bindings/esp32c3.rs +++ b/rtic-macros/src/codegen/bindings/esp32c3.rs @@ -2,6 +2,7 @@ pub use esp32c3::*; #[cfg(feature = "riscv-esp32c3")] +#[allow(clippy::module_inception)] mod esp32c3 { use crate::{ analyze::Analysis as CodegenAnalysis, @@ -92,7 +93,7 @@ mod esp32c3 { for (&priority, name) in interrupt_ids.chain( app.hardware_tasks .values() - .filter_map(|task| Some((&task.args.priority, &task.args.binds))), + .map(|task| (&task.args.priority, &task.args.binds)), ) { let es = format!( "Maximum priority used by interrupt vector '{name}' is more than supported by hardware" @@ -207,7 +208,7 @@ mod esp32c3 { stmts } - pub fn async_prio_limit(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> { + pub fn async_prio_limit(_app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> { let max = if let Some(max) = analysis.max_async_prio { quote!(#max) } else { @@ -232,7 +233,7 @@ mod esp32c3 { for (_, name) in interrupt_ids.chain( app.hardware_tasks .values() - .filter_map(|task| Some((&task.args.priority, &task.args.binds))), + .map(|task| (&task.args.priority, &task.args.binds)), ) { if *name == dispatcher_name { let ret = &("interrupt".to_owned() + &curr_cpu_id.to_string()); diff --git a/rtic-monotonics/src/esp32c3.rs b/rtic-monotonics/src/esp32c3.rs index 924df2c..51eac83 100644 --- a/rtic-monotonics/src/esp32c3.rs +++ b/rtic-monotonics/src/esp32c3.rs @@ -49,8 +49,8 @@ impl TimerBackend { /// Use the prelude macros instead. pub fn _start(timer: SYSTIMER) { const INTERRUPT_MAP_BASE: u32 = 0x600c2000; - let interrupt_number = 37 as isize; - let cpu_interrupt_number = 31 as isize; + let interrupt_number = 37isize; + let cpu_interrupt_number = 31isize; unsafe { let intr_map_base = INTERRUPT_MAP_BASE as *mut u32; intr_map_base @@ -65,7 +65,7 @@ impl TimerBackend { intr_prio_base .offset(cpu_interrupt_number) - .write_volatile(15 as u32); + .write_volatile(15); } timer.conf().write(|w| w.timer_unit0_work_en().set_bit()); timer diff --git a/rtic/src/export/riscv_esp32c3.rs b/rtic/src/export/riscv_esp32c3.rs index f1b6b63..2af6fc9 100644 --- a/rtic/src/export/riscv_esp32c3.rs +++ b/rtic/src/export/riscv_esp32c3.rs @@ -57,8 +57,7 @@ where pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R) -> R { if ceiling == (15) { //turn off interrupts completely, were at max prio - let r = critical_section::with(|_| f(&mut *ptr)); - r + critical_section::with(|_| f(&mut *ptr)) } else { let current = unsafe { (*INTERRUPT_CORE0::ptr()) |