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2023-01-03Bump everlytic/branch-merge from 1.1.2 to 1.1.5dependabot[bot]
Bumps [everlytic/branch-merge](https://github.com/everlytic/branch-merge) from 1.1.2 to 1.1.5. - [Release notes](https://github.com/everlytic/branch-merge/releases) - [Commits](https://github.com/everlytic/branch-merge/compare/1.1.2...1.1.5) --- updated-dependencies: - dependency-name: everlytic/branch-merge dependency-type: direct:production update-type: version-update:semver-patch ... Signed-off-by: dependabot[bot] <support@github.com>
2023-01-03Bump actions/checkout from 1 to 3dependabot[bot]
Bumps [actions/checkout](https://github.com/actions/checkout) from 1 to 3. - [Release notes](https://github.com/actions/checkout/releases) - [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md) - [Commits](https://github.com/actions/checkout/compare/v1...v3) --- updated-dependencies: - dependency-name: actions/checkout dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com>
2023-01-03Merge #675bors[bot]
675: enable GitHub Dependabot r=AfoHT a=rursprung this ensures that the dependencies are kept up to date. see [the docs][] for further information. [the docs]: https://docs.github.com/en/code-security/dependabot/dependabot-version-updates Co-authored-by: Ralph Ursprung <ralph.ursprung@gmail.com>
2022-12-29Update example with SRP priority ceilingNathan
2022-12-28enable GitHub DependabotRalph Ursprung
this ensures that the dependencies are kept up to date. see [the docs][] for further information. [the docs]: https://docs.github.com/en/code-security/dependabot/dependabot-version-updates
2022-12-22Merge #674bors[bot]
674: CI: Updated to setup-python@v4 r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-21Revert recommended starting templaten8tlarsen
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-21CI: Updated to setup-python@v4Henrik Tjäder
2022-12-21Merge #673bors[bot]
673: CI: Run example tests on thumbv8m.* r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-21CI: Run example tests on thumbv8m.*Henrik Tjäder
2022-12-21Merge #672bors[bot]
672: CI: Update checkout from v2 to v3 r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-21CI: Update checkout from v2 to v3Henrik Tjäder
2022-12-21Merge #671bors[bot]
671: Docs: fancier meeting redirect r=perlindgren a=AfoHT Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-21Add to changelogHenrik Tjäder
2022-12-21Docs: fancier meeting redirectHenrik Tjäder
2022-12-20Merge #669bors[bot]
669: CI: Run rustup and cargo directly r=korken89 a=AfoHT actions-rs seems abandoned: See [link](https://github.com/actions-rs/toolchain/issues/216) As GHA bundles rustup using it directly is trivial Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-19Possessive itsn8tlarsen
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-19typon8tlarsen
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-19Clarify BASEPRI and NVIC interactionn8tlarsen
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-19Expand lock explanationn8tlarsen
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-19Improve basepri explanationn8tlarsen
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-16Add documentation for different targetsNathan
2022-12-16Remove redundant adding of rustfmt componentHenrik Tjäder
2022-12-16Forgot cargo...Henrik Tjäder
2022-12-16ChangelogHenrik Tjäder
2022-12-16Add clippy componentHenrik Tjäder
2022-12-16Bump swatinem/rust-cache to v2Henrik Tjäder
2022-12-16CI: Run rustup and cargo directlyHenrik Tjäder
2022-12-15Merge #668bors[bot]
668: Docs on RTOS r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com> Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
2022-12-15Clippy: Fix (clippy::needless_borrow)Henrik Tjäder
2022-12-15CI: Update to 22.04Henrik Tjäder
2022-12-14Fix CI error caused by `critical-section` 0.2.8Emil Fresk
2022-12-14Docs on RTOSEmil Fresk
2022-09-28Merge #660bors[bot]
660: Clarify r=AfoHT a=01joja I made 3 suggested changes - `.cargo/config` -> `.cargo/config.toml`. Now extensions for vs code recognizes that it is a toml-file. - Moved a note about how to configure target in cargo.toml to by-example.md from app_init.md. - changed all occurrences of `.cargo/config` to `.cargo/config.toml` in the ru and eng version of the book. Co-authored-by: Jonas Jacobsson <01joja@gmail.com>
2022-09-28Merge #661bors[bot]
661: Fix new lint in the compiler r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-09-28Fix new lint in the compilerEmil Fresk
2022-09-27added .toml to .cargo/config in bookJonas Jacobsson
2022-09-27.toml and note aboute targetJonas Jacobsson
2022-07-27Merge #652bors[bot]
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check. Context: [cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33): ``` #[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; ``` [cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21): ``` } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); println!("cargo:rustc-cfg=armv8m_base"); ``` Co-authored-by: David Watson <david@neonquill.com>
2022-07-27Remove use of basepri register on thumbv8m.baseDavid Watson
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-27Merge #653bors[bot]
653: Allow custom `link_section` attributes for late resources r=AfoHT a=vccggorski This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping. Co-authored-by: Gabriel Górski <gabriel.gorski@volvocars.com>
2022-07-27Update CHANGELOG.mdGabriel Górski
2022-07-27Fix missing formattingGabriel Górski
2022-07-06Allow custom `link_section` attributes for late resourcesGabriel Górski
This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping.
2022-06-23Merge #650bors[bot]
650: Release RTIC v1.1.3 r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-06-23Release RTIC v1.1.3Henrik Tjäder
2022-06-23Merge #649bors[bot]
649: Bump rtic-syntax to v1.0.2 and fix Changelog r=korken89 a=AfoHT Use the latest rtic-syntax, update the changelog with the last few undocumented releases Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-06-23Bump rtic-syntax to v1.0.2 and fix ChangelogHenrik Tjäder
2022-06-07Merge #645bors[bot]
645: fix ci: use SYST::PTR r=korken89 a=japaric SYST::ptr has been deprecated in cortex-m v0.7.5 SYST::PTR is available since cortex-m v0.7.0 CI was failing due to a warning turned into an error by `deny(warnings)` Co-authored-by: Jorge Aparicio <jorge.aparicio@ferrous-systems.com>
2022-06-07fix ci: use SYST::PTRJorge Aparicio
SYST::ptr has been deprecated in cortex-m v0.7.5 SYST::PTR is available since cortex-m v0.7.0
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