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2022-12-14Fix CI error caused by `critical-section` 0.2.8Emil Fresk
2022-12-14Docs on RTOSEmil Fresk
2022-09-28Merge #660bors[bot]
660: Clarify r=AfoHT a=01joja I made 3 suggested changes - `.cargo/config` -> `.cargo/config.toml`. Now extensions for vs code recognizes that it is a toml-file. - Moved a note about how to configure target in cargo.toml to by-example.md from app_init.md. - changed all occurrences of `.cargo/config` to `.cargo/config.toml` in the ru and eng version of the book. Co-authored-by: Jonas Jacobsson <01joja@gmail.com>
2022-09-28Merge #661bors[bot]
661: Fix new lint in the compiler r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-09-28Fix new lint in the compilerEmil Fresk
2022-09-27added .toml to .cargo/config in bookJonas Jacobsson
2022-09-27.toml and note aboute targetJonas Jacobsson
2022-07-27Merge #652bors[bot]
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check. Context: [cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33): ``` #[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; ``` [cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21): ``` } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); println!("cargo:rustc-cfg=armv8m_base"); ``` Co-authored-by: David Watson <david@neonquill.com>
2022-07-27Remove use of basepri register on thumbv8m.baseDavid Watson
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-27Merge #653bors[bot]
653: Allow custom `link_section` attributes for late resources r=AfoHT a=vccggorski This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping. Co-authored-by: Gabriel Górski <gabriel.gorski@volvocars.com>
2022-07-27Update CHANGELOG.mdGabriel Górski
2022-07-27Fix missing formattingGabriel Górski
2022-07-06Allow custom `link_section` attributes for late resourcesGabriel Górski
This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping.
2022-06-23Merge #650bors[bot]
650: Release RTIC v1.1.3 r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-06-23Release RTIC v1.1.3Henrik Tjäder
2022-06-23Merge #649bors[bot]
649: Bump rtic-syntax to v1.0.2 and fix Changelog r=korken89 a=AfoHT Use the latest rtic-syntax, update the changelog with the last few undocumented releases Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-06-23Bump rtic-syntax to v1.0.2 and fix ChangelogHenrik Tjäder
2022-06-07Merge #645bors[bot]
645: fix ci: use SYST::PTR r=korken89 a=japaric SYST::ptr has been deprecated in cortex-m v0.7.5 SYST::PTR is available since cortex-m v0.7.0 CI was failing due to a warning turned into an error by `deny(warnings)` Co-authored-by: Jorge Aparicio <jorge.aparicio@ferrous-systems.com>
2022-06-07fix ci: use SYST::PTRJorge Aparicio
SYST::ptr has been deprecated in cortex-m v0.7.5 SYST::PTR is available since cortex-m v0.7.0
2022-05-24Merge #644bors[bot]
644: Fix macros to Rust 2021 r=perlindgren a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-05-24Fix macros to Rust 2021Emil Fresk
2022-05-24Merge #643bors[bot]
643: Fix clash with defmt r=AfoHT a=korken89 Fixes #642 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-05-24Fix clash with defmtEmil Fresk
2022-05-17Merge #641bors[bot]
641: More ergonomic error from static asserts messages r=perlindgren a=korken89 Closes #634 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-05-17More ergonomic error from static asserts messagesEmil Fresk
2022-05-10Merge #638bors[bot]
638: Fixed warning from Rust Analyzer r=perlindgren a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-05-10Fixed warning from Rust AnalyzerEmil Fresk
2022-05-09Merge #637bors[bot]
637: Prepare v1.1.2 r=perlindgren a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-05-09Prepare v1.1.2Emil Fresk
2022-05-02Merge #636bors[bot]
636: Added matrix bot r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-05-02Added matrix botEmil Fresk
2022-04-20Merge #626bors[bot]
626: Fix error in book, shared resource need only `Send` r=korken89 a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-04-20Merge #635bors[bot]
635: Masks take 3 r=AfoHT a=korken89 This solves the `MASKS` generation issue by having `rtic::export` do the feature gating. Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-04-20Added check for resource usage and to generate an compile error for thumbv6 ↵Emil Fresk
exceptions
2022-04-20Masks take 3Emil Fresk
2022-04-13Merge #632bors[bot]
632: Fixed `macro` version r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2022-04-13Fixed `macro` versionEmil Fresk
2022-04-13Merge #630bors[bot]
630: Release RTIC v1.1 r=korken89 a=AfoHT Bump versions, including using using latest rtic-syntax Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-04-13Release RTIC v1.1Henrik Tjäder
Bump versions, including using using latest rtic-syntax
2022-03-20Fix error in book, shared resource need only `Send`Emil Fresk
2022-03-08Merge #624bors[bot]
624: Update software_tasks.md r=korken89 a=RCasatta Co-authored-by: Riccardo Casatta <riccardo.casatta@gmail.com>
2022-03-07Update software_tasks.mdRiccardo Casatta
2022-03-04Merge #589bors[bot]
589: Fine grained concurrency on thumbv6m (no BASEPRI). r=korken89 a=perlindgren This is an experimental implementation of SRP based scheduling on the M0/M0+ (thumbv6m) architecture. The aim is a (sub)-zero abstraction to the resource protection (locking mechanism). Please try, but not merge yet, since its an early POC. Co-authored-by: Per Lindgren <per.lindgren@ltu.se>
2022-03-02Added support for SRP based scheduling for armv6mPer Lindgren
2022-03-01Merge #620bors[bot]
620: Add CHANGELOG instructions and fix incorrectly placed item r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-03-01Merge #617bors[bot]
617: Clippy with pedantic suggestions r=korken89 a=AfoHT Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-02-22Add CHANGELOG instructions and fix incorrectly placed itemHenrik Tjäder
2022-02-22Clippy with pedantic suggestionsHenrik Tjäder
2022-02-22Merge #616bors[bot]
616: rtic::mutex::prelude::* fixes glob import lint r=korken89 a=AfoHT Running cargo Clippy with pedantic rules denied ``` cargo clippy -- --deny clippy::pedantic ``` it will complain: ``` error: usage of wildcard import | 16 | use rtic::mutex_prelude::*; | ^^^^^^^^^^^^^^^^^^^^^^ help: try: `rtic::mutex_prelude::{Mutex, TupleExt01, TupleExt02, TupleExt03, TupleExt04, TupleExt05, TupleExt06, TupleExt07, TupleExt08, TupleExt09, TupleExt10, TupleExt11, TupleExt12, TupleExt13, TupleExt14, TupleExt15, TupleExt16, TupleExt17, TupleExt18, TupleExt19, TupleExt20, TupleExt21, TupleExt22, TupleExt23, TupleExt24, TupleExt25, TupleExt26, TupleExt27, TupleExt28, TupleExt29, TupleExt30, TupleExt31, TupleExt32}` | = note: `-D clippy::wildcard-imports` implied by `-D clippy::pedantic` = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#wildcard_imports error: could not compile --- due to previous error Error: command `cargo clippy -- --deny clippy::all --deny clippy::pedantic` failed, exit status: 101 ``` Looking at the Clippy [wildcard-imports rule](https://rust-lang.github.io/rust-clippy/master/#wildcard_imports) the exception is for wildcards on modules named prelude. Thus, `prelude::*` is OK. Current state: `use rtic-core::prelude as mutex_prelude` almost fits the bill, but `mutex_prelude != prelude`. As this was part of user facing API I don’t think we can remove the current setup, so rtic-core `Mutex`, `Exclusive` and multi-lock `TupleExt0X` retained in old location to be backwards compatible. Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-02-20Provide Mutex relative to prelude to fix doc linking issues coming from ↵Henrik Tjäder
rtic-core
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