| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-07-27 | Remove use of basepri register on thumbv8m.base | David Watson | |
| The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets. | |||
| 2022-05-10 | Fixed warning from Rust Analyzer | Emil Fresk | |
| 2022-04-20 | Added check for resource usage and to generate an compile error for thumbv6 ↵ | Emil Fresk | |
| exceptions | |||
| 2022-04-20 | Masks take 3 | Emil Fresk | |
| 2022-03-02 | Added support for SRP based scheduling for armv6m | Per Lindgren | |
| 2022-02-22 | Clippy with pedantic suggestions | Henrik Tjäder | |
| 2021-12-25 | Clippy lints | Henrik Tjäder | |
| 2021-11-11 | Better errors on when missing to lock shared resources | Emil Fresk | |
| 2021-11-03 | Fixed aliasing in lock impl | Emil Fresk | |
| 2021-11-02 | Fixed aliasing issue due to RacyCell implementation | Emil Fresk | |
| 2021-08-20 | Use `mark_internal_name` by default for methods in `util` to make usage of ↵ | datdenkikniet | |
| these functions more straightforward. fq_ident is always internal rq_ident is always internal monotonic_ident is always internal inputs_ident is always internal local_resources_ident is always internal shared_resources_ident is always internal monotonic_instants_ident is always internal tq_ident is always internal timer_queue_marker_ident is always internal static_shared_resource_ident is always internal static_local_resource_ident is always internal declared_static_local_resource_ident is always internal Only names, not idents, are now marked as internal Use same rtic internal everywhere | |||
| 2021-08-19 | Fixed some lints from Rust Analyzer with experimental proc-macros | Emil Fresk | |
| 2021-07-08 | Cleanup from review (needs releases to compile) | Emil Fresk | |
| 2021-07-06 | Minimal app now compiles | Emil Fresk | |
| 2021-07-05 | Started work | Emil Fresk | |
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index : rtic | |
| Real-Time Interrupt-driven Concurrency (RTIC) framework for ARM Cortex-M microcontrollers |
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