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2022-12-14Fix CI error caused by `critical-section` 0.2.8Emil Fresk
2022-07-27Merge #652bors[bot]
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check. Context: [cortex-m:src/register/mod.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/src/register/mod.rs#L33): ``` #[cfg(all(not(armv6m), not(armv8m_base)))] pub mod basepri; ``` [cortex-m:build.rs](https://github.com/rust-embedded/cortex-m/blob/4e908625204a1e95dd3fd5bdcd8d66d6bc11c3bc/build.rs#L21): ``` } else if target.starts_with("thumbv8m.base") { println!("cargo:rustc-cfg=cortex_m"); println!("cargo:rustc-cfg=armv8m"); println!("cargo:rustc-cfg=armv8m_base"); ``` Co-authored-by: David Watson <david@neonquill.com>
2022-07-27Remove use of basepri register on thumbv8m.baseDavid Watson
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error: ``` error[E0432]: unresolved import `cortex_m::register::basepri` --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5 | 25 | use cortex_m::register::basepri; | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register` ``` This is an attempt to account for the fact that thumbv8m.base (M23) MCUs don't have the BASEPRI register but have more than 32 interrupts. This moves away from the architecture specific config flags and switches to a more functional flag. Make the mask size depend on the max interrupt id Rather than assuming a fixed interrupt count of 32 this code uses an array of u32 bitmasks to calculate the priority mask. The size of this array is calculated at compile time based on the size of the largest interrupt id being used in the target code. For thumbv6m this should be equivalent to the previous version that used a single u32 mask. For thumbv8m.base it will be larger depending on the interrupts used. Don't write 0s to the ISER and ICER registers Writing 0s to these registers is a no-op. Since these masks should be calculated at compile time, this conditional should result in writes being optimized out of the code. Prevent panic on non-arm targets Panicking on unknown targets was breaking things like the doc build on linux. This change should only panic when building on unknown arm targets.
2022-07-27Fix missing formattingGabriel Górski
2022-07-06Allow custom `link_section` attributes for late resourcesGabriel Górski
This commit makes RTIC aware of user-provided `link_section` attributes, letting user override default section mapping.
2022-06-23Bump rtic-syntax to v1.0.2 and fix ChangelogHenrik Tjäder
2022-05-24Fix macros to Rust 2021Emil Fresk
2022-05-24Fix clash with defmtEmil Fresk
2022-05-17More ergonomic error from static asserts messagesEmil Fresk
2022-05-10Fixed warning from Rust AnalyzerEmil Fresk
2022-05-09Prepare v1.1.2Emil Fresk
2022-04-20Added check for resource usage and to generate an compile error for thumbv6 ↵Emil Fresk
exceptions
2022-04-20Masks take 3Emil Fresk
2022-04-13Release RTIC v1.1Henrik Tjäder
Bump versions, including using using latest rtic-syntax
2022-03-02Added support for SRP based scheduling for armv6mPer Lindgren
2022-02-22Clippy with pedantic suggestionsHenrik Tjäder
2022-02-18rtic::mutex::prelude::* fixes glob import lintHenrik Tjäder
rtic-core Mutex, Exclusive and multi-lock retained in old location to not be backwards breaking
2022-02-09Fix/mute clippy errorsHenrik Tjäder
2022-01-28RTIC macro expansion: Try to find target-dirHenrik Tjäder
2021-12-25Merge #565 #566bors[bot]
565: Edition: Bump to 2021 r=korken89 a=AfoHT 566: v1.0.0 r=korken89 a=AfoHT This should fail building until all deps are released and accessible on crates.io (There are some required PRs for edition2021 for each repo, alternatively just bringing in the v1.0 PR should have commits included, we can drop the extra PRs later on) https://github.com/rtic-rs/rtic-monotonic/pull/6 https://github.com/rtic-rs/rtic-core/pull/22 https://github.com/rtic-rs/rtic-syntax/pull/68 Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2021-12-25Bump version to 1.0.0Henrik Tjäder
2021-12-25Clippy lintsHenrik Tjäder
2021-12-14Idle: Switch to NOP instead of WFIHenrik Tjäder
Add example how to get old WFI behaviour
2021-11-25Remove #[deny(warnings)], but deny warnings for CIHenrik Tjäder
2021-11-25Docs: add RTIC logoHenrik Tjäder
2021-11-11Better errors on when missing to lock shared resourcesEmil Fresk
2021-11-09Merge #547bors[bot]
547: New monotonic trait r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2021-11-09Update versions and changelogEmil Fresk
2021-11-09Merge #549bors[bot]
549: fix #543 r=korken89 a=andrewgazelka The remaining PR to fix #543 alongside https://github.com/rtic-rs/rtic-syntax/pull/58 Co-authored-by: Andrew Gazelka <andrew.gazelka@gmail.com>
2021-11-09New monotonic trait workingEmil Fresk
2021-11-08Bump version to 0.6.0-rc.3Henrik Tjäder
2021-11-07Match new rtic-syntax naming of shared and localHenrik Tjäder
2021-11-03fix #543Andrew Gazelka
2021-11-03Fixed aliasing in lock implEmil Fresk
2021-11-03Cleanup of resource initialization, no need to dereferenceEmil Fresk
2021-11-02Fixed aliasing issue due to RacyCell implementationEmil Fresk
2021-09-28Merge #539bors[bot]
539: Prepare rc.2 release r=AfoHT a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2021-09-28Prepare rc.2 releaseEmil Fresk
2021-09-28Fix export of SYSTEmil Fresk
2021-09-27Preparing 0.6.0-rc.1Emil Fresk
2021-09-27Updated codegen for the updated syntax (default monotonic priority)Emil Fresk
2021-09-23The great docs updateEmil Fresk
2021-09-14Merge #525bors[bot]
525: Cleanup export and actually use rtic::export, made fn init inline r=perlindgren a=korken89 Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2021-09-14Cleanup export and actually use rtic::export, made fn init inlineEmil Fresk
2021-08-31style fixJorge Aparicio
2021-08-31validate unused dispatchersJorge Aparicio
closes #521
2021-08-20Merge #516bors[bot]
516: More rustanalyzer lint fixes r=korken89 a=korken89 Found some more Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
2021-08-20More rustanalyzer lint fixesEmil Fresk
2021-08-20Use `mark_internal_name` by default for methods in `util` to make usage of ↵datdenkikniet
these functions more straightforward. fq_ident is always internal rq_ident is always internal monotonic_ident is always internal inputs_ident is always internal local_resources_ident is always internal shared_resources_ident is always internal monotonic_instants_ident is always internal tq_ident is always internal timer_queue_marker_ident is always internal static_shared_resource_ident is always internal static_local_resource_ident is always internal declared_static_local_resource_ident is always internal Only names, not idents, are now marked as internal Use same rtic internal everywhere
2021-08-19Silence rust-analyzer warnings on internal typesHenrik Tjäder
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