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* Fix incorrect end bracket, moved to after pub fn extra_modules
* Clean up - rtic-macros/src/codegen/bindings/esp32c3.rs
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* adjust esp32c3 codegen, bump pac to 0.21.0
* add esp32c3 example
* adjust workflow flags
* CI: Fix esp32c3 comment
* esp32c3: Remove commented out git-dep
* CI: Actually check the ESP32-C3 examples
* Autoformat rtic/cargo.toml
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Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
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* Rebase to master
* using interrupt_mod
* bug fixes
* fix other backends
* Add changelog
* forgot about rtic-macros
* backend-specific configuration
* core peripherals optional over macro argument
* pre_init_preprocessing binding
* CI for RISC-V (WIP)
* separation of concerns
* add targets for RISC-V examples
* remove qemu feature
* prepare examples folder
* move examples all together
* move ci out of examples
* minor changes
* add cortex-m
* new xtask: proof of concept
* fix build.yml
* feature typo
* clean rtic examples
* reproduce weird issue
* remove unsafe code in user app
* update dependencies
* allow builds on riscv32imc
* let's fix QEMU
* Update .github/workflows/build.yml
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* New build.rs
* removing test features
* adapt ui test to new version of clippy
* add more examples to RISC-V backend
* proper configuration of heapless for riscv32imc
* opt-out examples for riscv32imc
* point to new version of riscv-slic
* adapt new macro bindings
* adapt examples and CI to stable
* fix cortex-m CI
* Review
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Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
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