From d82f57772459d9bf12bb2c935e3ebc9b93368f51 Mon Sep 17 00:00:00 2001 From: Henrik Tjäder Date: Wed, 22 Feb 2023 19:03:51 +0100 Subject: Book: Fix links, proofread targets and starting_a_project --- book/en/src/internals/targets.md | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'book/en/src/internals') diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index 04fd592..efad150 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -1,7 +1,7 @@ # Target Architecture -While RTIC can currently target all Cortex-m devices there are some key architecure differences that -users should be aware of. Namely the absence of Base Priority Mask Register (`BASEPRI`) which lends +While RTIC can currently target all Cortex-m devices there are some key architecture differences that +users should be aware of. Namely, the absence of Base Priority Mask Register (`BASEPRI`) which lends itself exceptionally well to the hardware priority ceiling support used in RTIC, in the ARMv6-M and ARMv8-M-base architectures, which forces RTIC to use source masking instead. For each implementation of lock and a detailed commentary of pros and cons, see the implementation of @@ -29,7 +29,7 @@ Table 1 below shows a list of Cortex-m processors and which type of critical sec ## Priority Ceiling -This implementation is covered in depth by the [Critical Sections][critical_sections] page of this book. +This is covered by the [Resources][resources] page of this book. ## Source Masking @@ -55,17 +55,14 @@ with B. ``` At time *t1*, task B locks the shared resource by selectively disabling (using the NVIC) all other -tasks which have a priority equal to or less than any task which shares resouces with B. In effect -this creates a virtual priority ceiling, miroring the `BASEPRI` approach described in the -[Critical Sections][critical_Sections] page. Task A is one such task that shares resources with +tasks which have a priority equal to or less than any task which shares resources with B. In effect +this creates a virtual priority ceiling, mirroring the `BASEPRI` approach. Task A is one such task that shares resources with task B. At time *t2*, task A is either spawned by task B or becomes pending through an interrupt condition, but does not yet preempt task B even though its priority is greater. This is because the -NVIC is preventing it from starting due to task A being being disabled. At time *t3*, task B +NVIC is preventing it from starting due to task A being disabled. At time *t3*, task B releases the lock by re-enabling the tasks in the NVIC. Because task A was pending and has a higher priority than task B, it immediately preempts task B and is free to use the shared resource without risk of data race conditions. At time *t4*, task A completes and returns the execution context to B. Since source masking relies on use of the NVIC, core exception sources such as HardFault, SVCall, PendSV, and SysTick cannot share data with other tasks. - -[critical_sections]: https://github.com/rtic-rs/cortex-m-rtic/blob/master/book/en/src/internals/critical-sections.md -- cgit v1.2.3 From f03aede2f5a926bdb26d052766492c32454a60dd Mon Sep 17 00:00:00 2001 From: Henrik Tjäder Date: Thu, 2 Mar 2023 22:38:25 +0100 Subject: Fixes for repo rename to rtic --- .github/workflows/matrix-bot.yml | 6 +++--- book/en/book.toml | 2 +- book/en/src/by-example/hardware_tasks.md | 2 +- book/en/src/internals/targets.md | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'book/en/src/internals') diff --git a/.github/workflows/matrix-bot.yml b/.github/workflows/matrix-bot.yml index 6ef6787..bc985d9 100644 --- a/.github/workflows/matrix-bot.yml +++ b/.github/workflows/matrix-bot.yml @@ -5,7 +5,7 @@ on: jobs: new-pr: - if: github.event.action == 'opened' && github.repository == 'rtic-rs/cortex-m-rtic' + if: github.event.action == 'opened' && github.repository == 'rtic-rs/rtic' runs-on: ubuntu-latest continue-on-error: true steps: @@ -18,7 +18,7 @@ jobs: server: "matrix.org" merged-pr: - if: github.event.action == 'closed' && github.event.pull_request.merged == true && github.repository == 'rtic-rs/cortex-m-rtic' + if: github.event.action == 'closed' && github.event.pull_request.merged == true && github.repository == 'rtic-rs/rtic' runs-on: ubuntu-latest continue-on-error: true steps: @@ -31,7 +31,7 @@ jobs: server: "matrix.org" abandoned-pr: - if: github.event.action == 'closed' && github.event.pull_request.merged == false && github.repository == 'rtic-rs/cortex-m-rtic' + if: github.event.action == 'closed' && github.event.pull_request.merged == false && github.repository == 'rtic-rs/rtic' runs-on: ubuntu-latest continue-on-error: true steps: diff --git a/book/en/book.toml b/book/en/book.toml index 25f841a..8a89eeb 100644 --- a/book/en/book.toml +++ b/book/en/book.toml @@ -17,6 +17,6 @@ create-missing = false command = "mdbook-mermaid" [output.html] -git-repository-url = "https://github.com/rtic-rs/cortex-m-rtic" +git-repository-url = "https://github.com/rtic-rs/rtic" git-repository-icon = "fa-github" additional-js = ["mermaid.min.js", "mermaid-init.js"] diff --git a/book/en/src/by-example/hardware_tasks.md b/book/en/src/by-example/hardware_tasks.md index c902267..75dd1a4 100644 --- a/book/en/src/by-example/hardware_tasks.md +++ b/book/en/src/by-example/hardware_tasks.md @@ -10,7 +10,7 @@ All tasks bound to an explicit interrupt are called *hardware tasks* since they Specifying a non-existing interrupt name will cause a compilation error. The interrupt names are commonly defined by [PAC or HAL][pacorhal] crates. -Any available interrupt vector should work. Specific devices may bind specific interrupt priorities to specific interrupt vectors outside user code control. See for example the [nRF “softdevice”](https://github.com/rtic-rs/cortex-m-rtic/issues/434). +Any available interrupt vector should work. Specific devices may bind specific interrupt priorities to specific interrupt vectors outside user code control. See for example the [nRF “softdevice”](https://github.com/rtic-rs/rtic/issues/434). Beware of using interrupt vectors that are used internally by hardware features; RTIC is unaware of such hardware specific details. diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index efad150..3562eef 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -7,7 +7,7 @@ ARMv8-M-base architectures, which forces RTIC to use source masking instead. For of lock and a detailed commentary of pros and cons, see the implementation of [lock in src/export.rs][src_export]. -[src_export]: https://github.com/rtic-rs/cortex-m-rtic/blob/master/src/export.rs +[src_export]: https://github.com/rtic-rs/rtic/blob/master/src/export.rs These differences influence how critical sections are realized, but functionality should be the same except that ARMv6-M/ARMv8-M-base cannot have tasks with shared resources bound to exception -- cgit v1.2.3