From 4060c3def88f82d4e4f48de7137ce365167ef265 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?=
 <rcardenas.rod@gmail.com>
Date: Wed, 20 Mar 2024 21:06:47 +0100
Subject: RISC-V support over CLINT (#815)
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* Rebase to master

* using interrupt_mod

* bug fixes

* fix other backends

* Add changelog

* forgot about rtic-macros

* backend-specific configuration

* core peripherals optional over macro argument

* pre_init_preprocessing binding

* CI for RISC-V (WIP)

* separation of concerns

* add targets for RISC-V examples

* remove qemu feature

* prepare examples folder

* move examples all together

* move ci out of examples

* minor changes

* add cortex-m

* new xtask: proof of concept

* fix build.yml

* feature typo

* clean rtic examples

* reproduce weird issue

* remove unsafe code in user app

* update dependencies

* allow builds on riscv32imc

* let's fix QEMU

* Update .github/workflows/build.yml

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>

* New build.rs

* removing test features

* adapt ui test to new version of clippy

* add more examples to RISC-V backend

* proper configuration of heapless for riscv32imc

* opt-out examples for riscv32imc

* point to new version of riscv-slic

* adapt new macro bindings

* adapt examples and CI to stable

* fix cortex-m CI

* Review

---------

Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
---
 rtic-macros/src/codegen/bindings/cortex.rs | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

(limited to 'rtic-macros/src/codegen/bindings/cortex.rs')

diff --git a/rtic-macros/src/codegen/bindings/cortex.rs b/rtic-macros/src/codegen/bindings/cortex.rs
index 69b5ee5..5c56261 100644
--- a/rtic-macros/src/codegen/bindings/cortex.rs
+++ b/rtic-macros/src/codegen/bindings/cortex.rs
@@ -35,6 +35,12 @@ pub fn interrupt_ident() -> Ident {
     Ident::new("interrupt", span)
 }
 
+pub fn interrupt_mod(app: &App) -> TokenStream2 {
+    let device = &app.args.device;
+    let interrupt = interrupt_ident();
+    quote!(#device::#interrupt)
+}
+
 pub fn check_stack_overflow_before_init(
     _app: &App,
     _analysis: &CodegenAnalysis,
@@ -199,12 +205,16 @@ mod basepri {
     }
 }
 
+pub fn pre_init_preprocessing(_app: &mut App, _analysis: &SyntaxAnalysis) -> parse::Result<()> {
+    Ok(())
+}
+
 pub fn pre_init_checks(app: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
     let mut stmts = vec![];
 
     // check that all dispatchers exists in the `Interrupt` enumeration regardless of whether
     // they are used or not
-    let interrupt = util::interrupt_ident();
+    let interrupt = interrupt_ident();
     let rt_err = util::rt_err_ident();
 
     for name in app.args.dispatchers.keys() {
@@ -217,7 +227,7 @@ pub fn pre_init_checks(app: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
 pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
     let mut stmts = vec![];
 
-    let interrupt = util::interrupt_ident();
+    let interrupt = interrupt_ident();
     let rt_err = util::rt_err_ident();
     let device = &app.args.device;
     let nvic_prio_bits = quote!(#device::NVIC_PRIO_BITS);
@@ -381,3 +391,7 @@ pub fn handler_config(
 ) -> Vec<TokenStream2> {
     vec![]
 }
+
+pub fn extra_modules(_app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream2> {
+    vec![]
+}
-- 
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